input rdaddress[13] ;
input wraddress[13] ;
input wren ;
+ input rden ;
output q[8] ;
}
reg r_ram_data[8] = 0 ;
{
+ q = r_ram_data ;
+
/* Write part */
if(wren) {
m_vram[wraddress] := data ;
}
/* Read part */
- q = r_ram_data ;
- r_ram_data := m_vram[rdaddress] ;
+ if(rden) {
+ r_ram_data := m_vram[rdaddress] ;
+ }
}
}
\ No newline at end of file