From 7fdddaceca5a417bd304c82d26ab77337fa840c4 Mon Sep 17 00:00:00 2001 From: yujiro_kaeko Date: Sun, 6 Nov 2011 16:10:00 +0900 Subject: [PATCH] =?utf8?q?=EF=BC=91=EF=BC=8Evga=5Fgen.nsl=20=E4=BF=AE?= =?utf8?q?=E6=AD=A3=E3=80=80320x240=20=E3=83=A2=E3=83=8E=E3=82=AF=E3=83=AD?= =?utf8?q?=E7=94=BB=E9=9D=A2=E7=94=A8=E3=82=AB=E3=82=B9=E3=82=BF=E3=83=A0?= =?utf8?q?=20=E3=83=90=E3=83=83=E3=82=AF=E3=82=A2=E3=83=83=E3=83=97=20?= =?utf8?q?=EF=BC=92=EF=BC=8Evga=5Fram=E3=80=81fifo=E3=82=A2=E3=83=89?= =?utf8?q?=E3=83=AC=E3=82=B9=E7=94=A8FF=E3=81=AE=E3=83=93=E3=83=83?= =?utf8?q?=E3=83=88=E5=B9=85=20=E3=82=A2=E3=83=83=E3=83=97=E3=83=87?= =?utf8?q?=E3=83=BC=E3=83=88?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Change-Id: Ieef69191d6d3125a3b26b614fa4820dabf1e6c17 --- VGADisplay/src/vga_gen.nsl | 10 ++++++---- VGADisplay/src/vga_ram.nsh | 33 +++++++++------------------------ VGADisplay/src/vga_ram.v | 4 ++-- 3 files changed, 17 insertions(+), 30 deletions(-) diff --git a/VGADisplay/src/vga_gen.nsl b/VGADisplay/src/vga_gen.nsl index 31339de..8d4970c 100644 --- a/VGADisplay/src/vga_gen.nsl +++ b/VGADisplay/src/vga_gen.nsl @@ -21,7 +21,7 @@ declare vga_gen interface { input i_clk50 ; // 50MHz main clock - input i_fifo_fst ; // FIFO rst + input i_fifo_rst ; // FIFO rst input m_clock ; input p_reset ; output o_vsync ; // Vertical Sync @@ -74,6 +74,7 @@ module vga_gen { /* VGA Generate Node */ o_vsync = r_vsync ; o_hsync = r_hsync ; + o_vcnt = r_vcnt ; /* FIFO assign */ u_FIFO.i_clk50 = i_clk50 ; @@ -81,7 +82,7 @@ module vga_gen { o_rdack = u_FIFO.o_rdack ; u_FIFO.i_we = fi_fifo_write ; u_FIFO.i_wrdata = i_wrdata ; - u_FIFO.i_rst = i_fifo_fst ; + u_FIFO.i_rst = i_fifo_rst ; u_FIFO.i_re = fs_fifo_read ; /* TEST LED cnt routine */ @@ -134,9 +135,9 @@ module vga_gen { } any { - r_reg_cnt == 0b0 : o_dummy_rgb = 3#(r_data1[r_reg_cnt]) ; + r_reg_cnt == 0b0 : o_dummy_rgb = 3#(r_data1[r_bit_cnt]) ; // (r_reg_cnt == 0b1) - else : o_dummy_rgb = 3#(r_data2[r_reg_cnt]) ; + else : o_dummy_rgb = 3#(r_data2[r_bit_cnt]) ; } } @@ -165,6 +166,7 @@ module vga_gen { o_vga_b = 0 ; r_outcnt := 0 ; r_outclr := 0 ; + o_dummy_rgb = 0 ; } r_hcnt == H_FRONTP_MAX : { r_hsync := 0 ; diff --git a/VGADisplay/src/vga_ram.nsh b/VGADisplay/src/vga_ram.nsh index 92f5412..ce67d23 100644 --- a/VGADisplay/src/vga_ram.nsh +++ b/VGADisplay/src/vga_ram.nsh @@ -1,25 +1,10 @@ -declare vga_ram interface { - input p_reset ; - input m_clock ; - - input i_we1 ; - input i_wrdata1[8] ; - input i_wradrs1[8] ; - - input i_we2 ; - input i_wrdata2[8] ; - input i_wradrs2[8] ; - - output o_rddata1[24] ; - output o_rddata2[24] ; - input i_rdadrs1[8] ; - input i_rdadrs2[8] ; - - input i_clock ; - - input i_re1 ; - input i_re2 ; - - output o_rdack1 ; - output o_rdack2 ; +declare vga_ram interface { + input i_rst ; + input i_clk50 ; + input i_clk25 ; + input i_we ; + input i_wrdata[8] ; + input i_re ; + output o_rddata[8] ; + output o_rdack ; } \ No newline at end of file diff --git a/VGADisplay/src/vga_ram.v b/VGADisplay/src/vga_ram.v index d4c3de7..ea2bf3a 100644 --- a/VGADisplay/src/vga_ram.v +++ b/VGADisplay/src/vga_ram.v @@ -16,8 +16,8 @@ module vga_ram ( output o_rdack ; - reg [9:0] r_wradrs ; - reg [9:0] r_rdadrs ; + reg [8:0] r_wradrs ; + reg [8:0] r_rdadrs ; reg r_rdadrs_buff ; (* remstyle = "no_rw_check" *) reg [7:0] mem1[511:0] ; -- 2.11.0