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[pf3gnuchains/pf3gnuchains3x.git] / libgloss / bfin / include / defBF548.h

diff --git a/libgloss/bfin/include/defBF548.h b/libgloss/bfin/include/defBF548.h
index 88db39f..5a43190 100644 (file)
--- a/libgloss/bfin/include/defBF548.h
+++ b/libgloss/bfin/include/defBF548.h
@@ -13,7 +13,7 @@
 /*
 ** defBF548.h
 **
-** Copyright (C) 2008 Analog Devices, Inc.
+** Copyright (C) 2008, 2009 Analog Devices, Inc.
 **
 ************************************************************************************
 **
@@ -32,6 +32,12 @@
 /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
 #include <defBF54x_base.h>
 
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4:"some macros violate rule 19.4")
+#pragma diag(suppress:misra_rule_19_7:"Allow function-like macros ")
+#endif /* _MISRA_RULES */
+
 /* The following are the #defines needed by ADSP-BF548 that are not in the common header */
 
 /* Timer Registers */
@@ -189,7 +195,7 @@
 #define                         CAN1_EWR  0xffc032b0   /* CAN Controller 1 Programmable Warning Level Register */
 #define                         CAN1_ESR  0xffc032b4   /* CAN Controller 1 Error Status Register */
 #define                       CAN1_UCCNT  0xffc032c4   /* CAN Controller 1 Universal Counter Register */
-#define                        CAN1_UCRC  0xffc032c8   /* CAN Controller 1 Universal Counter Force Reload Register */
+#define                        CAN1_UCRC  0xffc032c8   /* Universal Counter Reload/Capture Register */
 #define                       CAN1_UCCNF  0xffc032cc   /* CAN Controller 1 Universal Counter Configuration Register */
 
 /* CAN Controller 1 Mailbox Acceptance Registers */
@@ -1040,15 +1046,24 @@
 #define                KPAD_ROWEN  0x1c00     /* Row Enable Width */
 #define                KPAD_COLEN  0xe000     /* Column Enable Width */
 
+#ifdef _MISRA_RULES
+#define         SET_KPAD_ROWEN(x)  (((x)&0x7u)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
+#define         SET_KPAD_COLEN(x)  (((x)&0x7u)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
+#else
 #define         SET_KPAD_ROWEN(x)  (((x)&0x7)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
 #define         SET_KPAD_COLEN(x)  (((x)&0x7)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
+#endif /* _MISRA_RULES */
 
 
 /* Bit masks for KPAD_PRESCALE */
 
 #define         KPAD_PRESCALE_VAL  0x3f       /* Key Prescale Value */
 
+#ifdef _MISRA_RULES
+#define      SET_KPAD_PRESCALE(x)  ((x)&0x3Fu)   /* KPAD_PRESCALE_VAL (Key Prescale). Key Prescale Value (5:0) */
+#else
 #define      SET_KPAD_PRESCALE(x)  ((x)&0x3F)   /* KPAD_PRESCALE_VAL (Key Prescale). Key Prescale Value (5:0) */
+#endif /* _MISRA_RULES */
 
 
 /* Bit masks for KPAD_MSEL */
@@ -1056,8 +1071,13 @@
 #define                DBON_SCALE  0xff       /* Debounce Scale Value */
 #define              COLDRV_SCALE  0xff00     /* Column Driver Scale Value */
 
+#ifdef _MISRA_RULES
+#define    SET_KPAD_DBON_SCALE(x)  ((x)&0xFFu)   /* DBON_SCALE (Debounce Scale). Debounce Delay Multiplier Select [7:0] */
+#define  SET_KPAD_COLDRV_SCALE(x)  (((x)&0xFFu)<<8) /* COLDRV_SCALE (Column Driver Scale). Column Driver Period Multiplier Select [15:8] */
+#else
 #define    SET_KPAD_DBON_SCALE(x)  ((x)&0xFF)   /* DBON_SCALE (Debounce Scale). Debounce Delay Multiplier Select [7:0] */
 #define  SET_KPAD_COLDRV_SCALE(x)  (((x)&0xFF)<<8) /* COLDRV_SCALE (Column Driver Scale). Column Driver Period Multiplier Select [15:8] */
+#endif /* _MISRA_RULES */
 
 
 /* Bit masks for KPAD_ROWCOL */
@@ -1930,5 +1950,8 @@
 /*     MULTI BIT MACRO ENUMERATIONS            */
 /* ******************************************* */
 
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
 
 #endif /* _DEF_BF548_H */