ARM: dts: at91: sama5d3: fix maximum peripheral clock rates

[sagit-ice-cold/kernel_xiaomi_msm8998.git] / arch / arm / boot / dts / sama5d3.dtsi

diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index a532791..6b18944 100644 (file)
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -1106,49 +1106,49 @@
                                        usart0_clk: usart0_clk {
                                                #clock-cells = <0>;
                                                reg = <12>;
-                                               atmel,clk-output-range = <0 66000000>;
+                                               atmel,clk-output-range = <0 83000000>;
                                        };
 
                                        usart1_clk: usart1_clk {
                                                #clock-cells = <0>;
                                                reg = <13>;
-                                               atmel,clk-output-range = <0 66000000>;
+                                               atmel,clk-output-range = <0 83000000>;
                                        };
 
                                        usart2_clk: usart2_clk {
                                                #clock-cells = <0>;
                                                reg = <14>;
-                                               atmel,clk-output-range = <0 66000000>;
+                                               atmel,clk-output-range = <0 83000000>;
                                        };
 
                                        usart3_clk: usart3_clk {
                                                #clock-cells = <0>;
                                                reg = <15>;
-                                               atmel,clk-output-range = <0 66000000>;
+                                               atmel,clk-output-range = <0 83000000>;
                                        };
 
                                        uart0_clk: uart0_clk {
                                                #clock-cells = <0>;
                                                reg = <16>;
-                                               atmel,clk-output-range = <0 66000000>;
+                                               atmel,clk-output-range = <0 83000000>;
                                        };
 
                                        twi0_clk: twi0_clk {
                                                reg = <18>;
                                                #clock-cells = <0>;
-                                               atmel,clk-output-range = <0 16625000>;
+                                               atmel,clk-output-range = <0 41500000>;
                                        };
 
                                        twi1_clk: twi1_clk {
                                                #clock-cells = <0>;
                                                reg = <19>;
-                                               atmel,clk-output-range = <0 16625000>;
+                                               atmel,clk-output-range = <0 41500000>;
                                        };
 
                                        twi2_clk: twi2_clk {
                                                #clock-cells = <0>;
                                                reg = <20>;
-                                               atmel,clk-output-range = <0 16625000>;
+                                               atmel,clk-output-range = <0 41500000>;
                                        };
 
                                        mci0_clk: mci0_clk {
@@ -1164,19 +1164,19 @@
                                        spi0_clk: spi0_clk {
                                                #clock-cells = <0>;
                                                reg = <24>;
-                                               atmel,clk-output-range = <0 133000000>;
+                                               atmel,clk-output-range = <0 166000000>;
                                        };
 
                                        spi1_clk: spi1_clk {
                                                #clock-cells = <0>;
                                                reg = <25>;
-                                               atmel,clk-output-range = <0 133000000>;
+                                               atmel,clk-output-range = <0 166000000>;
                                        };
 
                                        tcb0_clk: tcb0_clk {
                                                #clock-cells = <0>;
                                                reg = <26>;
-                                               atmel,clk-output-range = <0 133000000>;
+                                               atmel,clk-output-range = <0 166000000>;
                                        };
 
                                        pwm_clk: pwm_clk {
@@ -1187,7 +1187,7 @@
                                        adc_clk: adc_clk {
                                                #clock-cells = <0>;
                                                reg = <29>;
-                                               atmel,clk-output-range = <0 66000000>;
+                                               atmel,clk-output-range = <0 83000000>;
                                        };
 
                                        dma0_clk: dma0_clk {
@@ -1218,13 +1218,13 @@
                                        ssc0_clk: ssc0_clk {
                                                #clock-cells = <0>;
                                                reg = <38>;
-                                               atmel,clk-output-range = <0 66000000>;
+                                               atmel,clk-output-range = <0 83000000>;
                                        };
 
                                        ssc1_clk: ssc1_clk {
                                                #clock-cells = <0>;
                                                reg = <39>;
-                                               atmel,clk-output-range = <0 66000000>;
+                                               atmel,clk-output-range = <0 83000000>;
                                        };
 
                                        sha_clk: sha_clk {