ARM: tegra: Enable PLLP bypass during Tegra124 LP1

[sagit-ice-cold/kernel_xiaomi_msm8998.git] / arch / arm / mach-tegra / sleep-tegra30.S

diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index 9a2f0b0..c6cf775 100644 (file)
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -379,6 +379,14 @@ _pll_m_c_x_done:
        pll_locked r1, r0, CLK_RESET_PLLC_BASE
        pll_locked r1, r0, CLK_RESET_PLLX_BASE
 
+       tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
+       cmp     r1, #TEGRA30
+       beq     1f
+       ldr     r1, [r0, #CLK_RESET_PLLP_BASE]
+       bic     r1, r1, #(1<<31)        @ disable PllP bypass
+       str     r1, [r0, #CLK_RESET_PLLP_BASE]
+1:
+
        mov32   r7, TEGRA_TMRUS_BASE
        ldr     r1, [r7]
        add     r1, r1, #LOCK_DELAY
@@ -638,7 +646,10 @@ tegra30_switch_cpu_to_clk32k:
        str     r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
 
        /* disable PLLP, PLLA, PLLC and PLLX */
+       tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
+       cmp     r1, #TEGRA30
        ldr     r0, [r5, #CLK_RESET_PLLP_BASE]
+       orrne   r0, r0, #(1 << 31)      @ enable PllP bypass on fast cluster
        bic     r0, r0, #(1 << 30)
        str     r0, [r5, #CLK_RESET_PLLP_BASE]
        ldr     r0, [r5, #CLK_RESET_PLLA_BASE]