/*
* ADS1259
*
- * ADデータSPIエンディアン MSB first
+ * AD
+ * SPIエンディアン MSB first
*/
#include <p24FJ64GA004.h>
#include <libpic30.h>
#include "myspi.h"
#include "myad.h"
-
-#if 0
-// AD DRDY0 INTフラグ 1=INTかかった 0=なし
-static char ad_drdy0_int;
-// AD DRDY0 INTフラグ
-void ad_drdy0_intf_set(void)
-{
- ad_drdy0_int = 1;
-}
-void ad_drdy0_intf_clear(void)
-{
- ad_drdy0_int = 0;
-}
-char ad_is_drdy0_intf(void)
-{
- if (ad_drdy0_int == 1) {
- return 1;
- }
- return 0;
-}
-#endif
-
void ad_cs_init(void)
{
asm("NOP");
asm("NOP");
CS_DATA = 0;
}
-# if 0
-/*
- int cs: 0〜15
- */
-void ad_cs(unsigned char cs)
-{
- unsigned char i;
-
-//CS_CLK = 1;
- for(i = 16; i > 0; i--) {
- if (i == cs+1) {
- CS_DATA = 0;
- } else {
- CS_DATA = 1;
- }
- asm("NOP");
- CS_CLK = 1;
- CS_CLK = 0;
- }
- asm("NOP");
- CS_RCLK = 1;
- asm("NOP");
- CS_DATA = 0;
- asm("NOP");
- CS_RCLK = 0;
-}
-
-void ad_cs_dis(void)
-{
- unsigned char i;
-
- CS_DATA = 1;
- for(i = 16; i > 0; i--) {
- CS_CLK = 1;
- CS_CLK = 0;
- }
- asm("NOP");
- CS_RCLK = 1;
- asm("NOP");
- CS_DATA = 0;
- asm("NOP");
- CS_RCLK = 0;
-}
-#endif
void ad_reset(void)
{
while(spi1_tx_fifo_is_full());
spi1_putc(c);
}
-// polling rcv
-unsigned char ad_spi_rcv(void)
+// polling send/rcv
+unsigned char ad_spi_rcv(unsigned char c)
{
spi1_rx_overrun_clear();
while(spi1_tx_fifo_is_full());
// 前に受信したデータをクリア
spi1_getc();
// 送信
- spi1_putc(0);
+ spi1_putc(c);
// 受信待ち
while(!spi1_rx_fifo_is_full());
return spi1_getc();
{
int cs;
int i;
-for(i = 0; i < AD_CHNUM; i++) {
- cs = AD_CH1_CS + i;
-//1. Send the SDATAC command <11h>. This command cancels the RDATAC mode. RDATAC mode must be
-//cancelled before the register write commands.
-
- ad_cs(cs);
- ad_spi_send(ADCMD_SDATAC);
- ad_cs_dis();
-//2. Send the register write command. The following example shows the register write as a block of nine bytes,
-//starting at register 0 (CONFIG0).
- ad_cs(cs);
- ad_spi_send(ADCMD_WREG | 0); // Register write command
- ad_spi_send(9 - 1); // 9byte write
- // CONFIG0: RFBIAS OFF, SPI timeout enable
- // Bit 2 RBIAS: Internal reference bias
- // 0 = Internal reference bias disabled
- // 1 = Internal reference bias enabled (default)
- // Bit 0 SPI: SCLK timeout of SPI interface
- // 0 = SPI timeout disabled
- // 1 = SPI timeout enabled (default), when SCLK is held low for 216 clock cycles
- // bit76543210
- ad_spi_send(0b00000101);
- // CONFIG1: sinc1 filter, EXTREF ON, START delay = 0
- // Bit 6 CHKSUM: Checksum
- // 0 = Disabled (default)
- // 1 = Conversion data checksum byte included in readback
- // Bit 4 SINC2: Digital filter mode
- // 0 = sinc1 filter (default)
- // 1 = sinc2 filter
- // Bit 3 EXTREF: Reference select
- // 0 = Internal
- // 1 = External (default)
- // Bits 2-0 DELAY[2:0]: START conversion delay
- // 000 = No delay (default)
- // bit76543210
- ad_spi_send(0b00001000);
-
-
- // CONFIG2: SYNCOUT ON, Gate control, DataRate=10Hz
- // Bit 5 SYNCOUT: SYNCOUT clock enable
- // 0 = SYNCOUT disabled (default)
- // 1 = SYNCOUT enabled
- // Bit 4 PULSE: Conversion Control mode select
- // 0 = Gate Control mode (default)
- // 1 = Pulse Control mode
- // Bits 2-0 DR[2:0] Data rate setting
- // 000 = 10SPS (default)
- // 001 = 16.6SPS
- // 010 = 50SPS
- // 011 = 60SPS
- // 100 = 400SPS
- // 101 = 1200SPS
- // 110 = 3600SPS
- // 111 = 14400SPS
- // NOTE: fCLK = 7.3728MHz
- unsigned char rate_bit;
- switch(AD_SAMPLE) {
- case 50:
- rate_bit = 0b00000010;
- break;
- case 400:
- rate_bit = 0b00000100;
- break;
- default:
- case 10:
- rate_bit = 0b00000000;
- break;
- }
- // bit76543210
- ad_spi_send(0b00100000 | rate_bit);
-
- // OFC0,1,2: no offset correction
- ad_spi_send(0);
- ad_spi_send(0);
- ad_spi_send(0);
+ for(i = 0; i < AD_CHNUM; i++) {
+ cs = AD_CH1_CS + i;
+ //1. Send the SDATAC command <11h>. This command cancels the RDATAC mode. RDATAC mode must be
+ //cancelled before the register write commands.
- // FSC0,1,2: no full scale correction
- ad_spi_send(0);
- ad_spi_send(0);
- ad_spi_send(0b01000000);
- ad_cs_dis();
+ ad_cs(cs);
+ ad_spi_send(ADCMD_SDATAC);
+ ad_cs_dis();
+ //2. Send the register write command. The following example shows the register write as a block of nine bytes,
+ //starting at register 0 (CONFIG0).
+ ad_cs(cs);
+ ad_spi_send(ADCMD_WREG | 0); // Register write command
+ ad_spi_send(9 - 1); // 9byte write
+ // CONFIG0: RFBIAS OFF, SPI timeout enable
+ // Bit 2 RBIAS: Internal reference bias
+ // 0 = Internal reference bias disabled
+ // 1 = Internal reference bias enabled (default)
+ // Bit 0 SPI: SCLK timeout of SPI interface
+ // 0 = SPI timeout disabled
+ // 1 = SPI timeout enabled (default), when SCLK is held low for 216 clock cycles
+ // bit76543210
+ ad_spi_send(0b00000101);
+ // CONFIG1: sinc1 filter, EXTREF ON, START delay = 0
+ // Bit 6 CHKSUM: Checksum
+ // 0 = Disabled (default)
+ // 1 = Conversion data checksum byte included in readback
+ // Bit 4 SINC2: Digital filter mode
+ // 0 = sinc1 filter (default)
+ // 1 = sinc2 filter
+ // Bit 3 EXTREF: Reference select
+ // 0 = Internal
+ // 1 = External (default)
+ // Bits 2-0 DELAY[2:0]: START conversion delay
+ // 000 = No delay (default)
+ // bit76543210
+ ad_spi_send(0b00001000);
+
+
+ // CONFIG2: SYNCOUT ON, Gate control, DataRate=10Hz
+ // Bit 5 SYNCOUT: SYNCOUT clock enable
+ // 0 = SYNCOUT disabled (default)
+ // 1 = SYNCOUT enabled
+ // Bit 4 PULSE: Conversion Control mode select
+ // 0 = Gate Control mode (default)
+ // 1 = Pulse Control mode
+ // Bits 2-0 DR[2:0] Data rate setting
+ // 000 = 10SPS (default)
+ // 001 = 16.6SPS
+ // 010 = 50SPS
+ // 011 = 60SPS
+ // 100 = 400SPS
+ // 101 = 1200SPS
+ // 110 = 3600SPS
+ // 111 = 14400SPS
+ // NOTE: fCLK = 7.3728MHz
+ unsigned char rate_bit;
+ switch(AD_SAMPLE) {
+ case 50:
+ rate_bit = 0b00000010;
+ break;
+ case 400:
+ rate_bit = 0b00000100;
+ break;
+ default:
+ case 10:
+ rate_bit = 0b00000000;
+ break;
+ }
+ // bit76543210
+ ad_spi_send(0b00100000 | rate_bit);
+
+ // OFC0,1,2: no offset correction
+ ad_spi_send(0);
+ ad_spi_send(0);
+ ad_spi_send(0);
+
+ // FSC0,1,2: no full scale correction
+ ad_spi_send(0);
+ ad_spi_send(0);
+ ad_spi_send(0b01000000);
+ ad_cs_dis();
-}
+ }
// 4. Take the START pin high or send the START command to start conversions.
ad_start_ena(); // +AD START
}
/*
- PGA280 init
- BUF OFF
+ * PGA280 init
+ * BUF OFF
+ * SYNCin enable
*/
void pga_init(void)
{
int cs;
int i;
-for(i = 0; i < AD_CHNUM; i++) {
- cs = PGA_CH1_CS + i;
- //Register 1
- //Soft Reset
- ad_cs(cs);
- ad_spi_send(0x41);
- ad_spi_send(0x01);
- ad_cs_dis();
- //waitいる?
- delay_ms(1);
+ for(i = 0; i < AD_CHNUM; i++) {
+ cs = PGA_CH1_CS + i;
+ //Register 1
+ //Soft Reset
+ ad_cs(cs);
+ ad_spi_send(0x41);
+ ad_spi_send(0x01);
+ ad_cs_dis();
+ //waitいる?
+ delay_ms(1);
- //Register 0
- //Gain=1/4
- ad_cs(cs);
- ad_spi_send(0x40); //(BUF OFF)
- ad_spi_send(0x08);
- ad_cs_dis();
+ //Register 0
+ //Gain=1/4
+ ad_cs(cs);
+ ad_spi_send(0x40); //(BUF OFF)
+ ad_spi_send(0x08);
+ ad_cs_dis();
- //Register 8: GPIO Configuration Register
- //使わないpinはoutput(=1)にする
- //bit6 GPIO6(SYNCIN) input(=0)
- ad_cs(cs);
- ad_spi_send(0x48);
- ad_spi_send(0b00111111);
- ad_cs_dis();
+ //Register 8: GPIO Configuration Register
+ //使わないpinはoutput(=1)にする
+ //bit6 GPIO6(SYNCIN) input(=0)
+ ad_cs(cs);
+ ad_spi_send(0x48);
+ ad_spi_send(0b00111111);
+ ad_cs_dis();
- //Register 12: Special Functions Register
- //bit6 SYNCin=1 SYNCIN(GPIO6) Enable
- ad_cs(cs);
- ad_spi_send(0x4C);
- ad_spi_send(0b01000000);
- ad_cs_dis();
-}
+ //Register 12: Special Functions Register
+ //bit6 SYNCin=1 SYNCIN(GPIO6) Enable
+ ad_cs(cs);
+ ad_spi_send(0x4C);
+ ad_spi_send(0b01000000);
+ ad_cs_dis();
+ }
}
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