11/11/30 12H serial csv out.

[scilog/cpu2010.git] / myad.h

diff --git a/myad.h b/myad.h
index b84ce72..29de4c5 100644 (file)
--- a/myad.h
+++ b/myad.h
@@ -4,6 +4,10 @@
 
 #define __MYAD_H__
 
+#define CS_RCLK PORTAbits.RA7
+#define CS_CLK  PORTAbits.RA8
+#define CS_DATA PORTAbits.RA9
+
 #define AD_CHNUM    6
 #define AD_CH1_CS   0   // AD CH1のCS番号
 #define PGA_CH1_CS  6   // PGA CH1のCS番号
@@ -24,14 +28,51 @@
 //char ad_is_drdy0_intf(void);
 
 void ad_cs_init(void);
-void ad_cs(unsigned char adr);
-void ad_cs_dis(void);
+inline extern void ad_cs(unsigned char cs)
+{
+    unsigned char i;
+
+//CS_CLK = 1;
+    for(i = 16; i > 0; i--) {
+        if (i == cs+1) {
+            CS_DATA = 0;
+        } else {
+            CS_DATA = 1;
+        }
+        asm("NOP");
+        CS_CLK = 1;
+        CS_CLK = 0;
+    }
+    asm("NOP");
+    CS_RCLK = 1;
+    asm("NOP");
+    CS_DATA = 0;
+    asm("NOP");
+    CS_RCLK = 0;
+}
+
+inline extern void ad_cs_dis(void){
+    unsigned char i;
+
+    CS_DATA = 1;
+    for(i = 16; i > 0; i--) {
+        CS_CLK = 1;
+        CS_CLK = 0;
+    }
+    asm("NOP");
+    CS_RCLK = 1;
+    asm("NOP");
+    CS_DATA = 0;
+    asm("NOP");
+    CS_RCLK = 0;
+}
+
 
-#define ad_reset_dis()  PORTBbits.RB10 = 1; __delay32(1)
-#define ad_reset_ena()  PORTBbits.RB10 = 0; __delay32(1)
+#define ad_reset_dis()  PORTBbits.RB10 = 1; asm("NOP")
+#define ad_reset_ena()  PORTBbits.RB10 = 0; asm("NOP")
 
-#define ad_start_dis()  PORTBbits.RB11 = 0; __delay32(1)
-#define ad_start_ena()  PORTBbits.RB11 = 1; __delay32(1)
+#define ad_start_dis()  PORTBbits.RB11 = 0; asm("NOP")
+#define ad_start_ena()  PORTBbits.RB11 = 1; asm("NOP")
 
 #define ad_is_drdy0_enable()    (PORTBbits.RB12 == 0)