hw/MC3630.h: reg fields

[stock/stock.osdn.git] / hw / MC3630.h

diff --git a/hw/MC3630.h b/hw/MC3630.h
index 5196e11..a36bc6d 100644 (file)
--- a/hw/MC3630.h
+++ b/hw/MC3630.h
@@ -50,3 +50,75 @@ enum {
    MC3630_YGAIN      = 0x31, // Y Gain
    MC3630_ZGAIN      = 0x32, // Z Gain
 };
+
+enum {
+   // MC3630_FREG_1, Feature Register 1
+   MC3630_FREG_1_SPI_EN  = 1<<7,
+   MC3630_FREG_1_I2C_EN  = 1<<6,
+   MC3630_FREG_1_SPI3_EN = 1<<5,
+   MC3630_FREG_1_SPI4 = MC3630_FREG_1_SPI_EN, // SPI 4-wire
+
+   // MC3630_FREG_2, Feature Register 2
+   MC3630_FREG_2_FIFO_BURST   = 1<<1, // FIFO burst read
+   MC3630_FREG_2_FIFO_STAT_EN = 1<<3, // FIFO status token enable
+   MC3630_FREG_2_FIFO_STREAM  = 1<<5, // FIFO stream or “continuous” write mode
+
+   // MC3630_INIT_1, Initialization 1
+   MC3630_INIT_1_INIT = 0x42,
+
+   // MC3630_MODE_C, Mode Control
+   MC3630_MODE_SLEEP   = 0,
+   MC3630_MODE_STANDBY = 1,
+   MC3630_MODE_SNIFF   = 2,
+   MC3630_MODE_CWAKE   = 5,
+   MC3630_MODE_SWAKE   = 6,
+   MC3630_MODE_TRIG    = 7,
+
+   // MC3630_RANGE_C, Range and Resolution Control
+   MC3630_RES_6    = 0<<0, // 6 bits
+   MC3630_RES_7    = 1<<0, // 7 bits
+   MC3630_RES_8    = 2<<0, // 8 bits
+   MC3630_RES_10   = 3<<0, // 10 bits
+   MC3630_RES_12   = 4<<0, // 12 bits
+   MC3630_RES_14   = 5<<0, // 14 bits
+   MC3630_RANGE_2  = 0<<4, // ±2g 
+   MC3630_RANGE_4  = 1<<4, // ±4g 
+   MC3630_RANGE_8  = 2<<4, // ±8g 
+   MC3630_RANGE_16 = 3<<4, // ±16g 
+   MC3630_RANGE_12 = 4<<4, // ±12g 
+
+   // MC3630_FIFO_C, FIFO Control
+   MC3630_FIFO_C_FIFO_MODE  = 1<<5,
+   MC3630_FIFO_C_FIFO_EN    = 1<<6,
+   MC3630_FIFO_C_FIFO_RESET = 1<<7,
+
+   // MC3630_INTR_C, Interrupt Control
+   MC3630_INTR_C_IPP             = 1<<0, // INTN pin: “push-pull” mode
+   MC3630_INTR_C_IAH             = 1<<1, // Interrupt request is active high
+   MC3630_INTR_C_INT_WAKE        = 1<<2,
+   MC3630_INTR_C_INT_ACQ         = 1<<3,
+   MC3630_INTR_C_INT_FIFO_EMPTY  = 1<<4,
+   MC3630_INTR_C_INT_FIFO_FULL   = 1<<5,
+   MC3630_INTR_C_INT_FIFO_THRESH = 1<<6,
+   MC3630_INTR_C_INT_SWAKE       = 1<<7,
+
+   // MC3630_CHIP_ID, Chip ID Register
+   MC3630_CHIP_ID_VALUE = 0x71,
+
+   // MC3630_INIT_3, Initialization 3
+   MC3630_INIT_3_INIT = 0,
+
+   // MC3630_PMCR, Power Mode Control
+   MC3630_POWER_LOW  = 0, // Low Power Mode (nominal noise levels)
+   MC3630_POWER_ULOW = 3, // Ultra-Low Power Mode (highest noise levels)
+   MC3630_POWER_PREC = 4, // Precision Mode (lowest noise levels)
+
+   // MC3630_DMX, Drive Motion X
+   MC3630_DMX_INIT = 0x01,
+
+   // MC3630_DMY, Drive Motion Y
+   MC3630_DMY_INIT = 0x80,
+
+   // MC3630_INIT_2, Initialization 2
+   MC3630_INIT_2_INIT = 0,
+};