LPC4330のコアが204MHzで動作するように調整。LPC1830のPLLも制御ロジックを合わせた。

[toppersasp4lpc/asp.git] / asp / arch / arm_m_gcc / lpc4300_gcc / chip_config.c

diff --git a/asp/arch/arm_m_gcc/lpc4300_gcc/chip_config.c b/asp/arch/arm_m_gcc/lpc4300_gcc/chip_config.c
index 598e9e8..dbfa73d 100644 (file)
--- a/asp/arch/arm_m_gcc/lpc4300_gcc/chip_config.c
+++ b/asp/arch/arm_m_gcc/lpc4300_gcc/chip_config.c
@@ -46,7 +46,7 @@
  */
 /**
  * \file chip_config.c
- * \brief カーネル実装のチップ依存モジュール（LPC18xx汎用）
+ * \brief カーネル実装のチップ依存モジュール（LPC43xx汎用）
  */
 #include "kernel_impl.h"
 #include <sil.h>
@@ -66,25 +66,39 @@ void chip_initialize(void)
 
 }
 
-// Todo:ビルドは通るがPLLの設定が正しいか確認
-extern void initPLL1(
-               pllClockSource_type     clkSrc,
-               unsigned int                    N,
-               unsigned int                    M,
-               unsigned int                    cpuClkDiv
-       )
+extern void initPLL1( unsigned int     Hz      )
 {
 
-               // Set PLL
-       LPC_CGU->PLL1_CTRL =  ((M-1)<<CGU_PLL1_CTRL_MSEL_Pos)           // Multiplier
-                                               | ((N-1)<<CGU_PLL1_CTRL_NSEL_Pos)               // Pre-PLL div
-                                               | ((clkSrc-1)<<CGU_PLL1_CTRL_CLK_SEL_Pos)       // clock source
-                                               | CGU_PLL1_CTRL_AUTOBLOCK_Msk;
-       while
-         (!(LPC_CGU->PLL1_STAT & CGU_PLL1_STAT_LOCK_Msk));             /* PLLの準備が整うまで待つ  */
-
-               // select PLL1 as input for M3 core
-       LPC_CGU->BASE_M4_CLK = CGU_BASE_M4_CLK_AUTOBLOCK_Msk | (0x09 << CGU_BASE_M4_CLK_CLK_SEL_Pos);
+    LPC_CGU->BASE_M4_CLK = 0x01000800;          // select IRC as cortex-m4 input, auto hold
+
+            // Set PLL1 frequency to 96MHz
+    LPC_CGU->PLL1_CTRL =
+                        1 << 24 |   // 28:24, clock sel = 1 (IRC)
+                       23 << 16 |   // 23:16, MSEL = 23 ( multiply by (MSEL+1) )
+                        2 << 12 |   // 13:12, NSEL = 2  ( pre division by (NSEL+1) )
+                        1 << 11 |   // 11,    AUTOBLOCK = 1
+                        1 << 8  |   // 9:8,   PSEL = 1 ( post division by (PSEL+1))
+                        1 << 7  |   // 7,     DIRECT=1 ( 1 : bypass PSEL, 0 : use PSEL )
+                        0 << 6  |   // 6,     FBSEL=0  ( 1 : output, 0 : CCO )
+                        0 << 1  |   // 1,     BYPASS=0 ( 1 : input, 0 : CCO )
+                             0;      // 0,     PD = 0   ( 1 : power down, 0 active );
+            // wait for lock
+    while ( ! LPC_CGU->PLL1_STAT )
+       ;
+    LPC_CGU->BASE_M4_CLK = 0x09000800;          // select PLL1, auto hold
+        // Set PLL1 frequency to desired
+        // PLL reference is 4MHz (12MHz/3). So, the multiplier have to be ( desired freq / 4 )-1
+    LPC_CGU->PLL1_CTRL =
+                1 << 24 |   // 28:24, clock sel = 1 (IRC)
+               (Hz/4000000-1) << 16 |   // 23:16, MSEL = 47 ( multiply by (MSEL+1) )
+                2 << 12 |   // 13:12, NSEL = 2  ( pre division by (NSEL+1) )
+                1 << 11 |   // 11,    AUTOBLOCK = 1
+                1 << 8  |   // 9:8,   PSEL = 1 ( post division by (PSEL+1))
+                1 << 7  |   // 7,     DIRECT=1 ( 1 : bypass PSEL, 0 : use PSEL )
+                0 << 6  |   // 6,     FBSEL=0  ( 1 : output, 0 : CCO )
+                0 << 1  |   // 1,     BYPASS=0 ( 1 : input, 0 : CCO )
+                     0;      // 0,     PD = 0   ( 1 : power down, 0 active );
+    // wait for lock
 
 }