#include <t_services.h>
+#include <s_services.h>
#include "kernel_id.h"
#include "rx_if.h"
#include <cdefBF533.h>
#define PEEPINGTEST // Define PEEPING test to see the top 4 of FIFO after enabling SPORT RX
#ifdef PEEPINGTEST
-#define SLEEPDURATION 2000
+#define SLEEPDURATION 1000
#else
#define SLEEPDURATION 10
#endif
unsigned short x_modify;
};
-static struct dma_descripter rx_dma_dsc0, rx_dma_dsc1;
+static struct dma_descripter rx_dma_dsc[2];
-unsigned int dummy_buffer0[RXIF_BUFSIZE], dummy_buffer1[RXIF_BUFSIZE];
+unsigned int rxif_buffer[2][RXIF_BUFSIZE];
/*
* RX_IF受信データの処理タスク。
syscall(serial_ctl_por(TASK_PORTID,
(IOCTL_CRLF | IOCTL_FCSND | IOCTL_FCRCV)));
- /*
- * タスクの起動
- act_tsk(TASK1);
- act_tsk(TASK2);
- act_tsk(TASK3);
- */
+
+
+ syscall(ena_int(INTNO_SPORT0_RX));
*pSPORT0_TCR1 =
0 << 14 | // TCKFE, 0:sample at down edge, 1:sample at up edge
// 受信DMAデスクリプタを作る
- rx_dma_dsc0.next_descripter = &rx_dma_dsc1;
- rx_dma_dsc0.start_address = dummy_buffer0;
- rx_dma_dsc0.x_count = RXIF_BUFSIZE;
- rx_dma_dsc0.x_modify = sizeof(dummy_buffer0[0]);
- rx_dma_dsc0.config =
- 7 <<12 | // FLOW, 0:Stop, 1:Auto buffer, 4:Desc array, 6:Desc List small, 7:Desc, List, Large
- 7 << 8 | // NDSIZE, the # of element of the next descripter to fetch
- 0 << 7 | // DI_EN, 0:No interrupt at the end, 1:Interrupt at the end
- 1 << 6 | // DI_SEL, 0:Interrupt at the end of outer loop, 1:Interrupt at the end of inter loop
- 1 << 5 | // RESTART, 0:Keep DMA FIFO before start, 1:Purge DMA FIFO before start
- 0 << 4 | // DMA2D, 0:Linear DMA, 1:2D DMA
- 2 << 2 | // WDSIZE, 0:8bit, 1:16bit, 2:32bit,3:reserved
- 1 << 1 | // WNR, 0:Read from memory, 1:Write to Memory
- 1 << 0 ; // DMA_EN, 0:Disable DMA, 1:Enable DMA
-
- rx_dma_dsc1.next_descripter = &rx_dma_dsc0;
- rx_dma_dsc1.start_address = dummy_buffer1;
- rx_dma_dsc1.x_count = RXIF_BUFSIZE;
- rx_dma_dsc1.x_modify = sizeof(dummy_buffer1[0]);
- rx_dma_dsc1.config =
- 7 <<12 | // FLOW, 0:Stop, 1:Auto buffer, 4:Desc array, 6:Desc List small, 7:Desc, List, Large
- 7 << 8 | // NDSIZE, the # of element of the next descripter to fetch
- 0 << 7 | // DI_EN, 0:No interrupt at the end, 1:Interrupt at the end
- 1 << 6 | // DI_SEL, 0:Interrupt at the end of outer loop, 1:Interrupt at the end of inter loop
- 1 << 5 | // RESTART, 0:Keep DMA FIFO before start, 1:Purge DMA FIFO before start
- 0 << 4 | // DMA2D, 0:Linear DMA, 1:2D DMA
- 2 << 2 | // WDSIZE, 0:8bit, 1:16bit, 2:32bit,3:reserved
- 1 << 1 | // WNR, 0:Read from memory, 1:Write to Memory
- 1 << 0 ; // DMA_EN, 0:Disable DMA, 1:Enable DMA
-
+ rx_dma_dsc[0].next_descripter = &rx_dma_dsc[1];
+ rx_dma_dsc[0].start_address = rxif_buffer[0];
+ rx_dma_dsc[0].x_count = RXIF_BUFSIZE;
+ rx_dma_dsc[0].x_modify = sizeof(rxif_buffer[0][0]);
+ rx_dma_dsc[0].config =
+ FLOW_LARGE | // FLOW, 0:Stop, 1:Auto buffer, 4:Desc array, 6:Desc List small, 7:Desc, List, Large
+ NDSIZE_7 | // NDSIZE, the # of element of the next descripter to fetch
+ 1 << DI_EN_P | // DI_EN, 0:No interrupt at the end, 1:Interrupt at the end
+ 0 << DI_SEL_P | // DI_SEL, 0:Interrupt at the end of outer loop, 1:Interrupt at the end of inter loop
+ 0 << RESTART_P | // RESTART, 0:Keep DMA FIFO before start, 1:Purge DMA FIFO before start
+ 0 << DMA2D_P | // DMA2D, 0:Linear DMA, 1:2D DMA
+ WDSIZE_32 | // WDSIZE, 0:8bit, 1:16bit, 2:32bit,3:reserved
+ 1 << WNR_P | // WNR, 0:Read from memory, 1:Write to Memory
+ 1 << 0 ; // DMA_EN, 0:Disable DMA, 1:Enable DMA
+
+ rx_dma_dsc[1].next_descripter = &rx_dma_dsc[0];
+ rx_dma_dsc[1].start_address = rxif_buffer[1];
+ rx_dma_dsc[1].x_count = RXIF_BUFSIZE;
+ rx_dma_dsc[1].x_modify = sizeof(rxif_buffer[1][0]);
+ rx_dma_dsc[1].config =
+ FLOW_LARGE | // FLOW, 0:Stop, 1:Auto buffer, 4:Desc array, 6:Desc List small, 7:Desc, List, Large
+ NDSIZE_7 | // NDSIZE, the # of element of the next descripter to fetch
+ 1 << DI_EN_P | // DI_EN, 0:No interrupt at the end, 1:Interrupt at the end
+ 0 << DI_SEL_P | // DI_SEL, 0:Interrupt at the end of outer loop, 1:Interrupt at the end of inter loop
+ 0 << RESTART_P | // RESTART, 0:Keep DMA FIFO before start, 1:Purge DMA FIFO before start
+ 0 << DMA2D_P | // DMA2D, 0:Linear DMA, 1:2D DMA
+ WDSIZE_32 | // WDSIZE, 0:8bit, 1:16bit, 2:32bit,3:reserved
+ 1 << WNR_P | // WNR, 0:Read from memory, 1:Write to Memory
+ 1 << 0 ; // DMA_EN, 0:Disable DMA, 1:Enable DMA
+
+ // DMAコントローラの初期状態設定
+ // ここではDMAをイネーブルにしない。また、バッファクリアする
+ *pDMA1_CONFIG =
+ FLOW_LARGE | // FLOW, 0:Stop, 1:Auto buffer, 4:Desc array, 6:Desc List small, 7:Desc, List, Large
+ NDSIZE_7 | // NDSIZE, the # of element of the next descripter to fetch
+ 1 << DI_EN_P | // DI_EN, 0:No interrupt at the end, 1:Interrupt at the end
+ 0 << DI_SEL_P | // DI_SEL, 0:Interrupt at the end of outer loop, 1:Interrupt at the end of inter loop
+ 1 << RESTART_P | // RESTART, 0:Keep DMA FIFO before start, 1:Purge DMA FIFO before start
+ 0 << DMA2D_P | // DMA2D, 0:Linear DMA, 1:2D DMA
+ WDSIZE_32 | // WDSIZE, 0:8bit, 1:16bit, 2:32bit,3:reserved
+ 1 << WNR_P | // WNR, 0:Read from memory, 1:Write to Memory
+ 0 << 0 ; // DMA_EN, 0:Disable DMA, 1:Enable DMA
+ *pDMA1_NEXT_DESC_PTR = &rx_dma_dsc[0];
#ifndef PEEPINGTEST
// RX受信を開始する
- *pDMA1_NEXT_DESC_PTR = & rx_dma_dsc0;
- *pDMA1_CONFIG = rx_dma_dsc1.config;
+ *pDMA1_CONFIG |= DMAEN;
*pSPORT0_RCR1 |= RSPEN; // RX SPORT Enable
ssync();
+ int count = 0;
/*
* メインループ
do {
long int rx[4];
- // 3mS スリープ
- tslp_tsk(3);
+ // SPORT0受信DMAがバッファを埋めるのを待つ。
+ syscall(wai_sem(SEM_SPORT0_RX));
- // FIFOにデータがたまったはずである。
- // FIFOデータを読みだして下位2bitのみ表示する
- rx[0] = dummy_buffer0[0]; // 下位2bitのみ抽出
- rx[1] = dummy_buffer0[1]; // 下位2bitのみ抽出
- rx[2] = dummy_buffer0[2]; // 下位2bitのみ抽出
- rx[3] = dummy_buffer0[3]; // 下位2bitのみ抽出
-
-#ifndef PEEPINGTEST
- *pSPORT0_RCR1 &= ~RSPEN; // RX SPORT disable
- if (rx[0] !=0)
+ count++;
+ if ( count > 31500/(RXIF_BUFSIZE/4))
{
- event ++;
-#endif
+ count = 0;
+ // FIFOにデータがたまったはずである。
+ // FIFOデータを読みだして下位2bitのみ表示する
+ rx[0] = rxif_buffer[0][0]; // 下位2bitのみ抽出
+ rx[1] = rxif_buffer[0][1]; // 下位2bitのみ抽出
+ rx[2] = rxif_buffer[0][2]; // 下位2bitのみ抽出
+ rx[3] = rxif_buffer[0][3]; // 下位2bitのみ抽出
+
syslog( LOG_NOTICE, "RX word : %08x,%08x,%08x,%08x", rx[0], rx[1], rx[2], rx[3] );
-#ifndef PEEPINGTEST
+
}
- count++;
- if (!( count % 1000 ))
- syslog( LOG_NOTICE, "trial : %d, event : %d", count, event);
-#endif
- // スリープ
- tslp_tsk(SLEEPDURATION);
+
+
syslog(LOG_NOTICE, "Sample program ends.");
kernel_exit();
}
+
+
+void sport0_rx_int_handler(void)
+{
+ // DMA割り込みをクリアする。
+ *pDMA1_IRQ_STATUS = DMA_DONE;
+
+ // ペリフェラルへの書き込みを待つ。
+ ssync();
+
+ // タスクにSPORT0受信DMAのバッファが埋まったと知らせる。
+ isig_sem(SEM_SPORT0_RX);
+
+
+}
+
+void sport0_tx_int_handler(void)
+{
+ *pDMA2_IRQ_STATUS = DMA_DONE;
+ ssync();
+
+
+}
+
+
+void init_peripherals(VP_INT p)
+{
+ *pSPORT0_TCR1 = 0;
+ *pSPORT0_RCR1 = 0;
+ *pDMA1_CONFIG = 0;
+ *pDMA2_CONFIG = 0;
+ ssync();
+
+ return;
+}
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