MIPS: MT: Remove SMTC support

[uclinux-h8/linux.git] / arch / mips / Kconfig

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 45e75b6..e3f040c 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1852,7 +1852,7 @@ config FORCE_MAX_ZONEORDER
 
 config CEVT_GIC
        bool "Use GIC global counter for clock events"
-       depends on IRQ_GIC && !(MIPS_SEAD3 || MIPS_MT_SMTC)
+       depends on IRQ_GIC && !MIPS_SEAD3
        help
          Use the GIC global counter for the clock events. The R4K clock
          event driver is always present, so if the platform ends up not
@@ -1936,24 +1936,6 @@ config MIPS_MT_SMP
          Intel Hyperthreading feature. For further information go to
          <http://www.imgtec.com/mips/mips-multithreading.asp>.
 
-config MIPS_MT_SMTC
-       bool "Use all TCs on all VPEs for SMP (DEPRECATED)"
-       depends on CPU_MIPS32_R2
-       depends on SYS_SUPPORTS_MULTITHREADING
-       depends on !MIPS_CPS
-       select CPU_MIPSR2_IRQ_VI
-       select CPU_MIPSR2_IRQ_EI
-       select MIPS_MT
-       select SMP
-       select SMP_UP
-       select SYS_SUPPORTS_SMP
-       select NR_CPUS_DEFAULT_8
-       help
-         This is a kernel model which is known as SMTC. This is
-         supported on cores with the MT ASE and presents all TCs
-         available on all VPEs to support SMP. For further
-         information see <http://www.linux-mips.org/wiki/34K#SMTC>.
-
 endchoice
 
 config MIPS_MT
@@ -1977,7 +1959,7 @@ config SYS_SUPPORTS_MULTITHREADING
 config MIPS_MT_FPAFF
        bool "Dynamic FPU affinity for FP-intensive threads"
        default y
-       depends on MIPS_MT_SMP || MIPS_MT_SMTC
+       depends on MIPS_MT_SMP
 
 config MIPS_VPE_LOADER
        bool "VPE loader support."
@@ -1999,29 +1981,6 @@ config MIPS_VPE_LOADER_MT
        default "y"
        depends on MIPS_VPE_LOADER && !MIPS_CMP
 
-config MIPS_MT_SMTC_IM_BACKSTOP
-       bool "Use per-TC register bits as backstop for inhibited IM bits"
-       depends on MIPS_MT_SMTC
-       default n
-       help
-         To support multiple TC microthreads acting as "CPUs" within
-         a VPE, VPE-wide interrupt mask bits must be specially manipulated
-         during interrupt handling. To support legacy drivers and interrupt
-         controller management code, SMTC has a "backstop" to track and
-         if necessary restore the interrupt mask. This has some performance
-         impact on interrupt service overhead.
-
-config MIPS_MT_SMTC_IRQAFF
-       bool "Support IRQ affinity API"
-       depends on MIPS_MT_SMTC
-       default n
-       help
-         Enables SMP IRQ affinity API (/proc/irq/*/smp_affinity, etc.)
-         for SMTC Linux kernel. Requires platform support, of which
-         an example can be found in the MIPS kernel i8259 and Malta
-         platform code.  Adds some overhead to interrupt dispatch, and
-         should be used only if you know what you are doing.
-
 config MIPS_VPE_LOADER_TOM
        bool "Load VPE program into memory hidden from linux"
        depends on MIPS_VPE_LOADER
@@ -2049,7 +2008,7 @@ config MIPS_VPE_APSP_API_MT
 
 config MIPS_CMP
        bool "MIPS CMP framework support (DEPRECATED)"
-       depends on SYS_SUPPORTS_MIPS_CMP && !MIPS_MT_SMTC
+       depends on SYS_SUPPORTS_MIPS_CMP
        select MIPS_GIC_IPI
        select SYNC_R4K
        select WEAK_ORDERING
@@ -2256,7 +2215,7 @@ config NODES_SHIFT
 
 config HW_PERF_EVENTS
        bool "Enable hardware performance counter support for perf events"
-       depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP)
+       depends on PERF_EVENTS && OPROFILE=n && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP)
        default y
        help
          Enable hardware performance counter support for perf events. If