Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6

[uclinux-h8/linux.git] / arch / powerpc / boot / dts / fsl / t104xrdb.dtsi

diff --git a/arch/powerpc/boot/dts/fsl/t104xrdb.dtsi b/arch/powerpc/boot/dts/fsl/t104xrdb.dtsi
index 830ea48..72691ef 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/t104xrdb.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t104xrdb.dtsi
@@ -1,7 +1,7 @@
 /*
  * T1040RDB/T1042RDB Device Tree Source
  *
- * Copyright 2014 Freescale Semiconductor Inc.
+ * Copyright 2014 - 2015 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -33,6 +33,12 @@
  */
 
 / {
+       aliases {
+               phy_rgmii_0 = &phy_rgmii_0;
+               phy_rgmii_1 = &phy_rgmii_1;
+               phy_sgmii_2 = &phy_sgmii_2;
+       };
+
        reserved-memory {
                #address-cells = <2>;
                #size-cells = <2>;
@@ -103,10 +109,15 @@
                        flash@0 {
                                #address-cells = <1>;
                                #size-cells = <1>;
-                               compatible = "micron,n25q512a";
+                               compatible = "micron,n25q512a", "jedec,spi-nor";
                                reg = <0>;
                                spi-max-frequency = <10000000>; /* input clock */
                        };
+                       slic@3 {
+                               compatible = "maxim,ds26522";
+                               reg = <3>;
+                               spi-max-frequency = <2000000>; /* input clock */
+                       };
                };
 
                i2c@118000 {
@@ -125,6 +136,31 @@
                        };
                };
 
+               fman@400000 {
+                       ethernet@e6000 {
+                               phy-handle = <&phy_rgmii_0>;
+                               phy-connection-type = "rgmii";
+                       };
+
+                       ethernet@e8000 {
+                               phy-handle = <&phy_rgmii_1>;
+                               phy-connection-type = "rgmii";
+                       };
+
+                       mdio0: mdio@fc000 {
+                               phy_sgmii_2: ethernet-phy@03 {
+                                       reg = <0x03>;
+                               };
+
+                               phy_rgmii_0: ethernet-phy@01 {
+                                       reg = <0x01>;
+                               };
+
+                               phy_rgmii_1: ethernet-phy@02 {
+                                       reg = <0x02>;
+                               };
+                       };
+               };
        };
 
        pci0: pcie@ffe240000 {