2 Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Aug 10 20:43:42 2011
\r
3 Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:
\r
6 module vga_gen ( i_clk50M , m_clock , p_reset , o_vsync , o_hsync , o_vga_r , o_vga_g , o_vga_b , i_wrdata1 , i_wrdata2 , fi_fifo1_write , fi_fifo2_write , fi_fifo1_reset , fi_fifo2_reset , outled , o_vcnt );
\r
12 output [3:0] o_vga_r;
\r
13 output [3:0] o_vga_g;
\r
14 output [3:0] o_vga_b;
\r
15 input [7:0] i_wrdata1;
\r
16 input [7:0] i_wrdata2;
\r
17 input fi_fifo1_write;
\r
18 input fi_fifo2_write;
\r
19 input fi_fifo1_reset;
\r
20 input fi_fifo2_reset;
\r
22 output [9:0] o_vcnt;
\r
27 reg [4:0] r_bit_number;
\r
36 wire [23:0] w_rddata1;
\r
37 wire [23:0] w_rddata2;
\r
38 wire _u_FIFO_p_reset;
\r
39 wire _u_FIFO_m_clock;
\r
41 wire [7:0] _u_FIFO_i_wdata1;
\r
43 wire [7:0] _u_FIFO_i_wdata2;
\r
44 wire [23:0] _u_FIFO_o_rddata1;
\r
45 wire [23:0] _u_FIFO_o_rddata2;
\r
46 wire _u_FIFO_i_clock;
\r
49 wire _u_FIFO_i_fifo1_rst;
\r
50 wire _u_FIFO_i_fifo2_rst;
\r
51 wire _u_FIFO_o_rdack1;
\r
52 wire _u_FIFO_o_rdack2;
\r
106 vga_ram u_FIFO (.o_rdack2(_u_FIFO_o_rdack2), .o_rdack1(_u_FIFO_o_rdack1), .i_fifo2_rst(_u_FIFO_i_fifo2_rst), .i_fifo1_rst(_u_FIFO_i_fifo1_rst), .i_re2(_u_FIFO_i_re2), .i_re1(_u_FIFO_i_re1), .i_clock(_u_FIFO_i_clock), .o_rddata2(_u_FIFO_o_rddata2), .o_rddata1(_u_FIFO_o_rddata1), .i_wdata2(_u_FIFO_i_wdata2), .i_we2(_u_FIFO_i_we2), .i_wdata1(_u_FIFO_i_wdata1), .i_we1(_u_FIFO_i_we1), .m_clock(_u_FIFO_m_clock), .p_reset(_u_FIFO_p_reset));
\r
108 assign fs_fifo1_read = _net_20;
\r
109 assign fs_fifo2_read = _net_17;
\r
110 assign fs_fifo1_exec = _net_12;
\r
111 assign fs_fifo2_exec = _net_10;
\r
112 assign w_rddata1 = _u_FIFO_o_rddata1;
\r
113 assign w_rddata2 = _u_FIFO_o_rddata2;
\r
114 assign _u_FIFO_m_clock = m_clock;
\r
115 assign _u_FIFO_i_we1 = fi_fifo1_write;
\r
116 assign _u_FIFO_i_wdata1 = i_wrdata1;
\r
117 assign _u_FIFO_i_we2 = fi_fifo2_write;
\r
118 assign _u_FIFO_i_wdata2 = i_wrdata2;
\r
119 assign _u_FIFO_i_clock = i_clk50M;
\r
120 assign _u_FIFO_i_re1 = fs_fifo1_read;
\r
121 assign _u_FIFO_i_re2 = fs_fifo2_read;
\r
122 assign _u_FIFO_i_fifo1_rst = fi_fifo1_reset;
\r
123 assign _u_FIFO_i_fifo2_rst = fi_fifo2_reset;
\r
124 assign _net_0 = (cnt)==(26'b01011111010111100001000000);
\r
125 assign _net_1 = ~_net_0;
\r
126 assign _net_2 = (r_hcnt) < (10'b1100100000);
\r
127 assign _net_3 = ~_net_2;
\r
128 assign _net_4 = (r_vcnt) < (10'b1000001001);
\r
129 assign _net_5 = ~_net_2;
\r
130 assign _net_6 = (~_net_2)&_net_4;
\r
131 assign _net_7 = (~_net_2)&(~_net_4);
\r
132 assign _net_8 = ((r_hcnt) < (10'b1010000000))&((r_vcnt) < (10'b0111100000));
\r
133 assign _net_9 = r_vcnt[0];
\r
134 assign _net_10 = _net_8&_net_9;
\r
135 assign _net_11 = ~(r_vcnt[0]);
\r
136 assign _net_12 = _net_8&_net_11;
\r
137 assign _net_13 = (r_bit_number)==(5'b10111);
\r
138 assign _net_14 = _net_8&_net_13;
\r
139 assign _net_15 = r_vcnt[0];
\r
140 assign _net_16 = _net_8&_net_13;
\r
141 assign _net_17 = (_net_8&_net_13)&_net_15;
\r
142 assign _net_18 = ~(r_vcnt[0]);
\r
143 assign _net_19 = _net_8&_net_13;
\r
144 assign _net_20 = (_net_8&_net_13)&_net_18;
\r
145 assign _net_21 = _net_8&(~_net_13);
\r
146 assign _net_22 = (r_hcnt)==(10'b1011110000);
\r
147 assign _net_23 = ~_net_8;
\r
148 assign _net_24 = (~_net_8)&_net_22;
\r
149 assign _net_25 = (r_hcnt)==(10'b1010010000);
\r
150 assign _net_26 = ~_net_8;
\r
151 assign _net_27 = (~_net_8)&_net_25;
\r
152 assign _net_28 = (r_hcnt)==(10'b1010000000);
\r
153 assign _net_29 = ~_net_8;
\r
154 assign _net_30 = (~_net_8)&_net_28;
\r
155 assign _net_31 = (~_net_8)&_net_28;
\r
156 assign _net_32 = (~_net_8)&_net_28;
\r
157 assign _net_33 = (~_net_8)&_net_28;
\r
158 assign _net_34 = (~_net_8)&_net_28;
\r
159 assign _net_35 = (~_net_8)&_net_28;
\r
160 assign _net_36 = (r_vcnt)==(10'b0111101100);
\r
161 assign _net_37 = (r_vcnt)==(10'b0111101010);
\r
162 assign _net_38 = (r_vcnt)==(10'b0111100000);
\r
163 assign _net_39 = w_rddata1[r_bit_number];
\r
164 assign _net_40 = fs_fifo1_exec&_net_39;
\r
165 assign _net_41 = fs_fifo1_exec&_net_39;
\r
166 assign _net_42 = fs_fifo1_exec&_net_39;
\r
167 assign _net_43 = fs_fifo1_exec&(~_net_39);
\r
168 assign _net_44 = fs_fifo1_exec&(~_net_39);
\r
169 assign _net_45 = fs_fifo1_exec&(~_net_39);
\r
170 assign _net_46 = w_rddata2[r_bit_number];
\r
171 assign _net_47 = fs_fifo2_exec&_net_46;
\r
172 assign _net_48 = fs_fifo2_exec&_net_46;
\r
173 assign _net_49 = fs_fifo2_exec&_net_46;
\r
174 assign _net_50 = fs_fifo2_exec&(~_net_46);
\r
175 assign _net_51 = fs_fifo2_exec&(~_net_46);
\r
176 assign _net_52 = fs_fifo2_exec&(~_net_46);
\r
177 assign o_vsync = r_vsync;
\r
178 assign o_hsync = r_hsync;
\r
179 assign o_vga_r = ((_net_47|_net_40)?4'b1111:4'b0)|
\r
180 ((_net_50|_net_43|_net_30)?4'b0000:4'b0);
\r
181 assign o_vga_g = ((_net_48|_net_41)?4'b1111:4'b0)|
\r
182 ((_net_51|_net_44|_net_31)?4'b0000:4'b0);
\r
183 assign o_vga_b = ((_net_49|_net_42)?4'b1111:4'b0)|
\r
184 ((_net_52|_net_45|_net_32)?4'b0000:4'b0);
\r
185 assign outled = testled;
\r
186 assign o_vcnt = r_vcnt;
\r
187 always @(posedge m_clock or negedge p_reset)
\r
190 r_bit_number <= 5'b00000;
\r
191 else if ((_net_21)|(_net_35|_net_14))
\r
192 r_bit_number <= ((_net_21) ?(r_bit_number)+(5'b00001):5'b0)|
\r
193 ((_net_35|_net_14) ?5'b00000:5'b0);
\r
196 always @(posedge m_clock or negedge p_reset)
\r
200 else if ((_net_37)|(_net_36))
\r
201 r_vsync <= ((_net_37) ?1'b0:1'b0)|
\r
202 ((_net_36) ?1'b1:1'b0);
\r
205 always @(posedge m_clock or negedge p_reset)
\r
209 else if ((_net_27)|(_net_24))
\r
210 r_hsync <= ((_net_27) ?1'b0:1'b0)|
\r
211 ((_net_24) ?1'b1:1'b0);
\r
214 always @(posedge m_clock or negedge p_reset)
\r
217 r_vcnt <= 10'b0000000000;
\r
218 else if ((_net_7)|(_net_6))
\r
219 r_vcnt <= ((_net_7) ?10'b0000000000:10'b0)|
\r
220 ((_net_6) ?(r_vcnt)+(10'b0000000001):10'b0);
\r
223 always @(posedge m_clock or negedge p_reset)
\r
226 r_hcnt <= 10'b0000000000;
\r
227 else if ((_net_3)|(_net_2))
\r
228 r_hcnt <= ((_net_3) ?10'b0000000000:10'b0)|
\r
229 ((_net_2) ?(r_hcnt)+(10'b0000000001):10'b0);
\r
232 always @(posedge m_clock or negedge p_reset)
\r
235 cnt <= 26'b00000000000000000000000000;
\r
236 else if ((_net_1)|(_net_0))
\r
237 cnt <= ((_net_1) ?(cnt)+(26'b00000000000000000000000001):26'b0)|
\r
238 ((_net_0) ?26'b00000000000000000000000000:26'b0);
\r
241 always @(posedge m_clock or negedge p_reset)
\r
245 else if ((_net_0))
\r
246 testled <= ~testled;
\r
248 always @(posedge m_clock or negedge p_reset)
\r
251 r_outcnt <= 3'b000;
\r
252 else if ((_net_33))
\r
253 r_outcnt <= 3'b000;
\r
255 always @(posedge m_clock or negedge p_reset)
\r
258 r_outclr <= 7'b0000000;
\r
259 else if ((_net_34))
\r
260 r_outclr <= 7'b0000000;
\r
264 Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Aug 10 20:43:46 2011
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265 Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp
\r
268 module vga_top ( p_reset , m_clock , i_sw , o_vsync , o_hsync , o_vga_r , o_vga_g , o_vga_b , o_LED );
\r
269 input p_reset, m_clock;
\r
273 output [3:0] o_vga_r;
\r
274 output [3:0] o_vga_g;
\r
275 output [3:0] o_vga_b;
\r
276 output [7:0] o_LED;
\r
280 reg [25:0] r_sec_cnt;
\r
282 reg [13:0] r_init_cnt;
\r
283 reg [15:0] r_vram_rddata;
\r
284 reg [13:0] r_vram_start_adrs;
\r
285 reg r_hld_vram_start;
\r
286 wire [7:0] w_wrdata1;
\r
287 wire [7:0] w_wrdata2;
\r
288 wire fs_fifo1_write;
\r
289 wire fs_fifo2_write;
\r
291 wire fs_fifo1_charge;
\r
292 wire fs_fifo2_charge;
\r
293 wire fs_vram_cnt_inc;
\r
294 wire [13:0] _net_55;
\r
295 wire [13:0] _net_58;
\r
296 wire [13:0] _net_61;
\r
297 wire [13:0] _net_64;
\r
298 wire [13:0] _net_67;
\r
299 wire _u_VGA_i_clk50M;
\r
300 wire _u_VGA_m_clock;
\r
301 wire _u_VGA_p_reset;
\r
302 wire _u_VGA_o_vsync;
\r
303 wire _u_VGA_o_hsync;
\r
304 wire [3:0] _u_VGA_o_vga_r;
\r
305 wire [3:0] _u_VGA_o_vga_g;
\r
306 wire [3:0] _u_VGA_o_vga_b;
\r
307 wire [7:0] _u_VGA_i_wrdata1;
\r
308 wire [7:0] _u_VGA_i_wrdata2;
\r
309 wire _u_VGA_fi_fifo1_write;
\r
310 wire _u_VGA_fi_fifo2_write;
\r
311 wire _u_VGA_fi_fifo1_reset;
\r
312 wire _u_VGA_fi_fifo2_reset;
\r
313 wire _u_VGA_outled;
\r
314 wire [9:0] _u_VGA_o_vcnt;
\r
315 wire [13:0] _u_EXP_i_Radrs;
\r
316 wire [15:0] _u_EXP_o_Rdata;
\r
317 wire _u_EXP_fi_Rd_req;
\r
318 wire _u_EXP_fo_Rd_ack;
\r
319 wire [7:0] _u_EXP_i_Wdata;
\r
320 wire [13:0] _u_EXP_i_Wadrs;
\r
321 wire _u_EXP_fi_Wr_req;
\r
322 wire _u_EXP_p_reset;
\r
323 wire _u_EXP_m_clock;
\r
409 wire _reg_135_goto;
\r
411 wire _reg_138_goin;
\r
414 wire _reg_138_goto;
\r
432 wire _reg_155_goto;
\r
434 wire _reg_158_goin;
\r
437 wire _reg_158_goto;
\r
439 wire _reg_154_goin;
\r
453 exp_ctrl u_EXP (.p_reset(p_reset), .m_clock(m_clock), .fi_Wr_req(_u_EXP_fi_Wr_req), .i_Wadrs(_u_EXP_i_Wadrs), .i_Wdata(_u_EXP_i_Wdata), .fo_Rd_ack(_u_EXP_fo_Rd_ack), .fi_Rd_req(_u_EXP_fi_Rd_req), .o_Rdata(_u_EXP_o_Rdata), .i_Radrs(_u_EXP_i_Radrs));
\r
454 vga_gen u_VGA (.o_vcnt(_u_VGA_o_vcnt), .outled(_u_VGA_outled), .fi_fifo2_reset(_u_VGA_fi_fifo2_reset), .fi_fifo1_reset(_u_VGA_fi_fifo1_reset), .fi_fifo2_write(_u_VGA_fi_fifo2_write), .fi_fifo1_write(_u_VGA_fi_fifo1_write), .i_wrdata2(_u_VGA_i_wrdata2), .i_wrdata1(_u_VGA_i_wrdata1), .o_vga_b(_u_VGA_o_vga_b), .o_vga_g(_u_VGA_o_vga_g), .o_vga_r(_u_VGA_o_vga_r), .o_hsync(_u_VGA_o_hsync), .o_vsync(_u_VGA_o_vsync), .p_reset(_u_VGA_p_reset), .m_clock(_u_VGA_m_clock), .i_clk50M(_u_VGA_i_clk50M));
\r
456 assign w_wrdata1 = ((_reg_136|_reg_83)?r_vram_rddata[7:0]:8'b0)|
\r
457 ((_reg_135|_reg_82)?r_vram_rddata[15:8]:8'b0);
\r
458 assign w_wrdata2 = ((_reg_156|_reg_78)?r_vram_rddata[7:0]:8'b0)|
\r
459 ((_reg_155|_reg_77)?r_vram_rddata[15:8]:8'b0);
\r
460 assign fs_fifo1_write = _reg_136|_reg_135|_reg_83|_reg_82;
\r
461 assign fs_fifo2_write = _reg_156|_reg_155|_reg_78|_reg_77;
\r
462 assign fs_init = _net_68;
\r
463 assign fs_fifo1_charge = _net_72;
\r
464 assign fs_fifo2_charge = _net_70;
\r
465 assign fs_vram_cnt_inc = _reg_154;
\r
466 assign _net_55 = (r_init_cnt)+(14'b00000000000001);
\r
467 assign _net_58 = (r_init_cnt)+(14'b00000000000001);
\r
468 assign _net_61 = (r_init_cnt)+(14'b00000000000001);
\r
469 assign _net_64 = (r_init_cnt)+(14'b00000000000001);
\r
470 assign _net_67 = (r_init_cnt)+(14'b00000000000001);
\r
471 assign _u_VGA_i_clk50M = m_clock;
\r
472 assign _u_VGA_m_clock = r_cnt;
\r
473 assign _u_VGA_p_reset = r_reset;
\r
474 assign _u_VGA_i_wrdata1 = w_wrdata1;
\r
475 assign _u_VGA_i_wrdata2 = w_wrdata2;
\r
476 assign _u_VGA_fi_fifo1_write = fs_fifo1_write;
\r
477 assign _u_VGA_fi_fifo2_write = fs_fifo2_write;
\r
478 assign _u_VGA_fi_fifo1_reset = _net_148|_net_119;
\r
479 assign _u_VGA_fi_fifo2_reset = _net_169|_reg_89;
\r
480 assign _u_EXP_i_Radrs = r_init_cnt;
\r
481 assign _u_EXP_fi_Rd_req = _net_167|_net_146|_net_105|_net_97;
\r
482 assign _u_EXP_i_Wdata = 8'b00001111;
\r
483 assign _u_EXP_i_Wadrs = r_init_cnt;
\r
484 assign _u_EXP_fi_Wr_req = _net_116;
\r
485 assign _net_68 = (trigger)==(3'b011);
\r
486 assign _net_69 = (~r_hld_vram_start)&(_u_VGA_o_vcnt[0]);
\r
487 assign _net_70 = r_reset&_net_69;
\r
488 assign _net_71 = r_hld_vram_start&(~(_u_VGA_o_vcnt[0]));
\r
489 assign _net_72 = r_reset&_net_71;
\r
490 assign _net_73 = (r_sec_cnt)==(26'b10111110101111000010000000);
\r
491 assign _net_74 = ~_net_73;
\r
492 assign _net_91 = (_net_61) < (14'b00000000101000);
\r
493 assign _reg_77_goto = _net_92;
\r
494 assign _net_92 = _reg_77&_net_91;
\r
495 assign _reg_80_goin = _net_93;
\r
496 assign _net_93 = _reg_77&_net_91;
\r
497 assign _net_94 = ~((r_init_cnt) < (14'b00000000101000));
\r
498 assign _reg_80_goto = _net_95;
\r
499 assign _net_95 = _reg_80&_net_94;
\r
500 assign _reg_76_goin = _net_96;
\r
501 assign _net_96 = _reg_80&_net_94;
\r
502 assign _net_97 = _reg_80&(~_net_94);
\r
503 assign _net_98 = _reg_80&(~_net_94);
\r
504 assign _net_99 = (_net_58) < (14'b00000000101000);
\r
505 assign _reg_82_goto = _net_100;
\r
506 assign _net_100 = _reg_82&_net_99;
\r
507 assign _reg_85_goin = _net_101;
\r
508 assign _net_101 = _reg_82&_net_99;
\r
509 assign _net_102 = ~((r_init_cnt) < (14'b00000000101000));
\r
510 assign _reg_85_goto = _net_103;
\r
511 assign _net_103 = _reg_85&_net_102;
\r
512 assign _reg_81_goin = _net_104;
\r
513 assign _net_104 = _reg_85&_net_102;
\r
514 assign _net_105 = _reg_85&(~_net_102);
\r
515 assign _net_106 = _reg_85&(~_net_102);
\r
516 assign _net_107 = ~((r_init_cnt) < (14'b10010110000000));
\r
517 assign _reg_87_goto = _net_114|_net_108;
\r
518 assign _net_108 = _reg_87&_net_107;
\r
519 assign _reg_86_goin = _net_109;
\r
520 assign _net_109 = _reg_87&_net_107;
\r
521 assign _net_110 = _reg_87&(~_net_107);
\r
522 assign _net_111 = _reg_87&(~_net_107);
\r
523 assign _net_112 = (_net_55) < (14'b10010110000000);
\r
524 assign _net_113 = _reg_87&(~_net_107);
\r
525 assign _net_114 = (_reg_87&(~_net_107))&_net_112;
\r
526 assign _reg_87_goin = _net_115;
\r
527 assign _net_115 = (_reg_87&(~_net_107))&_net_112;
\r
528 assign _net_116 = _reg_87&(~_net_107);
\r
529 assign _net_117 = _reg_87&(~_net_107);
\r
530 assign _net_118 = _reg_87&(~_net_107);
\r
531 assign _net_119 = fs_init|_reg_90;
\r
532 assign _net_120 = fs_init|_reg_89|_reg_90;
\r
533 assign _net_121 = fs_init|_reg_88|_reg_89;
\r
534 assign _net_122 = _reg_87_goin|_reg_87|_reg_88;
\r
535 assign _net_123 = _reg_86_goin|_reg_86|_reg_87;
\r
536 assign _net_124 = _reg_85_goin|_reg_85|_reg_86;
\r
537 assign _net_125 = _reg_85_goin|_reg_84|_reg_85;
\r
538 assign _net_126 = _reg_85_goin|_reg_83|_reg_84;
\r
539 assign _net_127 = _reg_85_goin|_reg_82|_reg_83;
\r
540 assign _net_128 = _reg_81_goin|_reg_81|_reg_82;
\r
541 assign _net_129 = _reg_80_goin|_reg_80|_reg_81;
\r
542 assign _net_130 = _reg_80_goin|_reg_79|_reg_80;
\r
543 assign _net_131 = _reg_80_goin|_reg_78|_reg_79;
\r
544 assign _net_132 = _reg_80_goin|_reg_77|_reg_78;
\r
545 assign _net_133 = _reg_76_goin|_reg_76|_reg_77;
\r
546 assign _net_134 = _reg_76_goin|_reg_75|_reg_76;
\r
547 assign _net_141 = (_net_64) < (14'b00000000101000);
\r
548 assign _reg_135_goto = _net_142;
\r
549 assign _net_142 = _reg_135&_net_141;
\r
550 assign _reg_138_goin = _net_143;
\r
551 assign _net_143 = _reg_135&_net_141;
\r
552 assign _net_144 = ~((r_init_cnt) < (14'b00000000101000));
\r
553 assign _reg_138_goto = _net_145;
\r
554 assign _net_145 = _reg_138&_net_144;
\r
555 assign _net_146 = _reg_138&(~_net_144);
\r
556 assign _net_147 = _reg_138&(~_net_144);
\r
557 assign _net_148 = fs_fifo1_charge|_reg_140;
\r
558 assign _net_149 = fs_fifo1_charge|_reg_139|_reg_140;
\r
559 assign _net_150 = _reg_138_goin|_reg_138|_reg_139;
\r
560 assign _net_151 = _reg_138_goin|_reg_137|_reg_138;
\r
561 assign _net_152 = _reg_138_goin|_reg_136|_reg_137;
\r
562 assign _net_153 = _reg_138_goin|_reg_135|_reg_136;
\r
563 assign _net_161 = (_net_67) < (14'b00000000101000);
\r
564 assign _reg_155_goto = _net_162;
\r
565 assign _net_162 = _reg_155&_net_161;
\r
566 assign _reg_158_goin = _net_163;
\r
567 assign _net_163 = _reg_155&_net_161;
\r
568 assign _net_164 = ~((r_init_cnt) < (14'b00000000101000));
\r
569 assign _reg_158_goto = _net_165;
\r
570 assign _net_165 = _reg_158&_net_164;
\r
571 assign _reg_154_goin = _net_166;
\r
572 assign _net_166 = _reg_158&_net_164;
\r
573 assign _net_167 = _reg_158&(~_net_164);
\r
574 assign _net_168 = _reg_158&(~_net_164);
\r
575 assign _net_169 = fs_fifo2_charge|_reg_160;
\r
576 assign _net_170 = fs_fifo2_charge|_reg_159|_reg_160;
\r
577 assign _net_171 = _reg_158_goin|_reg_158|_reg_159;
\r
578 assign _net_172 = _reg_158_goin|_reg_157|_reg_158;
\r
579 assign _net_173 = _reg_158_goin|_reg_156|_reg_157;
\r
580 assign _net_174 = _reg_158_goin|_reg_155|_reg_156;
\r
581 assign _net_175 = _reg_154_goin|_reg_154|_reg_155;
\r
582 assign _net_176 = (r_vram_start_adrs)==(14'b10010101011000);
\r
583 assign _net_177 = fs_vram_cnt_inc&_net_176;
\r
584 assign _net_178 = fs_vram_cnt_inc&(~_net_176);
\r
585 assign o_vsync = _u_VGA_o_vsync;
\r
586 assign o_hsync = _u_VGA_o_hsync;
\r
587 assign o_vga_r = _u_VGA_o_vga_r;
\r
588 assign o_vga_g = _u_VGA_o_vga_g;
\r
589 assign o_vga_b = _u_VGA_o_vga_b;
\r
590 assign o_LED = {5'b00000,i_sw,r_LED,_u_VGA_outled};
\r
591 always @(posedge m_clock or negedge p_reset)
\r
595 else trigger <= {trigger[1:0],1'b1};
\r
597 always @(posedge m_clock or negedge p_reset)
\r
601 else r_cnt <= ~r_cnt;
\r
603 always @(posedge m_clock or negedge p_reset)
\r
607 else if ((_reg_75))
\r
610 always @(posedge m_clock or negedge p_reset)
\r
613 r_sec_cnt <= 26'b00000000000000000000000000;
\r
614 else if ((_net_74)|(_net_73))
\r
615 r_sec_cnt <= ((_net_74) ?(r_sec_cnt)+(26'b00000000000000000000000001):26'b0)|
\r
616 ((_net_73) ?26'b00000000000000000000000000:26'b0);
\r
619 always @(posedge m_clock or negedge p_reset)
\r
623 else if ((_net_73))
\r
626 always @(posedge m_clock or negedge p_reset)
\r
629 r_init_cnt <= 14'b00000000000000;
\r
630 else if ((_reg_155)|(_reg_135)|(_net_110)|(_reg_82)|(_reg_159|_reg_139|_reg_88|_reg_86|_reg_81)|(_reg_77))
\r
631 r_init_cnt <= ((_reg_155) ?_net_67:14'b0)|
\r
632 ((_reg_135) ?_net_64:14'b0)|
\r
633 ((_net_110) ?_net_55:14'b0)|
\r
634 ((_reg_82) ?_net_58:14'b0)|
\r
635 ((_reg_159|_reg_139|_reg_88|_reg_86|_reg_81) ?14'b00000000000000:14'b0)|
\r
636 ((_reg_77) ?_net_61:14'b0);
\r
639 always @(posedge m_clock or negedge p_reset)
\r
642 r_vram_rddata <= 16'b0000000000000000;
\r
643 else if ((_reg_157|_reg_137|_reg_84|_reg_79))
\r
644 r_vram_rddata <= _u_EXP_o_Rdata;
\r
646 always @(posedge m_clock or negedge p_reset)
\r
649 r_vram_start_adrs <= 14'b00000000000000;
\r
650 else if ((_net_177)|(_net_178|_reg_76))
\r
651 r_vram_start_adrs <= ((_net_177) ?14'b00000000000000:14'b0)|
\r
652 ((_net_178|_reg_76) ?(r_vram_start_adrs)+(14'b00000000101000):14'b0);
\r
655 always @(posedge m_clock or negedge p_reset)
\r
658 r_hld_vram_start <= 1'b0;
\r
659 else r_hld_vram_start <= _u_VGA_o_vcnt[0];
\r
661 always @(posedge m_clock or negedge p_reset)
\r
665 else if ((_net_134))
\r
666 _reg_75 <= _reg_76;
\r
668 always @(posedge m_clock or negedge p_reset)
\r
672 else if ((_net_133))
\r
673 _reg_76 <= _reg_76_goin|(_reg_77&(~_reg_77_goto));
\r
675 always @(posedge m_clock or negedge p_reset)
\r
679 else if ((_net_132))
\r
680 _reg_77 <= _reg_78;
\r
682 always @(posedge m_clock or negedge p_reset)
\r
686 else if ((_net_131))
\r
687 _reg_78 <= _reg_79;
\r
689 always @(posedge m_clock or negedge p_reset)
\r
693 else if ((_net_130))
\r
694 _reg_79 <= _reg_80&(~_reg_80_goto);
\r
696 always @(posedge m_clock or negedge p_reset)
\r
700 else if ((_net_129))
\r
701 _reg_80 <= _reg_80_goin|_reg_81;
\r
703 always @(posedge m_clock or negedge p_reset)
\r
707 else if ((_net_128))
\r
708 _reg_81 <= _reg_81_goin|(_reg_82&(~_reg_82_goto));
\r
710 always @(posedge m_clock or negedge p_reset)
\r
714 else if ((_net_127))
\r
715 _reg_82 <= _reg_83;
\r
717 always @(posedge m_clock or negedge p_reset)
\r
721 else if ((_net_126))
\r
722 _reg_83 <= _reg_84;
\r
724 always @(posedge m_clock or negedge p_reset)
\r
728 else if ((_net_125))
\r
729 _reg_84 <= _reg_85&(~_reg_85_goto);
\r
731 always @(posedge m_clock or negedge p_reset)
\r
735 else if ((_net_124))
\r
736 _reg_85 <= _reg_85_goin|_reg_86;
\r
738 always @(posedge m_clock or negedge p_reset)
\r
742 else if ((_net_123))
\r
743 _reg_86 <= _reg_86_goin|(_reg_87&(~_reg_87_goto));
\r
745 always @(posedge m_clock or negedge p_reset)
\r
749 else if ((_net_122))
\r
750 _reg_87 <= _reg_87_goin|_reg_88;
\r
752 always @(posedge m_clock or negedge p_reset)
\r
756 else if ((_net_121))
\r
757 _reg_88 <= _reg_89;
\r
759 always @(posedge m_clock or negedge p_reset)
\r
763 else if ((_net_120))
\r
764 _reg_89 <= _reg_90|fs_init;
\r
766 always @(posedge m_clock or negedge p_reset)
\r
770 else if ((_reg_90))
\r
773 always @(posedge m_clock or negedge p_reset)
\r
777 else if ((_net_153))
\r
778 _reg_135 <= _reg_136;
\r
780 always @(posedge m_clock or negedge p_reset)
\r
784 else if ((_net_152))
\r
785 _reg_136 <= _reg_137;
\r
787 always @(posedge m_clock or negedge p_reset)
\r
791 else if ((_net_151))
\r
792 _reg_137 <= _reg_138&(~_reg_138_goto);
\r
794 always @(posedge m_clock or negedge p_reset)
\r
798 else if ((_net_150))
\r
799 _reg_138 <= _reg_138_goin|_reg_139;
\r
801 always @(posedge m_clock or negedge p_reset)
\r
805 else if ((_net_149))
\r
806 _reg_139 <= _reg_140|fs_fifo1_charge;
\r
808 always @(posedge m_clock or negedge p_reset)
\r
812 else if ((_reg_140))
\r
815 always @(posedge m_clock or negedge p_reset)
\r
819 else if ((_net_175))
\r
820 _reg_154 <= _reg_154_goin|(_reg_155&(~_reg_155_goto));
\r
822 always @(posedge m_clock or negedge p_reset)
\r
826 else if ((_net_174))
\r
827 _reg_155 <= _reg_156;
\r
829 always @(posedge m_clock or negedge p_reset)
\r
833 else if ((_net_173))
\r
834 _reg_156 <= _reg_157;
\r
836 always @(posedge m_clock or negedge p_reset)
\r
840 else if ((_net_172))
\r
841 _reg_157 <= _reg_158&(~_reg_158_goto);
\r
843 always @(posedge m_clock or negedge p_reset)
\r
847 else if ((_net_171))
\r
848 _reg_158 <= _reg_158_goin|_reg_159;
\r
850 always @(posedge m_clock or negedge p_reset)
\r
854 else if ((_net_170))
\r
855 _reg_159 <= _reg_160|fs_fifo2_charge;
\r
857 always @(posedge m_clock or negedge p_reset)
\r
861 else if ((_reg_160))
\r
866 Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Aug 10 20:43:49 2011
\r
867 Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp
\r
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