/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Jul 20 21:25:06 2011\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Tue Aug 09 20:17:19 2011\r
Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:\r
*/\r
\r
input fi_Rd_req;\r
output fo_Rd_ack;\r
reg [13:0] r_Radrs_hld;\r
- wire _u_VRAM_clk;\r
- wire [7:0] _u_VRAM_d;\r
- wire [13:0] _u_VRAM_ra;\r
- wire [13:0] _u_VRAM_wa;\r
- wire _u_VRAM_we;\r
+ wire _u_VRAM_clock;\r
+ wire [7:0] _u_VRAM_data;\r
+ wire [13:0] _u_VRAM_rdaddress;\r
+ wire [13:0] _u_VRAM_wraddress;\r
+ wire _u_VRAM_wren;\r
wire [7:0] _u_VRAM_q;\r
wire _u_VRAM_p_reset;\r
wire _u_VRAM_m_clock;\r
reg _reg_2;\r
wire _net_3;\r
wire _net_4;\r
-vram u_VRAM (.p_reset(p_reset), .m_clock(m_clock), .q(_u_VRAM_q), .we(_u_VRAM_we), .wa(_u_VRAM_wa), .ra(_u_VRAM_ra), .d(_u_VRAM_d), .clk(_u_VRAM_clk));\r
+vram u_VRAM (.p_reset(p_reset), .m_clock(m_clock), .q(_u_VRAM_q), .wren(_u_VRAM_wren), .wraddress(_u_VRAM_wraddress), .rdaddress(_u_VRAM_rdaddress), .data(_u_VRAM_data), .clock(_u_VRAM_clock));\r
\r
- assign _u_VRAM_d = i_Wdata;\r
- assign _u_VRAM_ra = ((_net_3)?i_Radrs:14'b0)|\r
+ assign _u_VRAM_clock = m_clock;\r
+ assign _u_VRAM_data = i_Wdata;\r
+ assign _u_VRAM_rdaddress = ((_net_3)?i_Radrs:14'b0)|\r
((_reg_1)?r_Radrs_hld:14'b0);\r
- assign _u_VRAM_wa = i_Wadrs;\r
- assign _u_VRAM_we = fi_Wr_req|\r
+ assign _u_VRAM_wraddress = i_Wadrs;\r
+ assign _u_VRAM_wren = fi_Wr_req|\r
((_net_0)?1'b0:1'b0);\r
assign _net_0 = ~fi_Wr_req;\r
assign _net_3 = fi_Rd_req|_reg_2;\r
assign _net_4 = fi_Rd_req|_reg_1|_reg_2;\r
assign o_Rdata = _u_VRAM_q;\r
assign fo_Rd_ack = _reg_1;\r
-always @(posedge p_reset)\r
+always @(negedge p_reset)\r
begin\r
-if (p_reset)\r
+if (~p_reset)\r
r_Radrs_hld <= 14'b00000000000000;\r
end\r
-always @(posedge m_clock or posedge p_reset)\r
+always @(posedge m_clock or negedge p_reset)\r
begin\r
-if (p_reset)\r
+if (~p_reset)\r
_reg_1 <= 1'b0;\r
else if ((_net_4)) \r
_reg_1 <= _reg_2|fi_Rd_req;\r
end\r
-always @(posedge m_clock or posedge p_reset)\r
+always @(posedge m_clock or negedge p_reset)\r
begin\r
-if (p_reset)\r
+if (~p_reset)\r
_reg_2 <= 1'b0;\r
else if ((_reg_2)) \r
_reg_2 <= 1'b0;\r
end\r
endmodule\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Jul 20 21:25:08 2011\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Tue Aug 09 20:17:20 2011\r
Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
*/\r
\r
wire _u_VRAMC_fo_Rd_ack;\r
wire _u_VRAMC_p_reset;\r
wire _u_VRAMC_m_clock;\r
- reg _reg_5;\r
- wire _net_6;\r
- wire _net_7;\r
vram_ctrl u_VRAMC (.p_reset(p_reset), .m_clock(m_clock), .fo_Rd_ack(_u_VRAMC_fo_Rd_ack), .fi_Rd_req(_u_VRAMC_fi_Rd_req), .fi_Wr_req(_u_VRAMC_fi_Wr_req), .o_Rdata(_u_VRAMC_o_Rdata), .i_Radrs(_u_VRAMC_i_Radrs), .i_Wadrs(_u_VRAMC_i_Wadrs), .i_Wdata(_u_VRAMC_i_Wdata));\r
\r
assign w_exp_q = {_u_VRAMC_o_Rdata[7],_u_VRAMC_o_Rdata[7],_u_VRAMC_o_Rdata[6],_u_VRAMC_o_Rdata[6],_u_VRAMC_o_Rdata[5],_u_VRAMC_o_Rdata[5],_u_VRAMC_o_Rdata[4],_u_VRAMC_o_Rdata[4],_u_VRAMC_o_Rdata[3],_u_VRAMC_o_Rdata[3],_u_VRAMC_o_Rdata[2],_u_VRAMC_o_Rdata[2],_u_VRAMC_o_Rdata[1],_u_VRAMC_o_Rdata[1],_u_VRAMC_o_Rdata[0],_u_VRAMC_o_Rdata[0]};\r
assign _u_VRAMC_i_Wadrs = i_Wadrs;\r
assign _u_VRAMC_i_Radrs = i_Radrs;\r
assign _u_VRAMC_fi_Wr_req = fi_Wr_req;\r
- assign _u_VRAMC_fi_Rd_req = _net_6;\r
- assign _net_6 = fi_Rd_req|_reg_5;\r
- assign _net_7 = fi_Rd_req|_reg_5;\r
+ assign _u_VRAMC_fi_Rd_req = fi_Rd_req;\r
assign o_Rdata = w_exp_q;\r
assign fo_Rd_ack = _u_VRAMC_fo_Rd_ack;\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_5 <= 1'b0;\r
-else if ((_reg_5)) \r
- _reg_5 <= 1'b0;\r
-end\r
endmodule\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Jul 20 21:25:09 2011\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Tue Aug 09 20:17:21 2011\r
Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
*/\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Mon Jul 25 23:44:36 2011\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Aug 10 20:42:35 2011\r
Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:\r
*/\r
\r
-module vga_gen ( i_clk50M , m_clock , p_reset , o_vsync , o_hsync , o_vga_r , o_vga_g , o_vga_b , i_we1 , i_wrdata1 , i_we2 , i_wrdata2 , i_fifo1_rst , i_fifo2_rst , outled );\r
+module vga_gen ( i_clk50M , m_clock , p_reset , o_vsync , o_hsync , o_vga_r , o_vga_g , o_vga_b , i_wrdata1 , i_wrdata2 , fi_fifo1_write , fi_fifo2_write , fi_fifo1_reset , fi_fifo2_reset , outled , o_vcnt );\r
input i_clk50M;\r
input m_clock;\r
input p_reset;\r
output [3:0] o_vga_r;\r
output [3:0] o_vga_g;\r
output [3:0] o_vga_b;\r
- input i_we1;\r
input [7:0] i_wrdata1;\r
- input i_we2;\r
input [7:0] i_wrdata2;\r
- input i_fifo1_rst;\r
- input i_fifo2_rst;\r
+ input fi_fifo1_write;\r
+ input fi_fifo2_write;\r
+ input fi_fifo1_reset;\r
+ input fi_fifo2_reset;\r
output outled;\r
- wire fi_fifo1_read;\r
- wire fi_fifo2_read;\r
+ output [9:0] o_vcnt;\r
+ wire fs_fifo1_read;\r
+ wire fs_fifo2_read;\r
+ wire fs_fifo1_exec;\r
+ wire fs_fifo2_exec;\r
+ reg [4:0] r_bit_number;\r
reg r_vsync;\r
reg r_hsync;\r
reg [9:0] r_vcnt;\r
reg testled;\r
reg [2:0] r_outcnt;\r
reg [6:0] r_outclr;\r
+ wire [23:0] w_rddata1;\r
+ wire [23:0] w_rddata2;\r
wire _u_FIFO_p_reset;\r
wire _u_FIFO_m_clock;\r
wire _u_FIFO_i_we1;\r
wire [7:0] _u_FIFO_i_wdata1;\r
wire _u_FIFO_i_we2;\r
wire [7:0] _u_FIFO_i_wdata2;\r
- wire [7:0] _u_FIFO_o_rddata1;\r
- wire [7:0] _u_FIFO_o_rddata2;\r
+ wire [23:0] _u_FIFO_o_rddata1;\r
+ wire [23:0] _u_FIFO_o_rddata2;\r
wire _u_FIFO_i_clock;\r
wire _u_FIFO_i_re1;\r
wire _u_FIFO_i_re2;\r
wire _net_35;\r
wire _net_36;\r
wire _net_37;\r
+ wire _net_38;\r
+ wire _net_39;\r
+ wire _net_40;\r
+ wire _net_41;\r
+ wire _net_42;\r
+ wire _net_43;\r
+ wire _net_44;\r
+ wire _net_45;\r
+ wire _net_46;\r
+ wire _net_47;\r
+ wire _net_48;\r
+ wire _net_49;\r
+ wire _net_50;\r
+ wire _net_51;\r
+ wire _net_52;\r
vga_ram u_FIFO (.o_rdack2(_u_FIFO_o_rdack2), .o_rdack1(_u_FIFO_o_rdack1), .i_fifo2_rst(_u_FIFO_i_fifo2_rst), .i_fifo1_rst(_u_FIFO_i_fifo1_rst), .i_re2(_u_FIFO_i_re2), .i_re1(_u_FIFO_i_re1), .i_clock(_u_FIFO_i_clock), .o_rddata2(_u_FIFO_o_rddata2), .o_rddata1(_u_FIFO_o_rddata1), .i_wdata2(_u_FIFO_i_wdata2), .i_we2(_u_FIFO_i_we2), .i_wdata1(_u_FIFO_i_wdata1), .i_we1(_u_FIFO_i_we1), .m_clock(_u_FIFO_m_clock), .p_reset(_u_FIFO_p_reset));\r
\r
- assign fi_fifo1_read = 1'b0;\r
- assign fi_fifo2_read = 1'b0;\r
- assign _u_FIFO_m_clock = i_clk50M;\r
- assign _u_FIFO_i_we1 = i_we1;\r
+ assign fs_fifo1_read = _net_20;\r
+ assign fs_fifo2_read = _net_17;\r
+ assign fs_fifo1_exec = _net_12;\r
+ assign fs_fifo2_exec = _net_10;\r
+ assign w_rddata1 = _u_FIFO_o_rddata1;\r
+ assign w_rddata2 = _u_FIFO_o_rddata2;\r
+ assign _u_FIFO_m_clock = m_clock;\r
+ assign _u_FIFO_i_we1 = fi_fifo1_write;\r
assign _u_FIFO_i_wdata1 = i_wrdata1;\r
- assign _u_FIFO_i_we2 = i_we2;\r
+ assign _u_FIFO_i_we2 = fi_fifo2_write;\r
assign _u_FIFO_i_wdata2 = i_wrdata2;\r
- assign _u_FIFO_i_clock = m_clock;\r
- assign _u_FIFO_i_re1 = fi_fifo1_read;\r
- assign _u_FIFO_i_re2 = fi_fifo2_read;\r
- assign _u_FIFO_i_fifo1_rst = i_fifo1_rst;\r
- assign _u_FIFO_i_fifo2_rst = i_fifo2_rst;\r
+ assign _u_FIFO_i_clock = i_clk50M;\r
+ assign _u_FIFO_i_re1 = fs_fifo1_read;\r
+ assign _u_FIFO_i_re2 = fs_fifo2_read;\r
+ assign _u_FIFO_i_fifo1_rst = fi_fifo1_reset;\r
+ assign _u_FIFO_i_fifo2_rst = fi_fifo2_reset;\r
assign _net_0 = (cnt)==(26'b01011111010111100001000000);\r
assign _net_1 = ~_net_0;\r
assign _net_2 = (r_hcnt) < (10'b1100100000);\r
assign _net_6 = (~_net_2)&_net_4;\r
assign _net_7 = (~_net_2)&(~_net_4);\r
assign _net_8 = ((r_hcnt) < (10'b1010000000))&((r_vcnt) < (10'b0111100000));\r
- assign _net_9 = (r_outcnt) < (3'b100);\r
+ assign _net_9 = r_vcnt[0];\r
assign _net_10 = _net_8&_net_9;\r
- assign _net_11 = _net_8&(~_net_9);\r
- assign _net_12 = _net_8&(~_net_9);\r
- assign _net_13 = ~(r_outclr[4]);\r
+ assign _net_11 = ~(r_vcnt[0]);\r
+ assign _net_12 = _net_8&_net_11;\r
+ assign _net_13 = (r_bit_number)==(5'b10111);\r
assign _net_14 = _net_8&_net_13;\r
- assign _net_15 = _net_8&(~_net_13);\r
- assign _net_16 = ~(r_outclr[5]);\r
- assign _net_17 = _net_8&_net_16;\r
- assign _net_18 = _net_8&(~_net_16);\r
- assign _net_19 = ~(r_outclr[6]);\r
- assign _net_20 = _net_8&_net_19;\r
- assign _net_21 = _net_8&(~_net_19);\r
+ assign _net_15 = r_vcnt[0];\r
+ assign _net_16 = _net_8&_net_13;\r
+ assign _net_17 = (_net_8&_net_13)&_net_15;\r
+ assign _net_18 = ~(r_vcnt[0]);\r
+ assign _net_19 = _net_8&_net_13;\r
+ assign _net_20 = (_net_8&_net_13)&_net_18;\r
+ assign _net_21 = _net_8&(~_net_13);\r
assign _net_22 = (r_hcnt)==(10'b1011110000);\r
assign _net_23 = ~_net_8;\r
assign _net_24 = (~_net_8)&_net_22;\r
assign _net_32 = (~_net_8)&_net_28;\r
assign _net_33 = (~_net_8)&_net_28;\r
assign _net_34 = (~_net_8)&_net_28;\r
- assign _net_35 = (r_vcnt)==(10'b0111101100);\r
- assign _net_36 = (r_vcnt)==(10'b0111101010);\r
- assign _net_37 = (r_vcnt)==(10'b0111100000);\r
+ assign _net_35 = (~_net_8)&_net_28;\r
+ assign _net_36 = (r_vcnt)==(10'b0111101100);\r
+ assign _net_37 = (r_vcnt)==(10'b0111101010);\r
+ assign _net_38 = (r_vcnt)==(10'b0111100000);\r
+ assign _net_39 = w_rddata1[r_bit_number];\r
+ assign _net_40 = fs_fifo1_exec&_net_39;\r
+ assign _net_41 = fs_fifo1_exec&_net_39;\r
+ assign _net_42 = fs_fifo1_exec&_net_39;\r
+ assign _net_43 = fs_fifo1_exec&(~_net_39);\r
+ assign _net_44 = fs_fifo1_exec&(~_net_39);\r
+ assign _net_45 = fs_fifo1_exec&(~_net_39);\r
+ assign _net_46 = w_rddata2[r_bit_number];\r
+ assign _net_47 = fs_fifo2_exec&_net_46;\r
+ assign _net_48 = fs_fifo2_exec&_net_46;\r
+ assign _net_49 = fs_fifo2_exec&_net_46;\r
+ assign _net_50 = fs_fifo2_exec&(~_net_46);\r
+ assign _net_51 = fs_fifo2_exec&(~_net_46);\r
+ assign _net_52 = fs_fifo2_exec&(~_net_46);\r
assign o_vsync = r_vsync;\r
assign o_hsync = r_hsync;\r
- assign o_vga_r = ((_net_30|_net_18)?4'b0000:4'b0)|\r
- ((_net_17)?~(r_outclr[3:0]):4'b0);\r
- assign o_vga_g = ((_net_31|_net_21)?4'b0000:4'b0)|\r
- ((_net_20)?~(r_outclr[3:0]):4'b0);\r
- assign o_vga_b = ((_net_32|_net_15)?4'b0000:4'b0)|\r
- ((_net_14)?~(r_outclr[3:0]):4'b0);\r
+ assign o_vga_r = ((_net_47|_net_40)?4'b1111:4'b0)|\r
+ ((_net_50|_net_43|_net_30)?4'b0000:4'b0);\r
+ assign o_vga_g = ((_net_48|_net_41)?4'b1111:4'b0)|\r
+ ((_net_51|_net_44|_net_31)?4'b0000:4'b0);\r
+ assign o_vga_b = ((_net_49|_net_42)?4'b1111:4'b0)|\r
+ ((_net_52|_net_45|_net_32)?4'b0000:4'b0);\r
assign outled = testled;\r
+ assign o_vcnt = r_vcnt;\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ r_bit_number <= 5'b00000;\r
+else if ((_net_21)|(_net_35|_net_14)) \r
+ r_bit_number <= ((_net_21) ?(r_bit_number)+(5'b00001):5'b0)|\r
+ ((_net_35|_net_14) ?5'b00000:5'b0);\r
+\r
+end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
r_vsync <= 1'b0;\r
-else if ((_net_36)|(_net_35)) \r
- r_vsync <= ((_net_36) ?1'b0:1'b0)|\r
- ((_net_35) ?1'b1:1'b0);\r
+else if ((_net_37)|(_net_36)) \r
+ r_vsync <= ((_net_37) ?1'b0:1'b0)|\r
+ ((_net_36) ?1'b1:1'b0);\r
\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
r_outcnt <= 3'b000;\r
-else if ((_net_33|_net_11)|(_net_10)) \r
- r_outcnt <= ((_net_33|_net_11) ?3'b000:3'b0)|\r
- ((_net_10) ?(r_outcnt)+(3'b001):3'b0);\r
-\r
+else if ((_net_33)) \r
+ r_outcnt <= 3'b000;\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
r_outclr <= 7'b0000000;\r
-else if ((_net_34)|(_net_12)) \r
- r_outclr <= ((_net_34) ?7'b0000000:7'b0)|\r
- ((_net_12) ?(r_outclr)+(7'b0000001):7'b0);\r
-\r
+else if ((_net_34)) \r
+ r_outclr <= 7'b0000000;\r
end\r
endmodule\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Mon Jul 25 23:44:38 2011\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Aug 10 20:42:38 2011\r
Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
*/\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Jul 20 21:25:12 2011\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Aug 06 22:05:03 2011\r
Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:\r
*/\r
\r
wire _u_VGARAM_p_reset;\r
wire _u_VGARAM_m_clock;\r
wire _u_VGARAM_i_we1;\r
- wire [31:0] _u_VGARAM_i_wdata1;\r
+ wire [7:0] _u_VGARAM_i_wdata1;\r
wire _u_VGARAM_i_we2;\r
- wire [31:0] _u_VGARAM_i_wdata2;\r
- wire [31:0] _u_VGARAM_o_rddata1;\r
- wire [31:0] _u_VGARAM_o_rddata2;\r
+ wire [7:0] _u_VGARAM_i_wdata2;\r
+ wire [7:0] _u_VGARAM_o_rddata1;\r
+ wire [7:0] _u_VGARAM_o_rddata2;\r
wire _u_VGARAM_i_clock;\r
wire _u_VGARAM_i_re1;\r
wire _u_VGARAM_i_re2;\r
assign o_vga_blue = w_blue;\r
assign o_h_cnt = r_h_cnt;\r
assign o_scanline = r_scanline_cnt;\r
-always @(posedge m_clock or posedge p_reset)\r
+always @(posedge m_clock or negedge p_reset)\r
begin\r
-if (p_reset)\r
+if (~p_reset)\r
r_v_sync <= 1'b0;\r
else if ((_net_15|_net_12)) \r
r_v_sync <= ~r_v_sync;\r
end\r
-always @(posedge m_clock or posedge p_reset)\r
+always @(posedge m_clock or negedge p_reset)\r
begin\r
-if (p_reset)\r
+if (~p_reset)\r
r_h_sync <= 1'b0;\r
else if ((_net_10|_net_7)) \r
r_h_sync <= ~r_h_sync;\r
end\r
-always @(posedge m_clock or posedge p_reset)\r
+always @(posedge m_clock or negedge p_reset)\r
begin\r
-if (p_reset)\r
+if (~p_reset)\r
r_vdata_flg <= 1'b0;\r
else if ((_net_14)|(_net_13)) \r
r_vdata_flg <= ((_net_14) ?1'b1:1'b0)|\r
((_net_13) ?1'b0:1'b0);\r
\r
end\r
-always @(posedge m_clock or posedge p_reset)\r
+always @(posedge m_clock or negedge p_reset)\r
begin\r
-if (p_reset)\r
+if (~p_reset)\r
r_hdata_flg <= 1'b0;\r
else if ((_net_9)|(_net_8)) \r
r_hdata_flg <= ((_net_9) ?1'b1:1'b0)|\r
((_net_8) ?1'b0:1'b0);\r
\r
end\r
-always @(posedge m_clock or posedge p_reset)\r
+always @(posedge m_clock or negedge p_reset)\r
begin\r
-if (p_reset)\r
+if (~p_reset)\r
r_h_cnt <= 10'b0000000000;\r
else if ((_net_11|_net_10|_net_9|_net_8)|(_net_7)) \r
r_h_cnt <= ((_net_11|_net_10|_net_9|_net_8) ?(r_h_cnt)+(10'b0000000001):10'b0)|\r
((_net_7) ?10'b0000000000:10'b0);\r
\r
end\r
-always @(posedge m_clock or posedge p_reset)\r
+always @(posedge m_clock or negedge p_reset)\r
begin\r
-if (p_reset)\r
+if (~p_reset)\r
r_v_cnt <= 19'b0000000000000000000;\r
else if ((_net_16|_net_15|_net_14|_net_13)|(_net_12)) \r
r_v_cnt <= ((_net_16|_net_15|_net_14|_net_13) ?(r_v_cnt)+(19'b0000000000000000001):19'b0)|\r
((_net_12) ?19'b0000000000000000000:19'b0);\r
\r
end\r
-always @(posedge m_clock or posedge p_reset)\r
+always @(posedge m_clock or negedge p_reset)\r
begin\r
-if (p_reset)\r
+if (~p_reset)\r
r_bit32_cnt <= 5'b00000;\r
else if ((fs_disp_data)|(_net_26)|(_net_27|_net_25)) \r
r_bit32_cnt <= ((fs_disp_data) ?(r_bit32_cnt)+(5'b00001):5'b0)|\r
((_net_27|_net_25) ?5'b00000:5'b0);\r
\r
end\r
-always @(posedge m_clock or posedge p_reset)\r
+always @(posedge m_clock or negedge p_reset)\r
begin\r
-if (p_reset)\r
+if (~p_reset)\r
r_flg <= 1'b0;\r
else if ((_net_145|_net_48)) \r
r_flg <= ~r_flg;\r
end\r
-always @(posedge m_clock or posedge p_reset)\r
+always @(posedge m_clock or negedge p_reset)\r
begin\r
-if (p_reset)\r
+if (~p_reset)\r
r1 <= 32'b00000000000000000000000000000000;\r
else if ((_net_42)) \r
r1 <= _u_VGARAM_o_rddata1;\r
end\r
-always @(posedge m_clock or posedge p_reset)\r
+always @(posedge m_clock or negedge p_reset)\r
begin\r
-if (p_reset)\r
+if (~p_reset)\r
r2 <= 32'b00000000000000000000000000000000;\r
else if ((_net_43)) \r
r2 <= _u_VGARAM_o_rddata2;\r
end\r
-always @(posedge m_clock or posedge p_reset)\r
+always @(posedge m_clock or negedge p_reset)\r
begin\r
-if (p_reset)\r
+if (~p_reset)\r
r_data_select_flag <= 1'b0;\r
else if ((_net_41)) \r
r_data_select_flag <= ~r_data_select_flag;\r
end\r
-always @(posedge m_clock or posedge p_reset)\r
+always @(posedge m_clock or negedge p_reset)\r
begin\r
-if (p_reset)\r
+if (~p_reset)\r
r_scanline_cnt <= 10'b0000000000;\r
else if ((_net_6)|(_net_4)) \r
r_scanline_cnt <= ((_net_6) ?10'b0000000000:10'b0)|\r
((_net_4) ?(r_scanline_cnt)+(10'b0000000001):10'b0);\r
\r
end\r
-always @(posedge m_clock or posedge p_reset)\r
+always @(posedge m_clock or negedge p_reset)\r
begin\r
-if (p_reset)\r
+if (~p_reset)\r
r_cnt_flg <= 1'b0;\r
else if ((_net_5)|(_net_3)) \r
r_cnt_flg <= ((_net_5) ?1'b0:1'b0)|\r
((_net_3) ?1'b1:1'b0);\r
\r
end\r
-always @(posedge m_clock or posedge p_reset)\r
+always @(posedge m_clock or negedge p_reset)\r
begin\r
-if (p_reset)\r
+if (~p_reset)\r
r_hld_h_sync <= 1'b0;\r
else r_hld_h_sync <= r_h_sync;\r
end\r
endmodule\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Jul 20 21:25:17 2011\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Aug 06 22:05:10 2011\r
Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
*/\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Jul 23 21:01:20 2011\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Aug 10 20:43:42 2011\r
Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:\r
*/\r
\r
-module vga_gen ( m_clock , p_reset , o_vsync , o_hsync , o_vga_r , o_vga_g , o_vga_b , outled );\r
+module vga_gen ( i_clk50M , m_clock , p_reset , o_vsync , o_hsync , o_vga_r , o_vga_g , o_vga_b , i_wrdata1 , i_wrdata2 , fi_fifo1_write , fi_fifo2_write , fi_fifo1_reset , fi_fifo2_reset , outled , o_vcnt );\r
+ input i_clk50M;\r
input m_clock;\r
input p_reset;\r
output o_vsync;\r
output [3:0] o_vga_r;\r
output [3:0] o_vga_g;\r
output [3:0] o_vga_b;\r
+ input [7:0] i_wrdata1;\r
+ input [7:0] i_wrdata2;\r
+ input fi_fifo1_write;\r
+ input fi_fifo2_write;\r
+ input fi_fifo1_reset;\r
+ input fi_fifo2_reset;\r
output outled;\r
+ output [9:0] o_vcnt;\r
+ wire fs_fifo1_read;\r
+ wire fs_fifo2_read;\r
+ wire fs_fifo1_exec;\r
+ wire fs_fifo2_exec;\r
+ reg [4:0] r_bit_number;\r
reg r_vsync;\r
reg r_hsync;\r
reg [9:0] r_vcnt;\r
reg testled;\r
reg [2:0] r_outcnt;\r
reg [6:0] r_outclr;\r
+ wire [23:0] w_rddata1;\r
+ wire [23:0] w_rddata2;\r
+ wire _u_FIFO_p_reset;\r
+ wire _u_FIFO_m_clock;\r
+ wire _u_FIFO_i_we1;\r
+ wire [7:0] _u_FIFO_i_wdata1;\r
+ wire _u_FIFO_i_we2;\r
+ wire [7:0] _u_FIFO_i_wdata2;\r
+ wire [23:0] _u_FIFO_o_rddata1;\r
+ wire [23:0] _u_FIFO_o_rddata2;\r
+ wire _u_FIFO_i_clock;\r
+ wire _u_FIFO_i_re1;\r
+ wire _u_FIFO_i_re2;\r
+ wire _u_FIFO_i_fifo1_rst;\r
+ wire _u_FIFO_i_fifo2_rst;\r
+ wire _u_FIFO_o_rdack1;\r
+ wire _u_FIFO_o_rdack2;\r
wire _net_0;\r
wire _net_1;\r
wire _net_2;\r
wire _net_35;\r
wire _net_36;\r
wire _net_37;\r
+ wire _net_38;\r
+ wire _net_39;\r
+ wire _net_40;\r
+ wire _net_41;\r
+ wire _net_42;\r
+ wire _net_43;\r
+ wire _net_44;\r
+ wire _net_45;\r
+ wire _net_46;\r
+ wire _net_47;\r
+ wire _net_48;\r
+ wire _net_49;\r
+ wire _net_50;\r
+ wire _net_51;\r
+ wire _net_52;\r
+vga_ram u_FIFO (.o_rdack2(_u_FIFO_o_rdack2), .o_rdack1(_u_FIFO_o_rdack1), .i_fifo2_rst(_u_FIFO_i_fifo2_rst), .i_fifo1_rst(_u_FIFO_i_fifo1_rst), .i_re2(_u_FIFO_i_re2), .i_re1(_u_FIFO_i_re1), .i_clock(_u_FIFO_i_clock), .o_rddata2(_u_FIFO_o_rddata2), .o_rddata1(_u_FIFO_o_rddata1), .i_wdata2(_u_FIFO_i_wdata2), .i_we2(_u_FIFO_i_we2), .i_wdata1(_u_FIFO_i_wdata1), .i_we1(_u_FIFO_i_we1), .m_clock(_u_FIFO_m_clock), .p_reset(_u_FIFO_p_reset));\r
\r
+ assign fs_fifo1_read = _net_20;\r
+ assign fs_fifo2_read = _net_17;\r
+ assign fs_fifo1_exec = _net_12;\r
+ assign fs_fifo2_exec = _net_10;\r
+ assign w_rddata1 = _u_FIFO_o_rddata1;\r
+ assign w_rddata2 = _u_FIFO_o_rddata2;\r
+ assign _u_FIFO_m_clock = m_clock;\r
+ assign _u_FIFO_i_we1 = fi_fifo1_write;\r
+ assign _u_FIFO_i_wdata1 = i_wrdata1;\r
+ assign _u_FIFO_i_we2 = fi_fifo2_write;\r
+ assign _u_FIFO_i_wdata2 = i_wrdata2;\r
+ assign _u_FIFO_i_clock = i_clk50M;\r
+ assign _u_FIFO_i_re1 = fs_fifo1_read;\r
+ assign _u_FIFO_i_re2 = fs_fifo2_read;\r
+ assign _u_FIFO_i_fifo1_rst = fi_fifo1_reset;\r
+ assign _u_FIFO_i_fifo2_rst = fi_fifo2_reset;\r
assign _net_0 = (cnt)==(26'b01011111010111100001000000);\r
assign _net_1 = ~_net_0;\r
assign _net_2 = (r_hcnt) < (10'b1100100000);\r
assign _net_6 = (~_net_2)&_net_4;\r
assign _net_7 = (~_net_2)&(~_net_4);\r
assign _net_8 = ((r_hcnt) < (10'b1010000000))&((r_vcnt) < (10'b0111100000));\r
- assign _net_9 = (r_outcnt) < (3'b100);\r
+ assign _net_9 = r_vcnt[0];\r
assign _net_10 = _net_8&_net_9;\r
- assign _net_11 = _net_8&(~_net_9);\r
- assign _net_12 = _net_8&(~_net_9);\r
- assign _net_13 = ~(r_outclr[4]);\r
+ assign _net_11 = ~(r_vcnt[0]);\r
+ assign _net_12 = _net_8&_net_11;\r
+ assign _net_13 = (r_bit_number)==(5'b10111);\r
assign _net_14 = _net_8&_net_13;\r
- assign _net_15 = _net_8&(~_net_13);\r
- assign _net_16 = ~(r_outclr[5]);\r
- assign _net_17 = _net_8&_net_16;\r
- assign _net_18 = _net_8&(~_net_16);\r
- assign _net_19 = ~(r_outclr[6]);\r
- assign _net_20 = _net_8&_net_19;\r
- assign _net_21 = _net_8&(~_net_19);\r
+ assign _net_15 = r_vcnt[0];\r
+ assign _net_16 = _net_8&_net_13;\r
+ assign _net_17 = (_net_8&_net_13)&_net_15;\r
+ assign _net_18 = ~(r_vcnt[0]);\r
+ assign _net_19 = _net_8&_net_13;\r
+ assign _net_20 = (_net_8&_net_13)&_net_18;\r
+ assign _net_21 = _net_8&(~_net_13);\r
assign _net_22 = (r_hcnt)==(10'b1011110000);\r
assign _net_23 = ~_net_8;\r
assign _net_24 = (~_net_8)&_net_22;\r
assign _net_32 = (~_net_8)&_net_28;\r
assign _net_33 = (~_net_8)&_net_28;\r
assign _net_34 = (~_net_8)&_net_28;\r
- assign _net_35 = (r_vcnt)==(10'b0111101100);\r
- assign _net_36 = (r_vcnt)==(10'b0111101010);\r
- assign _net_37 = (r_vcnt)==(10'b0111100000);\r
+ assign _net_35 = (~_net_8)&_net_28;\r
+ assign _net_36 = (r_vcnt)==(10'b0111101100);\r
+ assign _net_37 = (r_vcnt)==(10'b0111101010);\r
+ assign _net_38 = (r_vcnt)==(10'b0111100000);\r
+ assign _net_39 = w_rddata1[r_bit_number];\r
+ assign _net_40 = fs_fifo1_exec&_net_39;\r
+ assign _net_41 = fs_fifo1_exec&_net_39;\r
+ assign _net_42 = fs_fifo1_exec&_net_39;\r
+ assign _net_43 = fs_fifo1_exec&(~_net_39);\r
+ assign _net_44 = fs_fifo1_exec&(~_net_39);\r
+ assign _net_45 = fs_fifo1_exec&(~_net_39);\r
+ assign _net_46 = w_rddata2[r_bit_number];\r
+ assign _net_47 = fs_fifo2_exec&_net_46;\r
+ assign _net_48 = fs_fifo2_exec&_net_46;\r
+ assign _net_49 = fs_fifo2_exec&_net_46;\r
+ assign _net_50 = fs_fifo2_exec&(~_net_46);\r
+ assign _net_51 = fs_fifo2_exec&(~_net_46);\r
+ assign _net_52 = fs_fifo2_exec&(~_net_46);\r
assign o_vsync = r_vsync;\r
assign o_hsync = r_hsync;\r
- assign o_vga_r = ((_net_30|_net_18)?4'b0000:4'b0)|\r
- ((_net_17)?~(r_outclr[3:0]):4'b0);\r
- assign o_vga_g = ((_net_31|_net_21)?4'b0000:4'b0)|\r
- ((_net_20)?~(r_outclr[3:0]):4'b0);\r
- assign o_vga_b = ((_net_32|_net_15)?4'b0000:4'b0)|\r
- ((_net_14)?~(r_outclr[3:0]):4'b0);\r
+ assign o_vga_r = ((_net_47|_net_40)?4'b1111:4'b0)|\r
+ ((_net_50|_net_43|_net_30)?4'b0000:4'b0);\r
+ assign o_vga_g = ((_net_48|_net_41)?4'b1111:4'b0)|\r
+ ((_net_51|_net_44|_net_31)?4'b0000:4'b0);\r
+ assign o_vga_b = ((_net_49|_net_42)?4'b1111:4'b0)|\r
+ ((_net_52|_net_45|_net_32)?4'b0000:4'b0);\r
assign outled = testled;\r
+ assign o_vcnt = r_vcnt;\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ r_bit_number <= 5'b00000;\r
+else if ((_net_21)|(_net_35|_net_14)) \r
+ r_bit_number <= ((_net_21) ?(r_bit_number)+(5'b00001):5'b0)|\r
+ ((_net_35|_net_14) ?5'b00000:5'b0);\r
+\r
+end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
r_vsync <= 1'b0;\r
-else if ((_net_36)|(_net_35)) \r
- r_vsync <= ((_net_36) ?1'b0:1'b0)|\r
- ((_net_35) ?1'b1:1'b0);\r
+else if ((_net_37)|(_net_36)) \r
+ r_vsync <= ((_net_37) ?1'b0:1'b0)|\r
+ ((_net_36) ?1'b1:1'b0);\r
\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
r_outcnt <= 3'b000;\r
-else if ((_net_33|_net_11)|(_net_10)) \r
- r_outcnt <= ((_net_33|_net_11) ?3'b000:3'b0)|\r
- ((_net_10) ?(r_outcnt)+(3'b001):3'b0);\r
-\r
+else if ((_net_33)) \r
+ r_outcnt <= 3'b000;\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
r_outclr <= 7'b0000000;\r
-else if ((_net_34)|(_net_12)) \r
- r_outclr <= ((_net_34) ?7'b0000000:7'b0)|\r
- ((_net_12) ?(r_outclr)+(7'b0000001):7'b0);\r
-\r
+else if ((_net_34)) \r
+ r_outclr <= 7'b0000000;\r
end\r
endmodule\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Jul 23 21:01:23 2011\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Aug 10 20:43:46 2011\r
Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
*/\r
\r
output [3:0] o_vga_g;\r
output [3:0] o_vga_b;\r
output [7:0] o_LED;\r
+ reg [2:0] trigger;\r
reg r_cnt;\r
- reg [2:0] r_reset;\r
+ reg r_reset;\r
reg [25:0] r_sec_cnt;\r
reg r_LED;\r
+ reg [13:0] r_init_cnt;\r
+ reg [15:0] r_vram_rddata;\r
+ reg [13:0] r_vram_start_adrs;\r
+ reg r_hld_vram_start;\r
+ wire [7:0] w_wrdata1;\r
+ wire [7:0] w_wrdata2;\r
+ wire fs_fifo1_write;\r
+ wire fs_fifo2_write;\r
+ wire fs_init;\r
+ wire fs_fifo1_charge;\r
+ wire fs_fifo2_charge;\r
+ wire fs_vram_cnt_inc;\r
+ wire [13:0] _net_55;\r
+ wire [13:0] _net_58;\r
+ wire [13:0] _net_61;\r
+ wire [13:0] _net_64;\r
+ wire [13:0] _net_67;\r
+ wire _u_VGA_i_clk50M;\r
wire _u_VGA_m_clock;\r
wire _u_VGA_p_reset;\r
wire _u_VGA_o_vsync;\r
wire [3:0] _u_VGA_o_vga_r;\r
wire [3:0] _u_VGA_o_vga_g;\r
wire [3:0] _u_VGA_o_vga_b;\r
+ wire [7:0] _u_VGA_i_wrdata1;\r
+ wire [7:0] _u_VGA_i_wrdata2;\r
+ wire _u_VGA_fi_fifo1_write;\r
+ wire _u_VGA_fi_fifo2_write;\r
+ wire _u_VGA_fi_fifo1_reset;\r
+ wire _u_VGA_fi_fifo2_reset;\r
wire _u_VGA_outled;\r
- wire _net_38;\r
- wire _net_39;\r
-vga_gen u_VGA (.outled(_u_VGA_outled), .o_vga_b(_u_VGA_o_vga_b), .o_vga_g(_u_VGA_o_vga_g), .o_vga_r(_u_VGA_o_vga_r), .o_hsync(_u_VGA_o_hsync), .o_vsync(_u_VGA_o_vsync), .p_reset(_u_VGA_p_reset), .m_clock(_u_VGA_m_clock));\r
+ wire [9:0] _u_VGA_o_vcnt;\r
+ wire [13:0] _u_EXP_i_Radrs;\r
+ wire [15:0] _u_EXP_o_Rdata;\r
+ wire _u_EXP_fi_Rd_req;\r
+ wire _u_EXP_fo_Rd_ack;\r
+ wire [7:0] _u_EXP_i_Wdata;\r
+ wire [13:0] _u_EXP_i_Wadrs;\r
+ wire _u_EXP_fi_Wr_req;\r
+ wire _u_EXP_p_reset;\r
+ wire _u_EXP_m_clock;\r
+ wire _net_68;\r
+ wire _net_69;\r
+ wire _net_70;\r
+ wire _net_71;\r
+ wire _net_72;\r
+ wire _net_73;\r
+ wire _net_74;\r
+ reg _reg_75;\r
+ reg _reg_76;\r
+ reg _reg_77;\r
+ reg _reg_78;\r
+ reg _reg_79;\r
+ reg _reg_80;\r
+ reg _reg_81;\r
+ reg _reg_82;\r
+ reg _reg_83;\r
+ reg _reg_84;\r
+ reg _reg_85;\r
+ reg _reg_86;\r
+ reg _reg_87;\r
+ reg _reg_88;\r
+ reg _reg_89;\r
+ reg _reg_90;\r
+ wire _net_91;\r
+ wire _reg_77_goto;\r
+ wire _net_92;\r
+ wire _reg_80_goin;\r
+ wire _net_93;\r
+ wire _net_94;\r
+ wire _reg_80_goto;\r
+ wire _net_95;\r
+ wire _reg_76_goin;\r
+ wire _net_96;\r
+ wire _net_97;\r
+ wire _net_98;\r
+ wire _net_99;\r
+ wire _reg_82_goto;\r
+ wire _net_100;\r
+ wire _reg_85_goin;\r
+ wire _net_101;\r
+ wire _net_102;\r
+ wire _reg_85_goto;\r
+ wire _net_103;\r
+ wire _reg_81_goin;\r
+ wire _net_104;\r
+ wire _net_105;\r
+ wire _net_106;\r
+ wire _net_107;\r
+ wire _reg_87_goto;\r
+ wire _net_108;\r
+ wire _reg_86_goin;\r
+ wire _net_109;\r
+ wire _net_110;\r
+ wire _net_111;\r
+ wire _net_112;\r
+ wire _net_113;\r
+ wire _net_114;\r
+ wire _reg_87_goin;\r
+ wire _net_115;\r
+ wire _net_116;\r
+ wire _net_117;\r
+ wire _net_118;\r
+ wire _net_119;\r
+ wire _net_120;\r
+ wire _net_121;\r
+ wire _net_122;\r
+ wire _net_123;\r
+ wire _net_124;\r
+ wire _net_125;\r
+ wire _net_126;\r
+ wire _net_127;\r
+ wire _net_128;\r
+ wire _net_129;\r
+ wire _net_130;\r
+ wire _net_131;\r
+ wire _net_132;\r
+ wire _net_133;\r
+ wire _net_134;\r
+ reg _reg_135;\r
+ reg _reg_136;\r
+ reg _reg_137;\r
+ reg _reg_138;\r
+ reg _reg_139;\r
+ reg _reg_140;\r
+ wire _net_141;\r
+ wire _reg_135_goto;\r
+ wire _net_142;\r
+ wire _reg_138_goin;\r
+ wire _net_143;\r
+ wire _net_144;\r
+ wire _reg_138_goto;\r
+ wire _net_145;\r
+ wire _net_146;\r
+ wire _net_147;\r
+ wire _net_148;\r
+ wire _net_149;\r
+ wire _net_150;\r
+ wire _net_151;\r
+ wire _net_152;\r
+ wire _net_153;\r
+ reg _reg_154;\r
+ reg _reg_155;\r
+ reg _reg_156;\r
+ reg _reg_157;\r
+ reg _reg_158;\r
+ reg _reg_159;\r
+ reg _reg_160;\r
+ wire _net_161;\r
+ wire _reg_155_goto;\r
+ wire _net_162;\r
+ wire _reg_158_goin;\r
+ wire _net_163;\r
+ wire _net_164;\r
+ wire _reg_158_goto;\r
+ wire _net_165;\r
+ wire _reg_154_goin;\r
+ wire _net_166;\r
+ wire _net_167;\r
+ wire _net_168;\r
+ wire _net_169;\r
+ wire _net_170;\r
+ wire _net_171;\r
+ wire _net_172;\r
+ wire _net_173;\r
+ wire _net_174;\r
+ wire _net_175;\r
+ wire _net_176;\r
+ wire _net_177;\r
+ wire _net_178;\r
+exp_ctrl u_EXP (.p_reset(p_reset), .m_clock(m_clock), .fi_Wr_req(_u_EXP_fi_Wr_req), .i_Wadrs(_u_EXP_i_Wadrs), .i_Wdata(_u_EXP_i_Wdata), .fo_Rd_ack(_u_EXP_fo_Rd_ack), .fi_Rd_req(_u_EXP_fi_Rd_req), .o_Rdata(_u_EXP_o_Rdata), .i_Radrs(_u_EXP_i_Radrs));\r
+vga_gen u_VGA (.o_vcnt(_u_VGA_o_vcnt), .outled(_u_VGA_outled), .fi_fifo2_reset(_u_VGA_fi_fifo2_reset), .fi_fifo1_reset(_u_VGA_fi_fifo1_reset), .fi_fifo2_write(_u_VGA_fi_fifo2_write), .fi_fifo1_write(_u_VGA_fi_fifo1_write), .i_wrdata2(_u_VGA_i_wrdata2), .i_wrdata1(_u_VGA_i_wrdata1), .o_vga_b(_u_VGA_o_vga_b), .o_vga_g(_u_VGA_o_vga_g), .o_vga_r(_u_VGA_o_vga_r), .o_hsync(_u_VGA_o_hsync), .o_vsync(_u_VGA_o_vsync), .p_reset(_u_VGA_p_reset), .m_clock(_u_VGA_m_clock), .i_clk50M(_u_VGA_i_clk50M));\r
\r
+ assign w_wrdata1 = ((_reg_136|_reg_83)?r_vram_rddata[7:0]:8'b0)|\r
+ ((_reg_135|_reg_82)?r_vram_rddata[15:8]:8'b0);\r
+ assign w_wrdata2 = ((_reg_156|_reg_78)?r_vram_rddata[7:0]:8'b0)|\r
+ ((_reg_155|_reg_77)?r_vram_rddata[15:8]:8'b0);\r
+ assign fs_fifo1_write = _reg_136|_reg_135|_reg_83|_reg_82;\r
+ assign fs_fifo2_write = _reg_156|_reg_155|_reg_78|_reg_77;\r
+ assign fs_init = _net_68;\r
+ assign fs_fifo1_charge = _net_72;\r
+ assign fs_fifo2_charge = _net_70;\r
+ assign fs_vram_cnt_inc = _reg_154;\r
+ assign _net_55 = (r_init_cnt)+(14'b00000000000001);\r
+ assign _net_58 = (r_init_cnt)+(14'b00000000000001);\r
+ assign _net_61 = (r_init_cnt)+(14'b00000000000001);\r
+ assign _net_64 = (r_init_cnt)+(14'b00000000000001);\r
+ assign _net_67 = (r_init_cnt)+(14'b00000000000001);\r
+ assign _u_VGA_i_clk50M = m_clock;\r
assign _u_VGA_m_clock = r_cnt;\r
- assign _u_VGA_p_reset = r_reset[2];\r
- assign _net_38 = (r_sec_cnt)==(26'b10111110101111000010000000);\r
- assign _net_39 = ~_net_38;\r
+ assign _u_VGA_p_reset = r_reset;\r
+ assign _u_VGA_i_wrdata1 = w_wrdata1;\r
+ assign _u_VGA_i_wrdata2 = w_wrdata2;\r
+ assign _u_VGA_fi_fifo1_write = fs_fifo1_write;\r
+ assign _u_VGA_fi_fifo2_write = fs_fifo2_write;\r
+ assign _u_VGA_fi_fifo1_reset = _net_148|_net_119;\r
+ assign _u_VGA_fi_fifo2_reset = _net_169|_reg_89;\r
+ assign _u_EXP_i_Radrs = r_init_cnt;\r
+ assign _u_EXP_fi_Rd_req = _net_167|_net_146|_net_105|_net_97;\r
+ assign _u_EXP_i_Wdata = 8'b00001111;\r
+ assign _u_EXP_i_Wadrs = r_init_cnt;\r
+ assign _u_EXP_fi_Wr_req = _net_116;\r
+ assign _net_68 = (trigger)==(3'b011);\r
+ assign _net_69 = (~r_hld_vram_start)&(_u_VGA_o_vcnt[0]);\r
+ assign _net_70 = r_reset&_net_69;\r
+ assign _net_71 = r_hld_vram_start&(~(_u_VGA_o_vcnt[0]));\r
+ assign _net_72 = r_reset&_net_71;\r
+ assign _net_73 = (r_sec_cnt)==(26'b10111110101111000010000000);\r
+ assign _net_74 = ~_net_73;\r
+ assign _net_91 = (_net_61) < (14'b00000000101000);\r
+ assign _reg_77_goto = _net_92;\r
+ assign _net_92 = _reg_77&_net_91;\r
+ assign _reg_80_goin = _net_93;\r
+ assign _net_93 = _reg_77&_net_91;\r
+ assign _net_94 = ~((r_init_cnt) < (14'b00000000101000));\r
+ assign _reg_80_goto = _net_95;\r
+ assign _net_95 = _reg_80&_net_94;\r
+ assign _reg_76_goin = _net_96;\r
+ assign _net_96 = _reg_80&_net_94;\r
+ assign _net_97 = _reg_80&(~_net_94);\r
+ assign _net_98 = _reg_80&(~_net_94);\r
+ assign _net_99 = (_net_58) < (14'b00000000101000);\r
+ assign _reg_82_goto = _net_100;\r
+ assign _net_100 = _reg_82&_net_99;\r
+ assign _reg_85_goin = _net_101;\r
+ assign _net_101 = _reg_82&_net_99;\r
+ assign _net_102 = ~((r_init_cnt) < (14'b00000000101000));\r
+ assign _reg_85_goto = _net_103;\r
+ assign _net_103 = _reg_85&_net_102;\r
+ assign _reg_81_goin = _net_104;\r
+ assign _net_104 = _reg_85&_net_102;\r
+ assign _net_105 = _reg_85&(~_net_102);\r
+ assign _net_106 = _reg_85&(~_net_102);\r
+ assign _net_107 = ~((r_init_cnt) < (14'b10010110000000));\r
+ assign _reg_87_goto = _net_114|_net_108;\r
+ assign _net_108 = _reg_87&_net_107;\r
+ assign _reg_86_goin = _net_109;\r
+ assign _net_109 = _reg_87&_net_107;\r
+ assign _net_110 = _reg_87&(~_net_107);\r
+ assign _net_111 = _reg_87&(~_net_107);\r
+ assign _net_112 = (_net_55) < (14'b10010110000000);\r
+ assign _net_113 = _reg_87&(~_net_107);\r
+ assign _net_114 = (_reg_87&(~_net_107))&_net_112;\r
+ assign _reg_87_goin = _net_115;\r
+ assign _net_115 = (_reg_87&(~_net_107))&_net_112;\r
+ assign _net_116 = _reg_87&(~_net_107);\r
+ assign _net_117 = _reg_87&(~_net_107);\r
+ assign _net_118 = _reg_87&(~_net_107);\r
+ assign _net_119 = fs_init|_reg_90;\r
+ assign _net_120 = fs_init|_reg_89|_reg_90;\r
+ assign _net_121 = fs_init|_reg_88|_reg_89;\r
+ assign _net_122 = _reg_87_goin|_reg_87|_reg_88;\r
+ assign _net_123 = _reg_86_goin|_reg_86|_reg_87;\r
+ assign _net_124 = _reg_85_goin|_reg_85|_reg_86;\r
+ assign _net_125 = _reg_85_goin|_reg_84|_reg_85;\r
+ assign _net_126 = _reg_85_goin|_reg_83|_reg_84;\r
+ assign _net_127 = _reg_85_goin|_reg_82|_reg_83;\r
+ assign _net_128 = _reg_81_goin|_reg_81|_reg_82;\r
+ assign _net_129 = _reg_80_goin|_reg_80|_reg_81;\r
+ assign _net_130 = _reg_80_goin|_reg_79|_reg_80;\r
+ assign _net_131 = _reg_80_goin|_reg_78|_reg_79;\r
+ assign _net_132 = _reg_80_goin|_reg_77|_reg_78;\r
+ assign _net_133 = _reg_76_goin|_reg_76|_reg_77;\r
+ assign _net_134 = _reg_76_goin|_reg_75|_reg_76;\r
+ assign _net_141 = (_net_64) < (14'b00000000101000);\r
+ assign _reg_135_goto = _net_142;\r
+ assign _net_142 = _reg_135&_net_141;\r
+ assign _reg_138_goin = _net_143;\r
+ assign _net_143 = _reg_135&_net_141;\r
+ assign _net_144 = ~((r_init_cnt) < (14'b00000000101000));\r
+ assign _reg_138_goto = _net_145;\r
+ assign _net_145 = _reg_138&_net_144;\r
+ assign _net_146 = _reg_138&(~_net_144);\r
+ assign _net_147 = _reg_138&(~_net_144);\r
+ assign _net_148 = fs_fifo1_charge|_reg_140;\r
+ assign _net_149 = fs_fifo1_charge|_reg_139|_reg_140;\r
+ assign _net_150 = _reg_138_goin|_reg_138|_reg_139;\r
+ assign _net_151 = _reg_138_goin|_reg_137|_reg_138;\r
+ assign _net_152 = _reg_138_goin|_reg_136|_reg_137;\r
+ assign _net_153 = _reg_138_goin|_reg_135|_reg_136;\r
+ assign _net_161 = (_net_67) < (14'b00000000101000);\r
+ assign _reg_155_goto = _net_162;\r
+ assign _net_162 = _reg_155&_net_161;\r
+ assign _reg_158_goin = _net_163;\r
+ assign _net_163 = _reg_155&_net_161;\r
+ assign _net_164 = ~((r_init_cnt) < (14'b00000000101000));\r
+ assign _reg_158_goto = _net_165;\r
+ assign _net_165 = _reg_158&_net_164;\r
+ assign _reg_154_goin = _net_166;\r
+ assign _net_166 = _reg_158&_net_164;\r
+ assign _net_167 = _reg_158&(~_net_164);\r
+ assign _net_168 = _reg_158&(~_net_164);\r
+ assign _net_169 = fs_fifo2_charge|_reg_160;\r
+ assign _net_170 = fs_fifo2_charge|_reg_159|_reg_160;\r
+ assign _net_171 = _reg_158_goin|_reg_158|_reg_159;\r
+ assign _net_172 = _reg_158_goin|_reg_157|_reg_158;\r
+ assign _net_173 = _reg_158_goin|_reg_156|_reg_157;\r
+ assign _net_174 = _reg_158_goin|_reg_155|_reg_156;\r
+ assign _net_175 = _reg_154_goin|_reg_154|_reg_155;\r
+ assign _net_176 = (r_vram_start_adrs)==(14'b10010101011000);\r
+ assign _net_177 = fs_vram_cnt_inc&_net_176;\r
+ assign _net_178 = fs_vram_cnt_inc&(~_net_176);\r
assign o_vsync = _u_VGA_o_vsync;\r
assign o_hsync = _u_VGA_o_hsync;\r
assign o_vga_r = _u_VGA_o_vga_r;\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
+ trigger <= 3'b000;\r
+else trigger <= {trigger[1:0],1'b1};\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
r_cnt <= 1'b0;\r
else r_cnt <= ~r_cnt;\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
- r_reset <= 3'b000;\r
-else r_reset <= {r_reset[1:0],1'b1};\r
+ r_reset <= 1'b0;\r
+else if ((_reg_75)) \r
+ r_reset <= 1'b1;\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
r_sec_cnt <= 26'b00000000000000000000000000;\r
-else if ((_net_39)|(_net_38)) \r
- r_sec_cnt <= ((_net_39) ?(r_sec_cnt)+(26'b00000000000000000000000001):26'b0)|\r
- ((_net_38) ?26'b00000000000000000000000000:26'b0);\r
+else if ((_net_74)|(_net_73)) \r
+ r_sec_cnt <= ((_net_74) ?(r_sec_cnt)+(26'b00000000000000000000000001):26'b0)|\r
+ ((_net_73) ?26'b00000000000000000000000000:26'b0);\r
\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
r_LED <= 1'b0;\r
-else if ((_net_38)) \r
+else if ((_net_73)) \r
r_LED <= ~r_LED;\r
end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ r_init_cnt <= 14'b00000000000000;\r
+else if ((_reg_155)|(_reg_135)|(_net_110)|(_reg_82)|(_reg_159|_reg_139|_reg_88|_reg_86|_reg_81)|(_reg_77)) \r
+ r_init_cnt <= ((_reg_155) ?_net_67:14'b0)|\r
+ ((_reg_135) ?_net_64:14'b0)|\r
+ ((_net_110) ?_net_55:14'b0)|\r
+ ((_reg_82) ?_net_58:14'b0)|\r
+ ((_reg_159|_reg_139|_reg_88|_reg_86|_reg_81) ?14'b00000000000000:14'b0)|\r
+ ((_reg_77) ?_net_61:14'b0);\r
+\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ r_vram_rddata <= 16'b0000000000000000;\r
+else if ((_reg_157|_reg_137|_reg_84|_reg_79)) \r
+ r_vram_rddata <= _u_EXP_o_Rdata;\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ r_vram_start_adrs <= 14'b00000000000000;\r
+else if ((_net_177)|(_net_178|_reg_76)) \r
+ r_vram_start_adrs <= ((_net_177) ?14'b00000000000000:14'b0)|\r
+ ((_net_178|_reg_76) ?(r_vram_start_adrs)+(14'b00000000101000):14'b0);\r
+\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ r_hld_vram_start <= 1'b0;\r
+else r_hld_vram_start <= _u_VGA_o_vcnt[0];\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_75 <= 1'b0;\r
+else if ((_net_134)) \r
+ _reg_75 <= _reg_76;\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_76 <= 1'b0;\r
+else if ((_net_133)) \r
+ _reg_76 <= _reg_76_goin|(_reg_77&(~_reg_77_goto));\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_77 <= 1'b0;\r
+else if ((_net_132)) \r
+ _reg_77 <= _reg_78;\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_78 <= 1'b0;\r
+else if ((_net_131)) \r
+ _reg_78 <= _reg_79;\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_79 <= 1'b0;\r
+else if ((_net_130)) \r
+ _reg_79 <= _reg_80&(~_reg_80_goto);\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_80 <= 1'b0;\r
+else if ((_net_129)) \r
+ _reg_80 <= _reg_80_goin|_reg_81;\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_81 <= 1'b0;\r
+else if ((_net_128)) \r
+ _reg_81 <= _reg_81_goin|(_reg_82&(~_reg_82_goto));\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_82 <= 1'b0;\r
+else if ((_net_127)) \r
+ _reg_82 <= _reg_83;\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_83 <= 1'b0;\r
+else if ((_net_126)) \r
+ _reg_83 <= _reg_84;\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_84 <= 1'b0;\r
+else if ((_net_125)) \r
+ _reg_84 <= _reg_85&(~_reg_85_goto);\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_85 <= 1'b0;\r
+else if ((_net_124)) \r
+ _reg_85 <= _reg_85_goin|_reg_86;\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_86 <= 1'b0;\r
+else if ((_net_123)) \r
+ _reg_86 <= _reg_86_goin|(_reg_87&(~_reg_87_goto));\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_87 <= 1'b0;\r
+else if ((_net_122)) \r
+ _reg_87 <= _reg_87_goin|_reg_88;\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_88 <= 1'b0;\r
+else if ((_net_121)) \r
+ _reg_88 <= _reg_89;\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_89 <= 1'b0;\r
+else if ((_net_120)) \r
+ _reg_89 <= _reg_90|fs_init;\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_90 <= 1'b0;\r
+else if ((_reg_90)) \r
+ _reg_90 <= 1'b0;\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_135 <= 1'b0;\r
+else if ((_net_153)) \r
+ _reg_135 <= _reg_136;\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_136 <= 1'b0;\r
+else if ((_net_152)) \r
+ _reg_136 <= _reg_137;\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_137 <= 1'b0;\r
+else if ((_net_151)) \r
+ _reg_137 <= _reg_138&(~_reg_138_goto);\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_138 <= 1'b0;\r
+else if ((_net_150)) \r
+ _reg_138 <= _reg_138_goin|_reg_139;\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_139 <= 1'b0;\r
+else if ((_net_149)) \r
+ _reg_139 <= _reg_140|fs_fifo1_charge;\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_140 <= 1'b0;\r
+else if ((_reg_140)) \r
+ _reg_140 <= 1'b0;\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_154 <= 1'b0;\r
+else if ((_net_175)) \r
+ _reg_154 <= _reg_154_goin|(_reg_155&(~_reg_155_goto));\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_155 <= 1'b0;\r
+else if ((_net_174)) \r
+ _reg_155 <= _reg_156;\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_156 <= 1'b0;\r
+else if ((_net_173)) \r
+ _reg_156 <= _reg_157;\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_157 <= 1'b0;\r
+else if ((_net_172)) \r
+ _reg_157 <= _reg_158&(~_reg_158_goto);\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_158 <= 1'b0;\r
+else if ((_net_171)) \r
+ _reg_158 <= _reg_158_goin|_reg_159;\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_159 <= 1'b0;\r
+else if ((_net_170)) \r
+ _reg_159 <= _reg_160|fs_fifo2_charge;\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_160 <= 1'b0;\r
+else if ((_reg_160)) \r
+ _reg_160 <= 1'b0;\r
+end\r
endmodule\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Jul 23 21:01:24 2011\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Aug 10 20:43:49 2011\r
Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
*/\r
reg [7:0] r_ram_data;\r
\r
assign q = r_ram_data;\r
-always @(posedge m_clock)\r
+always @(posedge clock)\r
begin\r
if (wren )\r
m_vram[wraddress] <= data;\r
end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- r_ram_data <= 8'b00000000;\r
-else r_ram_data <= m_vram[rdaddress];\r
-end\r
+always @(posedge clock)\r
+ begin\r
+ r_ram_data <= m_vram[rdaddress];\r
+ end\r
endmodule\r
+\r
/*\r
Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Jul 20 21:25:23 2011\r
Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
declare exp_ctrl {
- input iRadrs[14] ;
- output oRdata[16] ;
- func_in fiRd_req( iRadrs ) ;
- func_out foRd_ack( oRdata ) ;
+ input i_Radrs[14] ;
+ output o_Rdata[16] ;
+ func_in fi_Rd_req( i_Radrs ) ;
+ func_out fo_Rd_ack( o_Rdata ) ;
- input iWdata[8] ;
- input iWadrs[14] ;
- func_in fiWr_req( iWadrs, iWdata ) ;
+ input i_Wdata[8] ;
+ input i_Wadrs[14] ;
+ func_in fi_Wr_req( i_Wadrs, i_Wdata ) ;
}
if( u_VRAMC.fo_Rd_ack ) fo_Rd_ack( w_exp_q ) ;
- func fi_Rd_req seq {
+ func fi_Rd_req {
u_VRAMC.fi_Rd_req( i_Radrs ) ;
}
output o_vga_g[4] ;
output o_vga_b[4] ;
- input i_we1 ;
input i_wrdata1[8] ;
- input i_we2 ;
input i_wrdata2[8] ;
- input i_fifo1_rst ;
- input i_fifo2_rst ;
-
+ func_in fi_fifo1_write( i_wrdata1 ) ;
+ func_in fi_fifo2_write( i_wrdata2 ) ;
+ func_in fi_fifo1_reset() ;
+ func_in fi_fifo2_reset() ;
+
output outled ;
+ output o_vcnt[10] ;
}
module vga_gen {
- func_self fi_fifo1_read() ;
- func_self fi_fifo2_read() ;
+ func_self fs_fifo1_read() ;
+ func_self fs_fifo2_read() ;
+
+ func_self fs_fifo1_exec() ;
+ func_self fs_fifo2_exec() ;
+
+ reg r_bit_number[5] = 0 ;
reg r_vsync = 0 ;
reg r_hsync = 0 ;
reg testled = 0 ;
reg r_outcnt[3] = 0 ;
reg r_outclr[7] = 0 ;
+
+ wire w_rddata1[24] ;
+ wire w_rddata2[24] ;
vga_ram u_FIFO ;
{
/* FIFO assign */
- u_FIFO.m_clock = i_clk50M ;
- u_FIFO.i_we1 = i_we1 ;
+ u_FIFO.i_clock = i_clk50M ;
+ u_FIFO.m_clock = m_clock ;
+
+ u_FIFO.i_we1 = fi_fifo1_write ;
+ u_FIFO.i_we2 = fi_fifo2_write ;
u_FIFO.i_wdata1 = i_wrdata1 ;
- u_FIFO.i_we2 = i_we2 ;
u_FIFO.i_wdata2 = i_wrdata2 ;
- u_FIFO.i_fifo1_rst = i_fifo1_rst ;
- u_FIFO.i_fifo2_rst = i_fifo2_rst ;
- u_FIFO.i_clock = m_clock ;
-
+ u_FIFO.i_fifo1_rst = fi_fifo1_reset ;
+ u_FIFO.i_fifo2_rst = fi_fifo2_reset ;
+ u_FIFO.i_re1 = fs_fifo1_read ;
+ u_FIFO.i_re2 = fs_fifo2_read ;
+ w_rddata1 = u_FIFO.o_rddata1 ;
+ w_rddata2 = u_FIFO.o_rddata2 ;
+ o_vcnt = r_vcnt ;
+
/* LED test */
outled = testled ;
o_vsync = r_vsync ;
r_hcnt++ ;
} else {
r_hcnt := 0 ;
- if( r_vcnt < V_BACKP_MAX ) r_vcnt++ ;
- else r_vcnt := 0 ;
+ if( r_vcnt < V_BACKP_MAX ) {
+ r_vcnt++ ;
+ } else {
+ r_vcnt := 0 ;
+ }
}
if( ( r_hcnt < H_ACT_MAX ) && ( r_vcnt < V_ACT_MAX ) ) {
+
+ any {
+ ~r_vcnt[0] : fs_fifo1_exec() ;
+ r_vcnt[0] : fs_fifo2_exec() ;
+ }
+
+ any {
+ r_bit_number == 5'd23 : {
+ r_bit_number := 0 ;
+ any {
+ ~r_vcnt[0] : fs_fifo1_read() ;
+ r_vcnt[0] : fs_fifo2_read() ;
+ }
+ }
+ else : {
+ r_bit_number++ ;
+ }
+ }
/* \83J\83\89\81[\83o\81[\8dì\90¬ */
+/*
if( r_outcnt < 3'd4 ) {
r_outcnt++ ;
} else {
if( ~r_outclr[6]) o_vga_g = ~r_outclr[3:0] ;
else o_vga_g = 0 ;
-
+*/
} else {
any {
r_hcnt == H_ACT_MAX : {
o_vga_b = 0 ;
r_outcnt := 0 ;
r_outclr := 0 ;
+ r_bit_number := 0 ;
}
r_hcnt == H_FRONTP_MAX : {
r_hsync := 0 ;
}
}
- func fi_fifo1_read {
- u_FIFO.i_re1 = 1 ;
+ func fs_fifo1_exec {
+ if(w_rddata1[r_bit_number]){
+ o_vga_r = 4'b1111 ;
+ o_vga_g = 4'b1111 ;
+ o_vga_b = 4'b1111 ;
+ } else {
+ o_vga_r = 4'b0000 ;
+ o_vga_g = 4'b0000 ;
+ o_vga_b = 4'b0000 ;
+ }
}
- func fi_fifo2_read {
- u_FIFO.i_re2 = 1 ;
+ func fs_fifo2_exec {
+ if(w_rddata2[r_bit_number]){
+ o_vga_r = 4'b1111 ;
+ o_vga_g = 4'b1111 ;
+ o_vga_b = 4'b1111 ;
+ } else {
+ o_vga_r = 4'b0000 ;
+ o_vga_g = 4'b0000 ;
+ o_vga_b = 4'b0000 ;
+
+ }
}
-
} //module end
\ No newline at end of file
func_self vgaram_read1() ;
func_self vgaram_read2() ;
- vga_ram u_VGARAM ;
+ vga_ram u_VGARAM ; //vga_ram \83C\83\93\83X\83^\83\93\83X\90é\8c¾
{
/* vga_top - vga_ram assign */
input i_we2 ;
input i_wdata2[8] ;
- output o_rddata1[8] ;
- output o_rddata2[8] ;
+ output o_rddata1[24] ;
+ output o_rddata2[24] ;
input i_clock ;
output o_rdack1 ;\r
output o_rdack2 ;\r
\r
- reg r_hld_re1 = 0 ;\r
- reg r_hld_re2 = 0 ;\r
-\r
reg [7:0] r_wradrs1 = 0 ;\r
reg [7:0] r_wradrs2 = 0 ;\r
reg [7:0] r_rdadrs1 = 0 ;\r
if( i_re2 ) r_rdadrs2 = r_rdadrs2 + 3'd3 ;\r
end\r
\r
- always @ ( posedge m_clock ) begin\r
- r_hld_re1 = i_re1 ;\r
- r_hld_re2 = i_re2 ;\r
- end\r
-\r
assign o_rddata1 = {\r
mem1[r_rdadrs1+8'd2],\r
mem1[r_rdadrs1+8'd1],\r
*/\r
\r
#include "vga_gen.nsl"\r
-//#include "exp_ctrl.nsh"\r
+#include "exp_ctrl.nsh"\r
\r
#define CNT1S 26'd50000000\r
\r
output o_LED[8] ;\r
}\r
module vga_top {\r
+ reg trigger[3] = 0 ;\r
reg r_cnt = 0 ;\r
- reg r_reset[3] = 0b000 ;\r
+ reg r_reset = 0b0 ;\r
\r
reg r_sec_cnt[26] = 0 ;\r
reg r_LED = 0 ;\r
+ \r
+ reg r_init_cnt[14] = 0 ;\r
+ reg r_vram_rddata[16] = 0 ;\r
+ reg r_vram_start_adrs[14] = 0 ;\r
+ reg r_hld_vram_start = 0 ;\r
+ \r
+ wire w_wrdata1[8] ;\r
+ wire w_wrdata2[8] ;\r
+ func_self fs_fifo1_write( w_wrdata1 ) ;\r
+ func_self fs_fifo2_write( w_wrdata2 ) ;\r
+ \r
+ func_self fs_init() ;\r
+ \r
+ func_self fs_fifo1_charge ;\r
+ func_self fs_fifo2_charge ;\r
+\r
+ func_self fs_vram_cnt_inc ;\r
\r
vga_gen u_VGA ;\r
-// exp_ctrl u_EXP ;\r
+ exp_ctrl u_EXP ;\r
\r
{\r
- o_vsync = u_VGA.o_vsync ;\r
- o_hsync = u_VGA.o_hsync ;\r
- o_vga_r = u_VGA.o_vga_r ;\r
- o_vga_g = u_VGA.o_vga_g ;\r
- o_vga_b = u_VGA.o_vga_b ;\r
+ /* VGA */\r
+ o_vsync = u_VGA.o_vsync ;\r
+ o_hsync = u_VGA.o_hsync ;\r
+ o_vga_r = u_VGA.o_vga_r ;\r
+ o_vga_g = u_VGA.o_vga_g ;\r
+ o_vga_b = u_VGA.o_vga_b ;\r
+ u_VGA.i_clk50M = m_clock ;\r
+ r_hld_vram_start := u_VGA.o_vcnt[0] ;\r
+\r
+ trigger := { trigger[1:0], 0b1 } ;\r
+ if(trigger == 3'b011) fs_init() ;\r
+\r
+ if(r_reset) {\r
+ any {\r
+ r_hld_vram_start & ~u_VGA.o_vcnt[0] : { //FIFO1\82ð\93Ç\82Ý\8fo\82·\83^\83C\83~\83\93\83O\r
+ fs_fifo1_charge() ;\r
+ }\r
+ ~r_hld_vram_start & u_VGA.o_vcnt[0] : { //FIFO2\82ð\93Ç\82Ý\8fo\82·\83^\83C\83~\83\93\83O\r
+ fs_fifo2_charge() ;\r
+ }\r
+ }\r
+ }\r
\r
any {\r
r_sec_cnt == CNT1S : {\r
}\r
}\r
\r
+\r
r_cnt := ~r_cnt ;\r
o_LED = { 0b00000, i_sw, r_LED, u_VGA.outled } ;\r
\r
- r_reset := { r_reset[1:0], 0b1 } ;\r
- u_VGA.p_reset = r_reset[2] ;\r
u_VGA.m_clock = r_cnt ;\r
+ u_VGA.p_reset = r_reset ;\r
+\r
+\r
+ }\r
+ \r
+ \r
+ func fs_init seq {\r
+ u_VGA.fi_fifo1_reset() ;\r
+ u_VGA.fi_fifo2_reset() ;\r
+\r
+ /* VRAM\8f\89\8aú\89»\83\8b\81[\83`\83\93 */\r
+ for(r_init_cnt:=0;r_init_cnt<9600;r_init_cnt++) {\r
+ u_EXP.fi_Wr_req(r_init_cnt, 8'h0F) ;\r
+ }\r
+ \r
+ for(r_init_cnt:=0;r_init_cnt<40;r_init_cnt++) {\r
+ u_EXP.fi_Rd_req(r_init_cnt) ;\r
+ r_vram_rddata := u_EXP.o_Rdata ;\r
+ fs_fifo1_write(r_vram_rddata[7:0]) ;\r
+ fs_fifo1_write(r_vram_rddata[15:8]) ;\r
+ }\r
+ \r
+ for(r_init_cnt:=0;r_init_cnt<40;r_init_cnt++) {\r
+ u_EXP.fi_Rd_req(r_init_cnt) ;\r
+ r_vram_rddata := u_EXP.o_Rdata ;\r
+ fs_fifo2_write(r_vram_rddata[7:0]) ;\r
+ fs_fifo2_write(r_vram_rddata[15:8]) ;\r
+ }\r
+\r
+ r_vram_start_adrs := r_vram_start_adrs + 14'd40 ;\r
+ r_reset := 0b1 ;\r
+ }\r
+ \r
+ func fs_fifo1_write {\r
+ u_VGA.fi_fifo1_write(w_wrdata1) ;\r
+ }\r
+\r
+ func fs_fifo2_write {\r
+ u_VGA.fi_fifo2_write(w_wrdata2) ; \r
+ }\r
+ \r
+ func fs_fifo1_charge seq {\r
+ u_VGA.fi_fifo1_reset() ;\r
+\r
+ for(r_init_cnt:=0;r_init_cnt<40;r_init_cnt++) {\r
+ u_EXP.fi_Rd_req(r_init_cnt) ;\r
+ r_vram_rddata := u_EXP.o_Rdata ;\r
+ fs_fifo1_write(r_vram_rddata[7:0]) ;\r
+ fs_fifo1_write(r_vram_rddata[15:8]) ;\r
+ }\r
+ }\r
+\r
+ func fs_fifo2_charge seq {\r
+ u_VGA.fi_fifo2_reset() ;\r
+\r
+ for(r_init_cnt:=0;r_init_cnt<40;r_init_cnt++) {\r
+ u_EXP.fi_Rd_req(r_init_cnt) ;\r
+ r_vram_rddata := u_EXP.o_Rdata ;\r
+ fs_fifo2_write(r_vram_rddata[7:0]) ;\r
+ fs_fifo2_write(r_vram_rddata[15:8]) ;\r
+ } \r
+ fs_vram_cnt_inc() ;\r
+ }\r
+\r
+ func fs_vram_cnt_inc {\r
+ any {\r
+ r_vram_start_adrs == 14'd9560 :\r
+ r_vram_start_adrs := 0 ;\r
+ else : {\r
+ r_vram_start_adrs := r_vram_start_adrs + 14'd40 ;\r
+ }\r
+ }\r
}\r
}
\ No newline at end of file
* comment : Hokuto Ujou Danjin Ken!
*/
declare vram {
- input clk ;
- input d[8] ;
- input ra[14] ;
- input wa[14] ;
- input we ;
+ input clock ;
+ input data[8] ;
+ input rdaddress[14] ;
+ input wraddress[14] ;
+ input wren ;
output q[8] ;
}
\ No newline at end of file
reg r_Radrs_hld[14] = 0 ;
{
+ u_VRAM.clock = m_clock ;
+
/* Memory Terminal Assign */
if(~fi_Wr_req) {
- u_VRAM.we = 0 ;
+ u_VRAM.wren = 0 ;
}
}
func fi_Wr_req {
- u_VRAM.we = 1 ;
- u_VRAM.d = i_Wdata ;
- u_VRAM.wa = i_Wadrs ;
+ u_VRAM.wren = 1 ;
+ u_VRAM.data = i_Wdata ;
+ u_VRAM.wraddress = i_Wadrs ;
}
func fi_Rd_req seq {
- u_VRAM.ra = i_Radrs ;
+ u_VRAM.rdaddress = i_Radrs ;
{
- u_VRAM.ra = r_Radrs_hld ;
+ u_VRAM.rdaddress = r_Radrs_hld ;
fo_Rd_ack( u_VRAM.q ) ;
}
}
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