2 p_reset, m_clock, i_we1,
\r
3 i_wadrs1, i_wdata1, i_we2,
\r
4 i_wadrs2, i_wdata2, i_radrs1,
\r
5 o_rdasrs1, i_radrs2, o_rdasrs2,
\r
13 input [4:0] i_wadrs1 ;
\r
14 input [31:0] i_wdata1 ;
\r
18 input [4:0] i_wadrs2 ;
\r
19 input [31:0] i_wdata2 ;
\r
21 input [4:0] i_radrs1 ;
\r
22 output [31:0] o_rdasrs1 ;
\r
24 input [4:0] i_radrs2 ;
\r
25 output [31:0] o_rdasrs2 ;
\r
27 reg [4:0] r_rdadrs1 ;
\r
28 reg [4:0] r_rdadrs2 ;
\r
30 (* remstyle = "no_rw_check" *) reg [31:0] mem1[31:0] ;
\r
31 (* remstyle = "no_rw_check" *) reg [31:0] mem2[31:0] ;
\r
33 // memory write command
\r
34 always @ (posedge m_clock) begin
\r
35 if(we1) mem1[i_wadrs1] <= i_wdata1 ;
\r
36 if(we2) mem1[i_wadrs2] <= i_wdata2 ;
\r
39 always @ (posedge i_clock) begin
\r
40 r_rdadrs1 <= i_radrs1 ;
\r
41 r_rdadrs2 <= i_radrs2 ;
\r
44 assign q = mem1[r_rdadrs1] ;
\r
45 assign q = mem2[r_rdadrs2] ;
\r