Change-Id: I137d6edab408f7479f683f5dbf06fc84d2331595

diff --git a/VGADisplay/Verilog/vga_generate.v b/VGADisplay/Verilog/vga_generate.v
index 57555a9..6b4d2ca 100644 (file)
--- a/VGADisplay/Verilog/vga_generate.v
+++ b/VGADisplay/Verilog/vga_generate.v
@@ -1,653 +1,4 @@
 /*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Fri Jul 08 20:38:17 2011\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Tue Jul 12 23:16:45 2011\r
  Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:\r
 */\r
-\r
-module vga_generate ( p_reset , m_clock , i_pix32_data , o_v_sync , o_h_sync , o_vga_red , o_vga_green , o_vga_blue , o_h_cnt , fi_ack_req_32dot , fo_req_32dot );\r
-  input p_reset;\r
-  input m_clock;\r
-  input [31:0] i_pix32_data;\r
-  output o_v_sync;\r
-  output o_h_sync;\r
-  output [3:0] o_vga_red;\r
-  output [3:0] o_vga_green;\r
-  output [3:0] o_vga_blue;\r
-  output [9:0] o_h_cnt;\r
-  input fi_ack_req_32dot;\r
-  output fo_req_32dot;\r
-  wire fs_disp_data;\r
-  reg r_v_sync;\r
-  reg r_h_sync;\r
-  reg r_h_flg;\r
-  reg r_vdata_flg;\r
-  reg r_hdata_flg;\r
-  reg [9:0] r_h_cnt;\r
-  reg [18:0] r_v_cnt;\r
-  reg [4:0] r_bit32_cnt;\r
-  reg r_flg;\r
-  reg r_cnt;\r
-  reg [31:0] r1;\r
-  reg [31:0] r2;\r
-  reg r_data_select_flag;\r
-  wire [3:0] w_red;\r
-  wire [3:0] w_green;\r
-  wire [3:0] w_blue;\r
-  wire w_disp_data;\r
-  wire _net_0;\r
-  wire _net_1;\r
-  wire _net_2;\r
-  wire _net_3;\r
-  wire _net_4;\r
-  wire _net_5;\r
-  wire _net_6;\r
-  wire _net_7;\r
-  wire _net_8;\r
-  wire _net_9;\r
-  wire _net_10;\r
-  wire _net_11;\r
-  wire _net_12;\r
-  wire _net_13;\r
-  wire _net_14;\r
-  wire _net_15;\r
-  wire _net_16;\r
-  wire _net_17;\r
-  wire _net_18;\r
-  wire _net_19;\r
-  wire _net_20;\r
-  wire _net_21;\r
-  wire _net_22;\r
-  wire _net_23;\r
-  wire _net_24;\r
-  wire _net_25;\r
-  wire _net_26;\r
-  wire _net_27;\r
-  wire _net_28;\r
-  wire _net_29;\r
-  wire _net_30;\r
-  wire _net_31;\r
-  wire _net_32;\r
-  wire _net_33;\r
-  wire _net_34;\r
-  wire _net_35;\r
-  wire _net_36;\r
-  wire _net_37;\r
-  wire _net_38;\r
-  wire _net_39;\r
-  wire _net_40;\r
-  wire _net_41;\r
-  wire _net_42;\r
-  wire _net_43;\r
-  wire _net_44;\r
-  wire _net_45;\r
-  wire _net_46;\r
-  wire _net_47;\r
-  wire _net_48;\r
-  wire _net_49;\r
-  wire _net_50;\r
-  wire _net_51;\r
-  wire _net_52;\r
-  wire _net_53;\r
-  wire _net_54;\r
-  wire _net_55;\r
-  wire _net_56;\r
-  wire _net_57;\r
-  wire _net_58;\r
-  wire _net_59;\r
-  wire _net_60;\r
-  wire _net_61;\r
-  wire _net_62;\r
-  wire _net_63;\r
-  wire _net_64;\r
-  wire _net_65;\r
-  wire _net_66;\r
-  wire _net_67;\r
-  wire _net_68;\r
-  wire _net_69;\r
-  wire _net_70;\r
-  wire _net_71;\r
-  wire _net_72;\r
-  wire _net_73;\r
-  wire _net_74;\r
-  wire _net_75;\r
-  wire _net_76;\r
-  wire _net_77;\r
-  wire _net_78;\r
-  wire _net_79;\r
-  wire _net_80;\r
-  wire _net_81;\r
-  wire _net_82;\r
-  wire _net_83;\r
-  wire _net_84;\r
-  wire _net_85;\r
-  wire _net_86;\r
-  wire _net_87;\r
-  wire _net_88;\r
-  wire _net_89;\r
-  wire _net_90;\r
-  wire _net_91;\r
-  wire _net_92;\r
-  wire _net_93;\r
-  wire _net_94;\r
-  wire _net_95;\r
-  wire _net_96;\r
-  wire _net_97;\r
-  wire _net_98;\r
-  wire _net_99;\r
-  wire _net_100;\r
-  wire _net_101;\r
-  wire _net_102;\r
-  wire _net_103;\r
-  wire _net_104;\r
-  wire _net_105;\r
-  wire _net_106;\r
-  wire _net_107;\r
-  wire _net_108;\r
-  wire _net_109;\r
-  wire _net_110;\r
-  wire _net_111;\r
-  wire _net_112;\r
-  wire _net_113;\r
-  wire _net_114;\r
-  wire _net_115;\r
-  wire _net_116;\r
-  wire _net_117;\r
-  wire _net_118;\r
-  wire _net_119;\r
-  wire _net_120;\r
-  wire _net_121;\r
-  wire _net_122;\r
-  wire _net_123;\r
-  wire _net_124;\r
-  wire _net_125;\r
-  wire _net_126;\r
-  wire _net_127;\r
-  wire _net_128;\r
-  wire _net_129;\r
-  wire _net_130;\r
-  wire _net_131;\r
-  wire _net_132;\r
-  wire _net_133;\r
-  wire _net_134;\r
-  wire _net_135;\r
-  wire _net_136;\r
-  wire _net_137;\r
-  wire _net_138;\r
-  wire _net_139;\r
-  wire _net_140;\r
-  wire _net_141;\r
-  wire _net_142;\r
-  wire _net_143;\r
-  wire _net_144;\r
-  wire _net_145;\r
-  wire _net_146;\r
-  wire _net_147;\r
-  wire _net_148;\r
-  wire _net_149;\r
-  wire _net_150;\r
-  wire _net_151;\r
-  wire _net_152;\r
-  wire _net_153;\r
-  wire _net_154;\r
-  wire _net_155;\r
-  wire _net_156;\r
-  wire _net_157;\r
-  wire _net_158;\r
-  wire _net_159;\r
-  wire _net_160;\r
-  wire _net_161;\r
-  wire _net_162;\r
-  wire _net_163;\r
-  wire _net_164;\r
-  wire _net_165;\r
-  wire _net_166;\r
-  wire _net_167;\r
-  wire _net_168;\r
-  wire _net_169;\r
-  wire _net_170;\r
-  wire _net_171;\r
-  wire _net_172;\r
-  wire _net_173;\r
-  wire _net_174;\r
-  wire _net_175;\r
-  wire _net_176;\r
-  wire _net_177;\r
-  wire _net_178;\r
-  wire _net_179;\r
-  wire _net_180;\r
-  wire _net_181;\r
-  wire _net_182;\r
-  wire _net_183;\r
-  wire _net_184;\r
-  wire _net_185;\r
-  wire _net_186;\r
-  wire _net_187;\r
-  wire _net_188;\r
-  wire _net_189;\r
-  wire _net_190;\r
-  wire _net_191;\r
-  wire _net_192;\r
-  wire _net_193;\r
-  wire _net_194;\r
-  wire _net_195;\r
-  wire _net_196;\r
-  wire _net_197;\r
-  wire _net_198;\r
-  wire _net_199;\r
-  wire _net_200;\r
-  wire _net_201;\r
-  wire _net_202;\r
-  wire _net_203;\r
-  wire _net_204;\r
-  wire _net_205;\r
-  wire _net_206;\r
-  wire _net_207;\r
-  wire _net_208;\r
-  wire _net_209;\r
-  wire _net_210;\r
-  wire _net_211;\r
-  wire _net_212;\r
-  wire _net_213;\r
-  wire _net_214;\r
-  wire _net_215;\r
-  wire _net_216;\r
-  wire _net_217;\r
-  wire _net_218;\r
-\r
-   assign  fs_disp_data = _net_10;\r
-   assign  w_red = 4'b0000;\r
-   assign  w_green = 4'b0000;\r
-   assign  w_blue = ((_net_20)?4'b0000:4'b0)|\r
-    ((_net_18)?4'b1111:4'b0);\r
-   assign  w_disp_data = ((_net_218)?r2[31]:1'b0)|\r
-    ((_net_215)?r2[30]:1'b0)|\r
-    ((_net_212)?r2[29]:1'b0)|\r
-    ((_net_209)?r2[28]:1'b0)|\r
-    ((_net_206)?r2[27]:1'b0)|\r
-    ((_net_203)?r2[26]:1'b0)|\r
-    ((_net_200)?r2[25]:1'b0)|\r
-    ((_net_197)?r2[24]:1'b0)|\r
-    ((_net_194)?r2[23]:1'b0)|\r
-    ((_net_191)?r2[22]:1'b0)|\r
-    ((_net_188)?r2[21]:1'b0)|\r
-    ((_net_185)?r2[20]:1'b0)|\r
-    ((_net_182)?r2[19]:1'b0)|\r
-    ((_net_179)?r2[18]:1'b0)|\r
-    ((_net_176)?r2[17]:1'b0)|\r
-    ((_net_173)?r2[16]:1'b0)|\r
-    ((_net_170)?r2[15]:1'b0)|\r
-    ((_net_167)?r2[14]:1'b0)|\r
-    ((_net_164)?r2[13]:1'b0)|\r
-    ((_net_161)?r2[12]:1'b0)|\r
-    ((_net_158)?r2[11]:1'b0)|\r
-    ((_net_155)?r2[10]:1'b0)|\r
-    ((_net_152)?r2[9]:1'b0)|\r
-    ((_net_149)?r2[8]:1'b0)|\r
-    ((_net_146)?r2[7]:1'b0)|\r
-    ((_net_143)?r2[6]:1'b0)|\r
-    ((_net_140)?r2[5]:1'b0)|\r
-    ((_net_137)?r2[4]:1'b0)|\r
-    ((_net_134)?r2[3]:1'b0)|\r
-    ((_net_131)?r2[2]:1'b0)|\r
-    ((_net_128)?r2[1]:1'b0)|\r
-    ((_net_124)?r2[0]:1'b0)|\r
-    ((_net_121)?r1[31]:1'b0)|\r
-    ((_net_118)?r1[30]:1'b0)|\r
-    ((_net_115)?r1[29]:1'b0)|\r
-    ((_net_112)?r1[28]:1'b0)|\r
-    ((_net_109)?r1[27]:1'b0)|\r
-    ((_net_106)?r1[26]:1'b0)|\r
-    ((_net_103)?r1[25]:1'b0)|\r
-    ((_net_100)?r1[24]:1'b0)|\r
-    ((_net_97)?r1[23]:1'b0)|\r
-    ((_net_94)?r1[22]:1'b0)|\r
-    ((_net_91)?r1[21]:1'b0)|\r
-    ((_net_88)?r1[20]:1'b0)|\r
-    ((_net_85)?r1[19]:1'b0)|\r
-    ((_net_82)?r1[18]:1'b0)|\r
-    ((_net_79)?r1[17]:1'b0)|\r
-    ((_net_76)?r1[16]:1'b0)|\r
-    ((_net_73)?r1[15]:1'b0)|\r
-    ((_net_70)?r1[14]:1'b0)|\r
-    ((_net_67)?r1[13]:1'b0)|\r
-    ((_net_64)?r1[12]:1'b0)|\r
-    ((_net_61)?r1[11]:1'b0)|\r
-    ((_net_58)?r1[10]:1'b0)|\r
-    ((_net_55)?r1[9]:1'b0)|\r
-    ((_net_52)?r1[8]:1'b0)|\r
-    ((_net_49)?r1[7]:1'b0)|\r
-    ((_net_46)?r1[6]:1'b0)|\r
-    ((_net_43)?r1[5]:1'b0)|\r
-    ((_net_40)?r1[4]:1'b0)|\r
-    ((_net_37)?r1[3]:1'b0)|\r
-    ((_net_34)?r1[2]:1'b0)|\r
-    ((_net_31)?r1[1]:1'b0)|\r
-    ((_net_27)?r1[0]:1'b0);\r
-   assign  _net_0 = (r_h_cnt)==(10'b1100100000);\r
-   assign  _net_1 = (r_h_cnt)==(10'b1100001110);\r
-   assign  _net_2 = (r_h_cnt)==(10'b0010001110);\r
-   assign  _net_3 = (r_h_cnt)==(10'b0001100000);\r
-   assign  _net_4 = (((~_net_0)&(~_net_1))&(~_net_2))&(~_net_3);\r
-   assign  _net_5 = (r_v_cnt)==(19'b1100101110000011111);\r
-   assign  _net_6 = (r_v_cnt)==(19'b1100011110011011111);\r
-   assign  _net_7 = (r_v_cnt)==(19'b0000110000011011111);\r
-   assign  _net_8 = (r_v_cnt)==(19'b0000000011000111111);\r
-   assign  _net_9 = (((~_net_5)&(~_net_6))&(~_net_7))&(~_net_8);\r
-   assign  _net_10 = r_hdata_flg&r_vdata_flg;\r
-   assign  _net_11 = (((r_h_cnt) >= ((10'b0010001110)+(10'b1001100001)))&((r_h_cnt) <= (((10'b1100001110)+(10'b1001100001))+(10'b1111111111))))&((r_v_cnt) >= ((19'b0000110000011011111)+(19'b1111111111111100001)))&((r_v_cnt) <= (((19'b1100011110011011111)+(19'b1111111111111100001))+(19'b1111111111111111111)));\r
-   assign  _net_12 = (r_bit32_cnt)==(5'b00000);\r
-   assign  _net_13 = _net_11&_net_12;\r
-   assign  _net_14 = (r_bit32_cnt)==(5'b11111);\r
-   assign  _net_15 = _net_11&_net_14;\r
-   assign  _net_16 = _net_11&(~_net_14);\r
-   assign  _net_17 = ~_net_11;\r
-   assign  _net_18 = r_hdata_flg&r_vdata_flg;\r
-   assign  _net_19 = ~_net_18;\r
-   assign  _net_20 = ~_net_18;\r
-   assign  _net_21 = ~_net_18;\r
-   assign  _net_22 = fi_ack_req_32dot&r_data_select_flag;\r
-   assign  _net_23 = fi_ack_req_32dot&(~r_data_select_flag);\r
-   assign  _net_24 = ~r_flg;\r
-   assign  _net_25 = (r_bit32_cnt)==(5'b11111);\r
-   assign  _net_26 = fs_disp_data&_net_24;\r
-   assign  _net_27 = (fs_disp_data&_net_24)&_net_25;\r
-   assign  _net_28 = (fs_disp_data&_net_24)&_net_25;\r
-   assign  _net_29 = (r_bit32_cnt)==(5'b11110);\r
-   assign  _net_30 = fs_disp_data&_net_24;\r
-   assign  _net_31 = (fs_disp_data&_net_24)&_net_29;\r
-   assign  _net_32 = (r_bit32_cnt)==(5'b11101);\r
-   assign  _net_33 = fs_disp_data&_net_24;\r
-   assign  _net_34 = (fs_disp_data&_net_24)&_net_32;\r
-   assign  _net_35 = (r_bit32_cnt)==(5'b11100);\r
-   assign  _net_36 = fs_disp_data&_net_24;\r
-   assign  _net_37 = (fs_disp_data&_net_24)&_net_35;\r
-   assign  _net_38 = (r_bit32_cnt)==(5'b11011);\r
-   assign  _net_39 = fs_disp_data&_net_24;\r
-   assign  _net_40 = (fs_disp_data&_net_24)&_net_38;\r
-   assign  _net_41 = (r_bit32_cnt)==(5'b11010);\r
-   assign  _net_42 = fs_disp_data&_net_24;\r
-   assign  _net_43 = (fs_disp_data&_net_24)&_net_41;\r
-   assign  _net_44 = (r_bit32_cnt)==(5'b11001);\r
-   assign  _net_45 = fs_disp_data&_net_24;\r
-   assign  _net_46 = (fs_disp_data&_net_24)&_net_44;\r
-   assign  _net_47 = (r_bit32_cnt)==(5'b11000);\r
-   assign  _net_48 = fs_disp_data&_net_24;\r
-   assign  _net_49 = (fs_disp_data&_net_24)&_net_47;\r
-   assign  _net_50 = (r_bit32_cnt)==(5'b10111);\r
-   assign  _net_51 = fs_disp_data&_net_24;\r
-   assign  _net_52 = (fs_disp_data&_net_24)&_net_50;\r
-   assign  _net_53 = (r_bit32_cnt)==(5'b10110);\r
-   assign  _net_54 = fs_disp_data&_net_24;\r
-   assign  _net_55 = (fs_disp_data&_net_24)&_net_53;\r
-   assign  _net_56 = (r_bit32_cnt)==(5'b10101);\r
-   assign  _net_57 = fs_disp_data&_net_24;\r
-   assign  _net_58 = (fs_disp_data&_net_24)&_net_56;\r
-   assign  _net_59 = (r_bit32_cnt)==(5'b10100);\r
-   assign  _net_60 = fs_disp_data&_net_24;\r
-   assign  _net_61 = (fs_disp_data&_net_24)&_net_59;\r
-   assign  _net_62 = (r_bit32_cnt)==(5'b10011);\r
-   assign  _net_63 = fs_disp_data&_net_24;\r
-   assign  _net_64 = (fs_disp_data&_net_24)&_net_62;\r
-   assign  _net_65 = (r_bit32_cnt)==(5'b10010);\r
-   assign  _net_66 = fs_disp_data&_net_24;\r
-   assign  _net_67 = (fs_disp_data&_net_24)&_net_65;\r
-   assign  _net_68 = (r_bit32_cnt)==(5'b10001);\r
-   assign  _net_69 = fs_disp_data&_net_24;\r
-   assign  _net_70 = (fs_disp_data&_net_24)&_net_68;\r
-   assign  _net_71 = (r_bit32_cnt)==(5'b10000);\r
-   assign  _net_72 = fs_disp_data&_net_24;\r
-   assign  _net_73 = (fs_disp_data&_net_24)&_net_71;\r
-   assign  _net_74 = (r_bit32_cnt)==(5'b01111);\r
-   assign  _net_75 = fs_disp_data&_net_24;\r
-   assign  _net_76 = (fs_disp_data&_net_24)&_net_74;\r
-   assign  _net_77 = (r_bit32_cnt)==(5'b01110);\r
-   assign  _net_78 = fs_disp_data&_net_24;\r
-   assign  _net_79 = (fs_disp_data&_net_24)&_net_77;\r
-   assign  _net_80 = (r_bit32_cnt)==(5'b01101);\r
-   assign  _net_81 = fs_disp_data&_net_24;\r
-   assign  _net_82 = (fs_disp_data&_net_24)&_net_80;\r
-   assign  _net_83 = (r_bit32_cnt)==(5'b01100);\r
-   assign  _net_84 = fs_disp_data&_net_24;\r
-   assign  _net_85 = (fs_disp_data&_net_24)&_net_83;\r
-   assign  _net_86 = (r_bit32_cnt)==(5'b01011);\r
-   assign  _net_87 = fs_disp_data&_net_24;\r
-   assign  _net_88 = (fs_disp_data&_net_24)&_net_86;\r
-   assign  _net_89 = (r_bit32_cnt)==(5'b01010);\r
-   assign  _net_90 = fs_disp_data&_net_24;\r
-   assign  _net_91 = (fs_disp_data&_net_24)&_net_89;\r
-   assign  _net_92 = (r_bit32_cnt)==(5'b01001);\r
-   assign  _net_93 = fs_disp_data&_net_24;\r
-   assign  _net_94 = (fs_disp_data&_net_24)&_net_92;\r
-   assign  _net_95 = (r_bit32_cnt)==(5'b01000);\r
-   assign  _net_96 = fs_disp_data&_net_24;\r
-   assign  _net_97 = (fs_disp_data&_net_24)&_net_95;\r
-   assign  _net_98 = (r_bit32_cnt)==(5'b00111);\r
-   assign  _net_99 = fs_disp_data&_net_24;\r
-   assign  _net_100 = (fs_disp_data&_net_24)&_net_98;\r
-   assign  _net_101 = (r_bit32_cnt)==(5'b00110);\r
-   assign  _net_102 = fs_disp_data&_net_24;\r
-   assign  _net_103 = (fs_disp_data&_net_24)&_net_101;\r
-   assign  _net_104 = (r_bit32_cnt)==(5'b00101);\r
-   assign  _net_105 = fs_disp_data&_net_24;\r
-   assign  _net_106 = (fs_disp_data&_net_24)&_net_104;\r
-   assign  _net_107 = (r_bit32_cnt)==(5'b00100);\r
-   assign  _net_108 = fs_disp_data&_net_24;\r
-   assign  _net_109 = (fs_disp_data&_net_24)&_net_107;\r
-   assign  _net_110 = (r_bit32_cnt)==(5'b00011);\r
-   assign  _net_111 = fs_disp_data&_net_24;\r
-   assign  _net_112 = (fs_disp_data&_net_24)&_net_110;\r
-   assign  _net_113 = (r_bit32_cnt)==(5'b00010);\r
-   assign  _net_114 = fs_disp_data&_net_24;\r
-   assign  _net_115 = (fs_disp_data&_net_24)&_net_113;\r
-   assign  _net_116 = (r_bit32_cnt)==(5'b00001);\r
-   assign  _net_117 = fs_disp_data&_net_24;\r
-   assign  _net_118 = (fs_disp_data&_net_24)&_net_116;\r
-   assign  _net_119 = (r_bit32_cnt)==(5'b00000);\r
-   assign  _net_120 = fs_disp_data&_net_24;\r
-   assign  _net_121 = (fs_disp_data&_net_24)&_net_119;\r
-   assign  _net_122 = (r_bit32_cnt)==(5'b11111);\r
-   assign  _net_123 = fs_disp_data&(~_net_24);\r
-   assign  _net_124 = (fs_disp_data&(~_net_24))&_net_122;\r
-   assign  _net_125 = (fs_disp_data&(~_net_24))&_net_122;\r
-   assign  _net_126 = (r_bit32_cnt)==(5'b11110);\r
-   assign  _net_127 = fs_disp_data&(~_net_24);\r
-   assign  _net_128 = (fs_disp_data&(~_net_24))&_net_126;\r
-   assign  _net_129 = (r_bit32_cnt)==(5'b11101);\r
-   assign  _net_130 = fs_disp_data&(~_net_24);\r
-   assign  _net_131 = (fs_disp_data&(~_net_24))&_net_129;\r
-   assign  _net_132 = (r_bit32_cnt)==(5'b11100);\r
-   assign  _net_133 = fs_disp_data&(~_net_24);\r
-   assign  _net_134 = (fs_disp_data&(~_net_24))&_net_132;\r
-   assign  _net_135 = (r_bit32_cnt)==(5'b11011);\r
-   assign  _net_136 = fs_disp_data&(~_net_24);\r
-   assign  _net_137 = (fs_disp_data&(~_net_24))&_net_135;\r
-   assign  _net_138 = (r_bit32_cnt)==(5'b11010);\r
-   assign  _net_139 = fs_disp_data&(~_net_24);\r
-   assign  _net_140 = (fs_disp_data&(~_net_24))&_net_138;\r
-   assign  _net_141 = (r_bit32_cnt)==(5'b11001);\r
-   assign  _net_142 = fs_disp_data&(~_net_24);\r
-   assign  _net_143 = (fs_disp_data&(~_net_24))&_net_141;\r
-   assign  _net_144 = (r_bit32_cnt)==(5'b11000);\r
-   assign  _net_145 = fs_disp_data&(~_net_24);\r
-   assign  _net_146 = (fs_disp_data&(~_net_24))&_net_144;\r
-   assign  _net_147 = (r_bit32_cnt)==(5'b10111);\r
-   assign  _net_148 = fs_disp_data&(~_net_24);\r
-   assign  _net_149 = (fs_disp_data&(~_net_24))&_net_147;\r
-   assign  _net_150 = (r_bit32_cnt)==(5'b10110);\r
-   assign  _net_151 = fs_disp_data&(~_net_24);\r
-   assign  _net_152 = (fs_disp_data&(~_net_24))&_net_150;\r
-   assign  _net_153 = (r_bit32_cnt)==(5'b10101);\r
-   assign  _net_154 = fs_disp_data&(~_net_24);\r
-   assign  _net_155 = (fs_disp_data&(~_net_24))&_net_153;\r
-   assign  _net_156 = (r_bit32_cnt)==(5'b10100);\r
-   assign  _net_157 = fs_disp_data&(~_net_24);\r
-   assign  _net_158 = (fs_disp_data&(~_net_24))&_net_156;\r
-   assign  _net_159 = (r_bit32_cnt)==(5'b10011);\r
-   assign  _net_160 = fs_disp_data&(~_net_24);\r
-   assign  _net_161 = (fs_disp_data&(~_net_24))&_net_159;\r
-   assign  _net_162 = (r_bit32_cnt)==(5'b10010);\r
-   assign  _net_163 = fs_disp_data&(~_net_24);\r
-   assign  _net_164 = (fs_disp_data&(~_net_24))&_net_162;\r
-   assign  _net_165 = (r_bit32_cnt)==(5'b10001);\r
-   assign  _net_166 = fs_disp_data&(~_net_24);\r
-   assign  _net_167 = (fs_disp_data&(~_net_24))&_net_165;\r
-   assign  _net_168 = (r_bit32_cnt)==(5'b10000);\r
-   assign  _net_169 = fs_disp_data&(~_net_24);\r
-   assign  _net_170 = (fs_disp_data&(~_net_24))&_net_168;\r
-   assign  _net_171 = (r_bit32_cnt)==(5'b01111);\r
-   assign  _net_172 = fs_disp_data&(~_net_24);\r
-   assign  _net_173 = (fs_disp_data&(~_net_24))&_net_171;\r
-   assign  _net_174 = (r_bit32_cnt)==(5'b01110);\r
-   assign  _net_175 = fs_disp_data&(~_net_24);\r
-   assign  _net_176 = (fs_disp_data&(~_net_24))&_net_174;\r
-   assign  _net_177 = (r_bit32_cnt)==(5'b01101);\r
-   assign  _net_178 = fs_disp_data&(~_net_24);\r
-   assign  _net_179 = (fs_disp_data&(~_net_24))&_net_177;\r
-   assign  _net_180 = (r_bit32_cnt)==(5'b01100);\r
-   assign  _net_181 = fs_disp_data&(~_net_24);\r
-   assign  _net_182 = (fs_disp_data&(~_net_24))&_net_180;\r
-   assign  _net_183 = (r_bit32_cnt)==(5'b01011);\r
-   assign  _net_184 = fs_disp_data&(~_net_24);\r
-   assign  _net_185 = (fs_disp_data&(~_net_24))&_net_183;\r
-   assign  _net_186 = (r_bit32_cnt)==(5'b01010);\r
-   assign  _net_187 = fs_disp_data&(~_net_24);\r
-   assign  _net_188 = (fs_disp_data&(~_net_24))&_net_186;\r
-   assign  _net_189 = (r_bit32_cnt)==(5'b01001);\r
-   assign  _net_190 = fs_disp_data&(~_net_24);\r
-   assign  _net_191 = (fs_disp_data&(~_net_24))&_net_189;\r
-   assign  _net_192 = (r_bit32_cnt)==(5'b01000);\r
-   assign  _net_193 = fs_disp_data&(~_net_24);\r
-   assign  _net_194 = (fs_disp_data&(~_net_24))&_net_192;\r
-   assign  _net_195 = (r_bit32_cnt)==(5'b00111);\r
-   assign  _net_196 = fs_disp_data&(~_net_24);\r
-   assign  _net_197 = (fs_disp_data&(~_net_24))&_net_195;\r
-   assign  _net_198 = (r_bit32_cnt)==(5'b00110);\r
-   assign  _net_199 = fs_disp_data&(~_net_24);\r
-   assign  _net_200 = (fs_disp_data&(~_net_24))&_net_198;\r
-   assign  _net_201 = (r_bit32_cnt)==(5'b00101);\r
-   assign  _net_202 = fs_disp_data&(~_net_24);\r
-   assign  _net_203 = (fs_disp_data&(~_net_24))&_net_201;\r
-   assign  _net_204 = (r_bit32_cnt)==(5'b00100);\r
-   assign  _net_205 = fs_disp_data&(~_net_24);\r
-   assign  _net_206 = (fs_disp_data&(~_net_24))&_net_204;\r
-   assign  _net_207 = (r_bit32_cnt)==(5'b00011);\r
-   assign  _net_208 = fs_disp_data&(~_net_24);\r
-   assign  _net_209 = (fs_disp_data&(~_net_24))&_net_207;\r
-   assign  _net_210 = (r_bit32_cnt)==(5'b00010);\r
-   assign  _net_211 = fs_disp_data&(~_net_24);\r
-   assign  _net_212 = (fs_disp_data&(~_net_24))&_net_210;\r
-   assign  _net_213 = (r_bit32_cnt)==(5'b00001);\r
-   assign  _net_214 = fs_disp_data&(~_net_24);\r
-   assign  _net_215 = (fs_disp_data&(~_net_24))&_net_213;\r
-   assign  _net_216 = (r_bit32_cnt)==(5'b00000);\r
-   assign  _net_217 = fs_disp_data&(~_net_24);\r
-   assign  _net_218 = (fs_disp_data&(~_net_24))&_net_216;\r
-   assign  o_v_sync = r_v_sync;\r
-   assign  o_h_sync = r_h_sync;\r
-   assign  o_vga_red = w_red;\r
-   assign  o_vga_green = w_green;\r
-   assign  o_vga_blue = w_blue;\r
-   assign  o_h_cnt = r_h_cnt;\r
-   assign  fo_req_32dot = _net_13;\r
-always @(posedge m_clock or posedge p_reset)\r
-  begin\r
-if (p_reset)\r
-     r_v_sync <= 1'b0;\r
-else if ((_net_8|_net_5)) \r
-      r_v_sync <= ~r_v_sync;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
-  begin\r
-if (p_reset)\r
-     r_h_sync <= 1'b0;\r
-else if ((_net_3|_net_0)) \r
-      r_h_sync <= ~r_h_sync;\r
-end\r
-always @(posedge p_reset)\r
- begin\r
-if (p_reset)\r
-     r_h_flg <= 1'b0;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
-  begin\r
-if (p_reset)\r
-     r_vdata_flg <= 1'b0;\r
-else if ((_net_7)|(_net_6)) \r
-      r_vdata_flg <= ((_net_7) ?1'b1:1'b0)|\r
-    ((_net_6) ?1'b0:1'b0);\r
-\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
-  begin\r
-if (p_reset)\r
-     r_hdata_flg <= 1'b0;\r
-else if ((_net_2)|(_net_1)) \r
-      r_hdata_flg <= ((_net_2) ?1'b1:1'b0)|\r
-    ((_net_1) ?1'b0:1'b0);\r
-\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
-  begin\r
-if (p_reset)\r
-     r_h_cnt <= 10'b0000000000;\r
-else if ((_net_4|_net_3|_net_2|_net_1)|(_net_0)) \r
-      r_h_cnt <= ((_net_4|_net_3|_net_2|_net_1) ?(r_h_cnt)+(10'b0000000001):10'b0)|\r
-    ((_net_0) ?10'b0000000000:10'b0);\r
-\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
-  begin\r
-if (p_reset)\r
-     r_v_cnt <= 19'b0000000000000000000;\r
-else if ((_net_9|_net_8|_net_7|_net_6)|(_net_5)) \r
-      r_v_cnt <= ((_net_9|_net_8|_net_7|_net_6) ?(r_v_cnt)+(19'b0000000000000000001):19'b0)|\r
-    ((_net_5) ?19'b0000000000000000000:19'b0);\r
-\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
-  begin\r
-if (p_reset)\r
-     r_bit32_cnt <= 5'b00000;\r
-else if ((fs_disp_data)|(_net_16)|(_net_17|_net_15)) \r
-      r_bit32_cnt <= ((fs_disp_data) ?(r_bit32_cnt)+(5'b00001):5'b0)|\r
-    ((_net_16) ?(r_bit32_cnt)+(5'b00001):5'b0)|\r
-    ((_net_17|_net_15) ?5'b00000:5'b0);\r
-\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
-  begin\r
-if (p_reset)\r
-     r_flg <= 1'b0;\r
-else if ((_net_125|_net_28)) \r
-      r_flg <= ~r_flg;\r
-end\r
-always @(posedge p_reset)\r
- begin\r
-if (p_reset)\r
-     r_cnt <= 1'b0;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
-  begin\r
-if (p_reset)\r
-     r1 <= 32'b00000000000000000000000000000000;\r
-else if ((_net_22)) \r
-      r1 <= i_pix32_data;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
-  begin\r
-if (p_reset)\r
-     r2 <= 32'b00000000000000000000000000000000;\r
-else if ((_net_23)) \r
-      r2 <= i_pix32_data;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
-  begin\r
-if (p_reset)\r
-     r_data_select_flag <= 1'b0;\r
-else if ((fi_ack_req_32dot)) \r
-      r_data_select_flag <= ~r_data_select_flag;\r
-end\r
-endmodule\r
-/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Fri Jul 08 20:38:20 2011\r
- Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
-*/\r

diff --git a/VGADisplay/Verilog/vga_top.v b/VGADisplay/Verilog/vga_top.v
index 0addb68..9a1b10e 100644 (file)
--- a/VGADisplay/Verilog/vga_top.v
+++ b/VGADisplay/Verilog/vga_top.v
@@ -1,9 +1,16 @@
 /*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Fri Jul 08 20:39:37 2011\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Mon Jul 11 14:01:02 2011\r
  Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:\r
 */\r
 \r
-module vga_generate ( p_reset , m_clock , i_pix32_data , o_v_sync , o_h_sync , o_vga_red , o_vga_green , o_vga_blue , o_h_cnt , fi_ack_req_32dot , fo_req_32dot );\r
+module vga_generate ( i_50clk , i_we1 , i_wadrs1 , i_wdata1 , i_we2 , i_wadrs2 , i_wdata2 , p_reset , m_clock , i_pix32_data , o_v_sync , o_h_sync , o_vga_red , o_vga_green , o_vga_blue , o_h_cnt , fi_ack_req_32dot , fo_req_32dot );\r
+  input i_50clk;\r
+  input i_we1;\r
+  input [4:0] i_wadrs1;\r
+  input [31:0] i_wdata1;\r
+  input i_we2;\r
+  input [4:0] i_wadrs2;\r
+  input [31:0] i_wdata2;\r
   input p_reset;\r
   input m_clock;\r
   input [31:0] i_pix32_data;\r
@@ -16,6 +23,7 @@ module vga_generate ( p_reset , m_clock , i_pix32_data , o_v_sync , o_h_sync , o
   input fi_ack_req_32dot;\r
   output fo_req_32dot;\r
   wire fs_disp_data;\r
+  reg r_line_buff_cnt;\r
   reg r_v_sync;\r
   reg r_h_sync;\r
   reg r_h_flg;\r
@@ -33,6 +41,19 @@ module vga_generate ( p_reset , m_clock , i_pix32_data , o_v_sync , o_h_sync , o
   wire [3:0] w_green;\r
   wire [3:0] w_blue;\r
   wire w_disp_data;\r
+  wire _u_FIFO_p_reset;\r
+  wire _u_FIFO_m_clock;\r
+  wire _u_FIFO_i_we1;\r
+  wire [6:0] _u_FIFO_i_wadrs1;\r
+  wire [7:0] _u_FIFO_i_wdata1;\r
+  wire _u_FIFO_i_we2;\r
+  wire [6:0] _u_FIFO_i_wadrs2;\r
+  wire [7:0] _u_FIFO_i_wdata2;\r
+  wire [6:0] _u_FIFO_i_radrs1;\r
+  wire [7:0] _u_FIFO_o_rdasrs1;\r
+  wire [6:0] _u_FIFO_i_radrs2;\r
+  wire [7:0] _u_FIFO_o_rdasrs2;\r
+  wire _u_FIFO_i_clock;\r
   wire _net_0;\r
   wire _net_1;\r
   wire _net_2;\r
@@ -252,6 +273,7 @@ module vga_generate ( p_reset , m_clock , i_pix32_data , o_v_sync , o_h_sync , o
   wire _net_216;\r
   wire _net_217;\r
   wire _net_218;\r
+FIFO u_FIFO (.i_clock(_u_FIFO_i_clock), .o_rdasrs2(_u_FIFO_o_rdasrs2), .i_radrs2(_u_FIFO_i_radrs2), .o_rdasrs1(_u_FIFO_o_rdasrs1), .i_radrs1(_u_FIFO_i_radrs1), .i_wdata2(_u_FIFO_i_wdata2), .i_wadrs2(_u_FIFO_i_wadrs2), .i_we2(_u_FIFO_i_we2), .i_wdata1(_u_FIFO_i_wdata1), .i_wadrs1(_u_FIFO_i_wadrs1), .i_we1(_u_FIFO_i_we1), .m_clock(_u_FIFO_m_clock), .p_reset(_u_FIFO_p_reset));\r
 \r
    assign  fs_disp_data = _net_10;\r
    assign  w_red = 4'b0000;\r
@@ -548,6 +570,11 @@ module vga_generate ( p_reset , m_clock , i_pix32_data , o_v_sync , o_h_sync , o
    assign  o_vga_blue = w_blue;\r
    assign  o_h_cnt = r_h_cnt;\r
    assign  fo_req_32dot = _net_13;\r
+always @(posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+     r_line_buff_cnt <= 1'b0;\r
+end\r
 always @(posedge m_clock or posedge p_reset)\r
   begin\r
 if (p_reset)\r
@@ -648,6 +675,6 @@ else if ((fi_ack_req_32dot))
 end\r
 endmodule\r
 /*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Fri Jul 08 20:39:41 2011\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Mon Jul 11 14:01:06 2011\r
  Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
 */\r

diff --git a/VGADisplay/src/vga_generate.nsh b/VGADisplay/src/vga_generate.nsh
index f903d83..59fa65b 100644 (file)
--- a/VGADisplay/src/vga_generate.nsh
+++ b/VGADisplay/src/vga_generate.nsh
@@ -1,4 +1,12 @@
 declare vga_generate interface {
+       input  i_50clk ;
+       input  i_we1 ;
+       input  i_wadrs1[5] ;
+       input  i_wdata1[32] ;
+       input  i_we2 ;
+       input  i_wadrs2[5] ;
+       input  i_wdata2[32] ;
+
        input  p_reset ;
        input  m_clock ;
        input  i_pix32_data[32] ;

diff --git a/VGADisplay/src/vga_generate.nsl b/VGADisplay/src/vga_generate.nsl
index 3f17a66..852eaf4 100644 (file)
--- a/VGADisplay/src/vga_generate.nsl
+++ b/VGADisplay/src/vga_generate.nsl
@@ -1,6 +1,6 @@
-//%d CNT_H_00                  0b0000000000
+//%d CNT_H_00          0b0000000000
 //%d CNT_H1                    0b0001011111 /* 96clock */
-//%d CNT_H_REP32               0b0001101110 /* 110 clock */
+//%d CNT_H_REP32       0b0001101110 /* 110 clock */
 //%d CNT_H_DATA_IN     0b0010001110 /* 142 for 144clock */
 //%d CNT_H_DATA_OUT    0b1100001110 /* 782 for 784clock */
 //%d CNT_H2                    0b1100011111 /* 800clock */
@@ -14,6 +14,8 @@
 //%d CNT_V_DATA_OUT    0b1100011110011011111 /* 408800clock */ 
 //%d CNT_V2                    0b1100101110000011111 /* 416800clock */
 
+#include "vga_ram.nsh"
+
 /**
 *      VGA\81@Signal Generate Circuit
 *      Module name is "vga_generate"
@@ -43,6 +45,15 @@
 
 
 declare vga_generate  interface {
+       // FIFO\81@interface
+       input  i_50clk ;
+       input  i_we1 ;
+       input  i_wadrs1[5] ;
+       input  i_wdata1[32] ;
+       input  i_we2 ;
+       input  i_wadrs2[5] ;
+       input  i_wdata2[32] ;
+
        input  p_reset ;
        input  m_clock ;
        input  i_pix32_data[32] ;
@@ -55,11 +66,15 @@ declare vga_generate  interface {
 
        func_in  fi_ack_req_32dot(i_pix32_data) ;
        func_out fo_req_32dot ;
+       
+       func_in vgaram_write1() ;
+       func_in vgaram_write2() ;
 }
-
 module vga_generate {
        func_self fs_disp_data ;
 
+       reg r_line_buff_cnt = 0 ;
+
        reg r_v_sync = 0 ;
        reg r_h_sync = 0 ;
        reg r_h_flg = 0 ;
@@ -81,16 +96,48 @@ module vga_generate {
        wire w_green[4] ;
        wire w_blue[4] ;
        wire w_disp_data;
+       
+       reg r_rptr1[5] = 0 ;
+       reg r_rptr2[5] = 0 ;
+       reg r_wptr1[5] = 0 ;
+       reg r_wptr2[5] = 0 ;
+       reg r_cnt_hsync[10] = 0 ;
+       reg r_cnt_flg = 0 ;
+       reg r_hld_h_sync = 0 ;
+
+       func_self vgaram_read1() ;
+       func_self vgaram_read2() ;
+
+       func_self vgaram_reset1() ;
+       func_self vgaram_reset2() ;
+
+       vga_ram u_VGARAM ;
 
        {
-               o_v_sync        = r_v_sync;
-               o_h_sync        = r_h_sync;
-               o_vga_red       = w_red;
-               o_vga_green     = w_green;
-               o_vga_blue  = w_blue;
-               o_h_cnt         = r_h_cnt;
+               o_v_sync        = r_v_sync ;
+               o_h_sync        = r_h_sync ;
+               o_vga_red       = w_red ;
+               o_vga_green     = w_green ;
+               o_vga_blue  = w_blue ;
+               o_h_cnt         = r_h_cnt ;
 
 
+               /* y point counter */
+               r_h_sync := r_hld_h_sync ;
+
+               if( r_v_sync ) {
+                       if(r_h_sync & ~r_hld_h_sync) {
+                               if(~r_cnt_flg) {
+                                       r_cnt_flg := 1 ;
+                               } else {
+                                       r_cnt_hsync++ ;
+                               }
+                       }
+               } else {
+                       r_cnt_flg := 0 ;
+                       r_cnt_hsync := 0 ;
+               }
+
                //horizonal synchronous signal generate
                any{
                        r_h_cnt == 10'd96 : {
@@ -270,5 +317,5 @@ module vga_generate {
                        }
                }
                r_bit32_cnt++ ;
-       }//disp_data
-}//module end
+       } //disp_data
+} //module end
\ No newline at end of file

diff --git a/VGADisplay/src/FIFO.nsh b/VGADisplay/src/vga_ram.nsh
similarity index 90%
rename from VGADisplay/src/FIFO.nsh
rename to VGADisplay/src/vga_ram.nsh
index c571607..5394cde 100644 (file)
--- a/VGADisplay/src/FIFO.nsh
+++ b/VGADisplay/src/vga_ram.nsh
@@ -1,4 +1,4 @@
-declare FIFO interface {
+declare vga_ram interface {
        input p_reset ;
        input m_clock ;
        

diff --git a/VGADisplay/src/FIFO.v b/VGADisplay/src/vga_ram.v
similarity index 54%
rename from VGADisplay/src/FIFO.v
rename to VGADisplay/src/vga_ram.v
index 24c6cbf..c82156f 100644 (file)
--- a/VGADisplay/src/FIFO.v
+++ b/VGADisplay/src/vga_ram.v
@@ -1,4 +1,4 @@
-module FIFO (\r
+module vga_ram (\r
        p_reset, m_clock, i_we1,\r
        i_wadrs1, i_wdata1, i_we2,\r
        i_wadrs2, i_wdata2, i_radrs1,\r
@@ -10,25 +10,25 @@ module FIFO (
        input m_clock ;\r
        \r
        input i_we1 ;\r
-       input [6:0] i_wadrs1 ;\r
-       input [7:0] i_wdata1 ;\r
+       input [4:0] i_wadrs1 ;\r
+       input [31:0] i_wdata1 ;\r
 \r
        input i_clock ;\r
        input i_we2 ;\r
-       input [6:0] i_wadrs2 ;\r
-       input [7:0] i_wdata2 ;\r
+       input [4:0] i_wadrs2 ;\r
+       input [31:0] i_wdata2 ;\r
        \r
-       input  [6:0] i_radrs1 ;\r
-       output [7:0] o_rdasrs1 ;\r
+       input  [4:0] i_radrs1 ;\r
+       output [31:0] o_rdasrs1 ;\r
 \r
-       input  [6:0] i_radrs2 ;\r
-       output [7:0] o_rdasrs2 ;\r
+       input  [4:0] i_radrs2 ;\r
+       output [31:0] o_rdasrs2 ;\r
 \r
-       reg [6:0] r_rdadrs1 ;\r
-       reg [6:0] r_rdadrs2 ;\r
+       reg [4:0] r_rdadrs1 ;\r
+       reg [4:0] r_rdadrs2 ;\r
        \r
-       (* remstyle = "no_rw_check" *) reg [7:0] mem1[127:0] ;\r
-       (* remstyle = "no_rw_check" *) reg [7:0] mem2[127:0] ;\r
+       (* remstyle = "no_rw_check" *) reg [31:0] mem1[31:0] ;\r
+       (* remstyle = "no_rw_check" *) reg [31:0] mem2[31:0] ;\r
        \r
        // memory write command\r
        always @ (posedge m_clock) begin\r

diff --git a/VGADisplay/src/vga_top.nsl b/VGADisplay/src/vga_top.nsl
index efc2f98..df9c723 100644 (file)
--- a/VGADisplay/src/vga_top.nsl
+++ b/VGADisplay/src/vga_top.nsl
@@ -16,7 +16,9 @@
 //#define ONE_SEC 25'd100\r
 \r
 \r
-declare vga_top {\r
+declare vga_top interface {\r
+       input  p_reset ;\r
+       input  m_clock ;\r
        output o_v_sync ;\r
        output o_h_sync ;\r
        output o_red[4] ;\r
@@ -43,13 +45,12 @@ module vga_top {
 \r
        vga_generate u_VGA ;\r
        exp_ctrl         u_EXP ;\r
-       FIFO             u_FIFO ;\r
        \r
-//     o_v_sync        = u_VGA.o_v_sync ;\r
-//     o_h_sync        = u_VGA.o_h_sync ;\r
-//     o_red           = u_VGA.o_vga_red ;\r
-//     o_green         = u_VGA.o_vga_green ;\r
-//     o_blue          = u_VGA.o_vga_blue ;\r
+       o_v_sync        = u_VGA.o_v_sync ;\r
+       o_h_sync        = u_VGA.o_h_sync ;\r
+       o_red           = u_VGA.o_vga_red ;\r
+       o_green         = u_VGA.o_vga_green ;\r
+       o_blue          = u_VGA.o_vga_blue ;\r
 \r
        if( u_VGA.fo_req_32dot ) {\r
                u_VGA.fi_ack_req_32dot( 32'hFFFFFFFF ) ;\r