amdgpu/amdgpu_gpu_info.c

   1 /*
   2  * Copyright © 2014 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <errno.h>
  25 #include <string.h>
  26
  27 #include "amdgpu.h"
  28 #include "amdgpu_drm.h"
  29 #include "amdgpu_internal.h"
  30 #include "xf86drm.h"
  31
  32 int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id,
  33                       unsigned size, void *value)
  34 {
  35         struct drm_amdgpu_info request;
  36
  37         memset(&request, 0, sizeof(request));
  38         request.return_pointer = (uintptr_t)value;
  39         request.return_size = size;
  40         request.query = info_id;
  41
  42         return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
  43                                sizeof(struct drm_amdgpu_info));
  44 }
  45
  46 int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id,
  47                               int32_t *result)
  48 {
  49         struct drm_amdgpu_info request;
  50
  51         memset(&request, 0, sizeof(request));
  52         request.return_pointer = (uintptr_t)result;
  53         request.return_size = sizeof(*result);
  54         request.query = AMDGPU_INFO_CRTC_FROM_ID;
  55         request.mode_crtc.id = id;
  56
  57         return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
  58                                sizeof(struct drm_amdgpu_info));
  59 }
  60
  61 int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset,
  62                              unsigned count, uint32_t instance, uint32_t flags,
  63                              uint32_t *values)
  64 {
  65         struct drm_amdgpu_info request;
  66
  67         memset(&request, 0, sizeof(request));
  68         request.return_pointer = (uintptr_t)values;
  69         request.return_size = count * sizeof(uint32_t);
  70         request.query = AMDGPU_INFO_READ_MMR_REG;
  71         request.read_mmr_reg.dword_offset = dword_offset;
  72         request.read_mmr_reg.count = count;
  73         request.read_mmr_reg.instance = instance;
  74         request.read_mmr_reg.flags = flags;
  75
  76         return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
  77                                sizeof(struct drm_amdgpu_info));
  78 }
  79
  80 int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, unsigned type,
  81                              uint32_t *count)
  82 {
  83         struct drm_amdgpu_info request;
  84
  85         memset(&request, 0, sizeof(request));
  86         request.return_pointer = (uintptr_t)count;
  87         request.return_size = sizeof(*count);
  88         request.query = AMDGPU_INFO_HW_IP_COUNT;
  89         request.query_hw_ip.type = type;
  90
  91         return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
  92                                sizeof(struct drm_amdgpu_info));
  93 }
  94
  95 int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type,
  96                             unsigned ip_instance,
  97                             struct drm_amdgpu_info_hw_ip *info)
  98 {
  99         struct drm_amdgpu_info request;
 100
 101         memset(&request, 0, sizeof(request));
 102         request.return_pointer = (uintptr_t)info;
 103         request.return_size = sizeof(*info);
 104         request.query = AMDGPU_INFO_HW_IP_INFO;
 105         request.query_hw_ip.type = type;
 106         request.query_hw_ip.ip_instance = ip_instance;
 107
 108         return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
 109                                sizeof(struct drm_amdgpu_info));
 110 }
 111
 112 int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type,
 113                                   unsigned ip_instance, unsigned index,
 114                                   uint32_t *version, uint32_t *feature)
 115 {
 116         struct drm_amdgpu_info request;
 117         struct drm_amdgpu_info_firmware firmware;
 118         int r;
 119
 120         memset(&request, 0, sizeof(request));
 121         request.return_pointer = (uintptr_t)&firmware;
 122         request.return_size = sizeof(firmware);
 123         request.query = AMDGPU_INFO_FW_VERSION;
 124         request.query_fw.fw_type = fw_type;
 125         request.query_fw.ip_instance = ip_instance;
 126         request.query_fw.index = index;
 127
 128         r = drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
 129                             sizeof(struct drm_amdgpu_info));
 130         if (r)
 131                 return r;
 132
 133         *version = firmware.ver;
 134         *feature = firmware.feature;
 135         return 0;
 136 }
 137
 138 int amdgpu_query_gpu_info_init(amdgpu_device_handle dev)
 139 {
 140         int r, i;
 141
 142         r = amdgpu_query_info(dev, AMDGPU_INFO_DEV_INFO, sizeof(dev->dev_info),
 143                               &dev->dev_info);
 144         if (r)
 145                 return r;
 146
 147         dev->info.asic_id = dev->dev_info.device_id;
 148         dev->info.chip_rev = dev->dev_info.chip_rev;
 149         dev->info.chip_external_rev = dev->dev_info.external_rev;
 150         dev->info.family_id = dev->dev_info.family;
 151         dev->info.max_engine_clk = dev->dev_info.max_engine_clock;
 152         dev->info.max_memory_clk = dev->dev_info.max_memory_clock;
 153         dev->info.gpu_counter_freq = dev->dev_info.gpu_counter_freq;
 154         dev->info.enabled_rb_pipes_mask = dev->dev_info.enabled_rb_pipes_mask;
 155         dev->info.rb_pipes = dev->dev_info.num_rb_pipes;
 156         dev->info.ids_flags = dev->dev_info.ids_flags;
 157         dev->info.num_hw_gfx_contexts = dev->dev_info.num_hw_gfx_contexts;
 158         dev->info.num_shader_engines = dev->dev_info.num_shader_engines;
 159         dev->info.num_shader_arrays_per_engine =
 160                 dev->dev_info.num_shader_arrays_per_engine;
 161         dev->info.vram_type = dev->dev_info.vram_type;
 162         dev->info.vram_bit_width = dev->dev_info.vram_bit_width;
 163
 164         for (i = 0; i < (int)dev->info.num_shader_engines; i++) {
 165                 unsigned instance = (i << AMDGPU_INFO_MMR_SE_INDEX_SHIFT) |
 166                                     (AMDGPU_INFO_MMR_SH_INDEX_MASK <<
 167                                      AMDGPU_INFO_MMR_SH_INDEX_SHIFT);
 168
 169                 r = amdgpu_read_mm_registers(dev, 0x263d, 1, instance, 0,
 170                                              &dev->info.backend_disable[i]);
 171                 if (r)
 172                         return r;
 173                 /* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */
 174                 dev->info.backend_disable[i] =
 175                         (dev->info.backend_disable[i] >> 16) & 0xff;
 176
 177                 r = amdgpu_read_mm_registers(dev, 0xa0d4, 1, instance, 0,
 178                                              &dev->info.pa_sc_raster_cfg[i]);
 179                 if (r)
 180                         return r;
 181
 182                 r = amdgpu_read_mm_registers(dev, 0xa0d5, 1, instance, 0,
 183                                              &dev->info.pa_sc_raster_cfg1[i]);
 184                 if (r)
 185                         return r;
 186         }
 187
 188         r = amdgpu_read_mm_registers(dev, 0x2644, 32, 0xffffffff, 0,
 189                                      dev->info.gb_tile_mode);
 190         if (r)
 191                 return r;
 192
 193         r = amdgpu_read_mm_registers(dev, 0x2664, 16, 0xffffffff, 0,
 194                                      dev->info.gb_macro_tile_mode);
 195         if (r)
 196                 return r;
 197
 198         r = amdgpu_read_mm_registers(dev, 0x263e, 1, 0xffffffff, 0,
 199                                      &dev->info.gb_addr_cfg);
 200         if (r)
 201                 return r;
 202
 203         r = amdgpu_read_mm_registers(dev, 0x9d8, 1, 0xffffffff, 0,
 204                                      &dev->info.mc_arb_ramcfg);
 205         if (r)
 206                 return r;
 207
 208         dev->info.cu_active_number = dev->dev_info.cu_active_number;
 209         dev->info.cu_ao_mask = dev->dev_info.cu_ao_mask;
 210         memcpy(&dev->info.cu_bitmap[0][0], &dev->dev_info.cu_bitmap[0][0], sizeof(dev->info.cu_bitmap));
 211
 212         /* TODO: info->max_quad_shader_pipes is not set */
 213         /* TODO: info->avail_quad_shader_pipes is not set */
 214         /* TODO: info->cache_entries_per_quad_pipe is not set */
 215         return 0;
 216 }
 217
 218 int amdgpu_query_gpu_info(amdgpu_device_handle dev,
 219                         struct amdgpu_gpu_info *info)
 220 {
 221         /* Get ASIC info*/
 222         *info = dev->info;
 223
 224         return 0;
 225 }
 226
 227 int amdgpu_query_heap_info(amdgpu_device_handle dev,
 228                         uint32_t heap,
 229                         uint32_t flags,
 230                         struct amdgpu_heap_info *info)
 231 {
 232         struct drm_amdgpu_info_vram_gtt vram_gtt_info;
 233         int r;
 234
 235         r = amdgpu_query_info(dev, AMDGPU_INFO_VRAM_GTT,
 236                               sizeof(vram_gtt_info), &vram_gtt_info);
 237         if (r)
 238                 return r;
 239
 240         /* Get heap information */
 241         switch (heap) {
 242         case AMDGPU_GEM_DOMAIN_VRAM:
 243                 /* query visible only vram heap */
 244                 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
 245                         info->heap_size = vram_gtt_info.vram_cpu_accessible_size;
 246                 else /* query total vram heap */
 247                         info->heap_size = vram_gtt_info.vram_size;
 248
 249                 info->max_allocation = vram_gtt_info.vram_cpu_accessible_size;
 250
 251                 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
 252                         r = amdgpu_query_info(dev, AMDGPU_INFO_VIS_VRAM_USAGE,
 253                                               sizeof(info->heap_usage),
 254                                               &info->heap_usage);
 255                 else
 256                         r = amdgpu_query_info(dev, AMDGPU_INFO_VRAM_USAGE,
 257                                               sizeof(info->heap_usage),
 258                                               &info->heap_usage);
 259                 if (r)
 260                         return r;
 261                 break;
 262         case AMDGPU_GEM_DOMAIN_GTT:
 263                 info->heap_size = vram_gtt_info.gtt_size;
 264                 info->max_allocation = vram_gtt_info.vram_cpu_accessible_size;
 265
 266                 r = amdgpu_query_info(dev, AMDGPU_INFO_GTT_USAGE,
 267                                       sizeof(info->heap_usage),
 268                                       &info->heap_usage);
 269                 if (r)
 270                         return r;
 271                 break;
 272         default:
 273                 return -EINVAL;
 274         }
 275
 276         return 0;
 277 }