arch/arm/boot/dts/tegra30.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra30-car.h>
   3 #include <dt-bindings/gpio/tegra-gpio.h>
   4 #include <dt-bindings/memory/tegra30-mc.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7
   8 #include "skeleton.dtsi"
   9
  10 / {
  11         compatible = "nvidia,tegra30";
  12         interrupt-parent = <&lic>;
  13
  14         pcie@3000 {
  15                 compatible = "nvidia,tegra30-pcie";
  16                 device_type = "pci";
  17                 reg = <0x00003000 0x00000800   /* PADS registers */
  18                        0x00003800 0x00000200   /* AFI registers */
  19                        0x10000000 0x10000000>; /* configuration space */
  20                 reg-names = "pads", "afi", "cs";
  21                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
  22                               GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  23                 interrupt-names = "intr", "msi";
  24
  25                 #interrupt-cells = <1>;
  26                 interrupt-map-mask = <0 0 0 0>;
  27                 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  28
  29                 bus-range = <0x00 0xff>;
  30                 #address-cells = <3>;
  31                 #size-cells = <2>;
  32
  33                 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000   /* port 0 configuration space */
  34                           0x82000000 0 0x00001000 0x00001000 0 0x00001000   /* port 1 configuration space */
  35                           0x82000000 0 0x00004000 0x00004000 0 0x00001000   /* port 2 configuration space */
  36                           0x81000000 0 0          0x02000000 0 0x00010000   /* downstream I/O */
  37                           0x82000000 0 0x20000000 0x20000000 0 0x08000000   /* non-prefetchable memory */
  38                           0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
  39
  40                 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
  41                          <&tegra_car TEGRA30_CLK_AFI>,
  42                          <&tegra_car TEGRA30_CLK_PLL_E>,
  43                          <&tegra_car TEGRA30_CLK_CML0>;
  44                 clock-names = "pex", "afi", "pll_e", "cml";
  45                 resets = <&tegra_car 70>,
  46                          <&tegra_car 72>,
  47                          <&tegra_car 74>;
  48                 reset-names = "pex", "afi", "pcie_x";
  49                 status = "disabled";
  50
  51                 pci@1,0 {
  52                         device_type = "pci";
  53                         assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
  54                         reg = <0x000800 0 0 0 0>;
  55                         bus-range = <0x00 0xff>;
  56                         status = "disabled";
  57
  58                         #address-cells = <3>;
  59                         #size-cells = <2>;
  60                         ranges;
  61
  62                         nvidia,num-lanes = <2>;
  63                 };
  64
  65                 pci@2,0 {
  66                         device_type = "pci";
  67                         assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
  68                         reg = <0x001000 0 0 0 0>;
  69                         bus-range = <0x00 0xff>;
  70                         status = "disabled";
  71
  72                         #address-cells = <3>;
  73                         #size-cells = <2>;
  74                         ranges;
  75
  76                         nvidia,num-lanes = <2>;
  77                 };
  78
  79                 pci@3,0 {
  80                         device_type = "pci";
  81                         assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
  82                         reg = <0x001800 0 0 0 0>;
  83                         bus-range = <0x00 0xff>;
  84                         status = "disabled";
  85
  86                         #address-cells = <3>;
  87                         #size-cells = <2>;
  88                         ranges;
  89
  90                         nvidia,num-lanes = <2>;
  91                 };
  92         };
  93
  94         iram@40000000 {
  95                 compatible = "mmio-sram";
  96                 reg = <0x40000000 0x40000>;
  97                 #address-cells = <1>;
  98                 #size-cells = <1>;
  99                 ranges = <0 0x40000000 0x40000>;
 100
 101                 vde_pool: vde@400 {
 102                         reg = <0x400 0x3fc00>;
 103                         pool;
 104                 };
 105         };
 106
 107         host1x@50000000 {
 108                 compatible = "nvidia,tegra30-host1x", "simple-bus";
 109                 reg = <0x50000000 0x00024000>;
 110                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
 111                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
 112                 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
 113                 resets = <&tegra_car 28>;
 114                 reset-names = "host1x";
 115                 iommus = <&mc TEGRA_SWGROUP_HC>;
 116
 117                 #address-cells = <1>;
 118                 #size-cells = <1>;
 119
 120                 ranges = <0x54000000 0x54000000 0x04000000>;
 121
 122                 mpe@54040000 {
 123                         compatible = "nvidia,tegra30-mpe";
 124                         reg = <0x54040000 0x00040000>;
 125                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 126                         clocks = <&tegra_car TEGRA30_CLK_MPE>;
 127                         resets = <&tegra_car 60>;
 128                         reset-names = "mpe";
 129
 130                         iommus = <&mc TEGRA_SWGROUP_MPE>;
 131                 };
 132
 133                 vi@54080000 {
 134                         compatible = "nvidia,tegra30-vi";
 135                         reg = <0x54080000 0x00040000>;
 136                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 137                         clocks = <&tegra_car TEGRA30_CLK_VI>;
 138                         resets = <&tegra_car 20>;
 139                         reset-names = "vi";
 140
 141                         iommus = <&mc TEGRA_SWGROUP_VI>;
 142                 };
 143
 144                 epp@540c0000 {
 145                         compatible = "nvidia,tegra30-epp";
 146                         reg = <0x540c0000 0x00040000>;
 147                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 148                         clocks = <&tegra_car TEGRA30_CLK_EPP>;
 149                         resets = <&tegra_car 19>;
 150                         reset-names = "epp";
 151
 152                         iommus = <&mc TEGRA_SWGROUP_EPP>;
 153                 };
 154
 155                 isp@54100000 {
 156                         compatible = "nvidia,tegra30-isp";
 157                         reg = <0x54100000 0x00040000>;
 158                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 159                         clocks = <&tegra_car TEGRA30_CLK_ISP>;
 160                         resets = <&tegra_car 23>;
 161                         reset-names = "isp";
 162
 163                         iommus = <&mc TEGRA_SWGROUP_ISP>;
 164                 };
 165
 166                 gr2d@54140000 {
 167                         compatible = "nvidia,tegra30-gr2d";
 168                         reg = <0x54140000 0x00040000>;
 169                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 170                         clocks = <&tegra_car TEGRA30_CLK_GR2D>;
 171                         resets = <&tegra_car 21>;
 172                         reset-names = "2d";
 173
 174                         iommus = <&mc TEGRA_SWGROUP_G2>;
 175                 };
 176
 177                 gr3d@54180000 {
 178                         compatible = "nvidia,tegra30-gr3d";
 179                         reg = <0x54180000 0x00040000>;
 180                         clocks = <&tegra_car TEGRA30_CLK_GR3D
 181                                   &tegra_car TEGRA30_CLK_GR3D2>;
 182                         clock-names = "3d", "3d2";
 183                         resets = <&tegra_car 24>,
 184                                  <&tegra_car 98>;
 185                         reset-names = "3d", "3d2";
 186
 187                         iommus = <&mc TEGRA_SWGROUP_NV>,
 188                                  <&mc TEGRA_SWGROUP_NV2>;
 189                 };
 190
 191                 dc@54200000 {
 192                         compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
 193                         reg = <0x54200000 0x00040000>;
 194                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 195                         clocks = <&tegra_car TEGRA30_CLK_DISP1>,
 196                                  <&tegra_car TEGRA30_CLK_PLL_P>;
 197                         clock-names = "dc", "parent";
 198                         resets = <&tegra_car 27>;
 199                         reset-names = "dc";
 200
 201                         iommus = <&mc TEGRA_SWGROUP_DC>;
 202
 203                         nvidia,head = <0>;
 204
 205                         rgb {
 206                                 status = "disabled";
 207                         };
 208                 };
 209
 210                 dc@54240000 {
 211                         compatible = "nvidia,tegra30-dc";
 212                         reg = <0x54240000 0x00040000>;
 213                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 214                         clocks = <&tegra_car TEGRA30_CLK_DISP2>,
 215                                  <&tegra_car TEGRA30_CLK_PLL_P>;
 216                         clock-names = "dc", "parent";
 217                         resets = <&tegra_car 26>;
 218                         reset-names = "dc";
 219
 220                         iommus = <&mc TEGRA_SWGROUP_DCB>;
 221
 222                         nvidia,head = <1>;
 223
 224                         rgb {
 225                                 status = "disabled";
 226                         };
 227                 };
 228
 229                 hdmi@54280000 {
 230                         compatible = "nvidia,tegra30-hdmi";
 231                         reg = <0x54280000 0x00040000>;
 232                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 233                         clocks = <&tegra_car TEGRA30_CLK_HDMI>,
 234                                  <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
 235                         clock-names = "hdmi", "parent";
 236                         resets = <&tegra_car 51>;
 237                         reset-names = "hdmi";
 238                         status = "disabled";
 239                 };
 240
 241                 tvo@542c0000 {
 242                         compatible = "nvidia,tegra30-tvo";
 243                         reg = <0x542c0000 0x00040000>;
 244                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 245                         clocks = <&tegra_car TEGRA30_CLK_TVO>;
 246                         status = "disabled";
 247                 };
 248
 249                 dsi@54300000 {
 250                         compatible = "nvidia,tegra30-dsi";
 251                         reg = <0x54300000 0x00040000>;
 252                         clocks = <&tegra_car TEGRA30_CLK_DSIA>;
 253                         resets = <&tegra_car 48>;
 254                         reset-names = "dsi";
 255                         status = "disabled";
 256                 };
 257         };
 258
 259         timer@50040600 {
 260                 compatible = "arm,cortex-a9-twd-timer";
 261                 reg = <0x50040600 0x20>;
 262                 interrupt-parent = <&intc>;
 263                 interrupts = <GIC_PPI 13
 264                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 265                 clocks = <&tegra_car TEGRA30_CLK_TWD>;
 266         };
 267
 268         intc: interrupt-controller@50041000 {
 269                 compatible = "arm,cortex-a9-gic";
 270                 reg = <0x50041000 0x1000
 271                        0x50040100 0x0100>;
 272                 interrupt-controller;
 273                 #interrupt-cells = <3>;
 274                 interrupt-parent = <&intc>;
 275         };
 276
 277         cache-controller@50043000 {
 278                 compatible = "arm,pl310-cache";
 279                 reg = <0x50043000 0x1000>;
 280                 arm,data-latency = <6 6 2>;
 281                 arm,tag-latency = <5 5 2>;
 282                 cache-unified;
 283                 cache-level = <2>;
 284         };
 285
 286         lic: interrupt-controller@60004000 {
 287                 compatible = "nvidia,tegra30-ictlr";
 288                 reg = <0x60004000 0x100>,
 289                       <0x60004100 0x50>,
 290                       <0x60004200 0x50>,
 291                       <0x60004300 0x50>,
 292                       <0x60004400 0x50>;
 293                 interrupt-controller;
 294                 #interrupt-cells = <3>;
 295                 interrupt-parent = <&intc>;
 296         };
 297
 298         timer@60005000 {
 299                 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 300                 reg = <0x60005000 0x400>;
 301                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 302                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 303                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 304                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 305                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 306                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 307                 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
 308         };
 309
 310         tegra_car: clock@60006000 {
 311                 compatible = "nvidia,tegra30-car";
 312                 reg = <0x60006000 0x1000>;
 313                 #clock-cells = <1>;
 314                 #reset-cells = <1>;
 315         };
 316
 317         flow-controller@60007000 {
 318                 compatible = "nvidia,tegra30-flowctrl";
 319                 reg = <0x60007000 0x1000>;
 320         };
 321
 322         apbdma: dma@6000a000 {
 323                 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
 324                 reg = <0x6000a000 0x1400>;
 325                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 326                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 327                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 328                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 329                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 330                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 331                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 332                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 333                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 334                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 335                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 336                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 337                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 338                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 339                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 340                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 341                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 342                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 343                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 344                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 345                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 346                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 347                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 348                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 349                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 350                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 351                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 352                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 353                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 354                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 355                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 356                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 357                 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
 358                 resets = <&tegra_car 34>;
 359                 reset-names = "dma";
 360                 #dma-cells = <1>;
 361         };
 362
 363         ahb: ahb@6000c000 {
 364                 compatible = "nvidia,tegra30-ahb";
 365                 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
 366         };
 367
 368         gpio: gpio@6000d000 {
 369                 compatible = "nvidia,tegra30-gpio";
 370                 reg = <0x6000d000 0x1000>;
 371                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 372                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 373                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 374                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 375                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 376                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 377                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 378                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 379                 #gpio-cells = <2>;
 380                 gpio-controller;
 381                 #interrupt-cells = <2>;
 382                 interrupt-controller;
 383                 /*
 384                 gpio-ranges = <&pinmux 0 0 248>;
 385                 */
 386         };
 387
 388         vde@6001a000 {
 389                 compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
 390                 reg = <0x6001a000 0x1000   /* Syntax Engine */
 391                        0x6001b000 0x1000   /* Video Bitstream Engine */
 392                        0x6001c000  0x100   /* Macroblock Engine */
 393                        0x6001c200  0x100   /* Post-processing Engine */
 394                        0x6001c400  0x100   /* Motion Compensation Engine */
 395                        0x6001c600  0x100   /* Transform Engine */
 396                        0x6001c800  0x100   /* Pixel prediction block */
 397                        0x6001ca00  0x100   /* Video DMA */
 398                        0x6001d800  0x400>; /* Video frame controls */
 399                 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
 400                             "tfe", "ppb", "vdma", "frameid";
 401                 iram = <&vde_pool>; /* IRAM region */
 402                 interrupts = <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
 403                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
 404                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
 405                 interrupt-names = "sync-token", "bsev", "sxe";
 406                 clocks = <&tegra_car TEGRA30_CLK_VDE>;
 407                 resets = <&tegra_car 61>;
 408         };
 409
 410         apbmisc@70000800 {
 411                 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
 412                 reg = <0x70000800 0x64   /* Chip revision */
 413                        0x70000008 0x04>; /* Strapping options */
 414         };
 415
 416         pinmux: pinmux@70000868 {
 417                 compatible = "nvidia,tegra30-pinmux";
 418                 reg = <0x70000868 0xd4    /* Pad control registers */
 419                        0x70003000 0x3e4>; /* Mux registers */
 420         };
 421
 422         /*
 423          * There are two serial driver i.e. 8250 based simple serial
 424          * driver and APB DMA based serial driver for higher baudrate
 425          * and performace. To enable the 8250 based driver, the compatible
 426          * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
 427          * the APB DMA based serial driver, the compatible is
 428          * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
 429          */
 430         uarta: serial@70006000 {
 431                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 432                 reg = <0x70006000 0x40>;
 433                 reg-shift = <2>;
 434                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 435                 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
 436                 resets = <&tegra_car 6>;
 437                 reset-names = "serial";
 438                 dmas = <&apbdma 8>, <&apbdma 8>;
 439                 dma-names = "rx", "tx";
 440                 status = "disabled";
 441         };
 442
 443         uartb: serial@70006040 {
 444                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 445                 reg = <0x70006040 0x40>;
 446                 reg-shift = <2>;
 447                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 448                 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
 449                 resets = <&tegra_car 7>;
 450                 reset-names = "serial";
 451                 dmas = <&apbdma 9>, <&apbdma 9>;
 452                 dma-names = "rx", "tx";
 453                 status = "disabled";
 454         };
 455
 456         uartc: serial@70006200 {
 457                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 458                 reg = <0x70006200 0x100>;
 459                 reg-shift = <2>;
 460                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 461                 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
 462                 resets = <&tegra_car 55>;
 463                 reset-names = "serial";
 464                 dmas = <&apbdma 10>, <&apbdma 10>;
 465                 dma-names = "rx", "tx";
 466                 status = "disabled";
 467         };
 468
 469         uartd: serial@70006300 {
 470                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 471                 reg = <0x70006300 0x100>;
 472                 reg-shift = <2>;
 473                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 474                 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
 475                 resets = <&tegra_car 65>;
 476                 reset-names = "serial";
 477                 dmas = <&apbdma 19>, <&apbdma 19>;
 478                 dma-names = "rx", "tx";
 479                 status = "disabled";
 480         };
 481
 482         uarte: serial@70006400 {
 483                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 484                 reg = <0x70006400 0x100>;
 485                 reg-shift = <2>;
 486                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 487                 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
 488                 resets = <&tegra_car 66>;
 489                 reset-names = "serial";
 490                 dmas = <&apbdma 20>, <&apbdma 20>;
 491                 dma-names = "rx", "tx";
 492                 status = "disabled";
 493         };
 494
 495         gmi@70009000 {
 496                 compatible = "nvidia,tegra30-gmi";
 497                 reg = <0x70009000 0x1000>;
 498                 #address-cells = <2>;
 499                 #size-cells = <1>;
 500                 ranges = <0 0 0x48000000 0x7ffffff>;
 501                 clocks = <&tegra_car TEGRA30_CLK_NOR>;
 502                 clock-names = "gmi";
 503                 resets = <&tegra_car 42>;
 504                 reset-names = "gmi";
 505                 status = "disabled";
 506         };
 507
 508         pwm: pwm@7000a000 {
 509                 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
 510                 reg = <0x7000a000 0x100>;
 511                 #pwm-cells = <2>;
 512                 clocks = <&tegra_car TEGRA30_CLK_PWM>;
 513                 resets = <&tegra_car 17>;
 514                 reset-names = "pwm";
 515                 status = "disabled";
 516         };
 517
 518         rtc@7000e000 {
 519                 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
 520                 reg = <0x7000e000 0x100>;
 521                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 522                 clocks = <&tegra_car TEGRA30_CLK_RTC>;
 523         };
 524
 525         i2c@7000c000 {
 526                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 527                 reg = <0x7000c000 0x100>;
 528                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 529                 #address-cells = <1>;
 530                 #size-cells = <0>;
 531                 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
 532                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 533                 clock-names = "div-clk", "fast-clk";
 534                 resets = <&tegra_car 12>;
 535                 reset-names = "i2c";
 536                 dmas = <&apbdma 21>, <&apbdma 21>;
 537                 dma-names = "rx", "tx";
 538                 status = "disabled";
 539         };
 540
 541         i2c@7000c400 {
 542                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 543                 reg = <0x7000c400 0x100>;
 544                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 545                 #address-cells = <1>;
 546                 #size-cells = <0>;
 547                 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
 548                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 549                 clock-names = "div-clk", "fast-clk";
 550                 resets = <&tegra_car 54>;
 551                 reset-names = "i2c";
 552                 dmas = <&apbdma 22>, <&apbdma 22>;
 553                 dma-names = "rx", "tx";
 554                 status = "disabled";
 555         };
 556
 557         i2c@7000c500 {
 558                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 559                 reg = <0x7000c500 0x100>;
 560                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 561                 #address-cells = <1>;
 562                 #size-cells = <0>;
 563                 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
 564                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 565                 clock-names = "div-clk", "fast-clk";
 566                 resets = <&tegra_car 67>;
 567                 reset-names = "i2c";
 568                 dmas = <&apbdma 23>, <&apbdma 23>;
 569                 dma-names = "rx", "tx";
 570                 status = "disabled";
 571         };
 572
 573         i2c@7000c700 {
 574                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 575                 reg = <0x7000c700 0x100>;
 576                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 577                 #address-cells = <1>;
 578                 #size-cells = <0>;
 579                 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
 580                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 581                 resets = <&tegra_car 103>;
 582                 reset-names = "i2c";
 583                 clock-names = "div-clk", "fast-clk";
 584                 dmas = <&apbdma 26>, <&apbdma 26>;
 585                 dma-names = "rx", "tx";
 586                 status = "disabled";
 587         };
 588
 589         i2c@7000d000 {
 590                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 591                 reg = <0x7000d000 0x100>;
 592                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 593                 #address-cells = <1>;
 594                 #size-cells = <0>;
 595                 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
 596                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 597                 clock-names = "div-clk", "fast-clk";
 598                 resets = <&tegra_car 47>;
 599                 reset-names = "i2c";
 600                 dmas = <&apbdma 24>, <&apbdma 24>;
 601                 dma-names = "rx", "tx";
 602                 status = "disabled";
 603         };
 604
 605         spi@7000d400 {
 606                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 607                 reg = <0x7000d400 0x200>;
 608                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 609                 #address-cells = <1>;
 610                 #size-cells = <0>;
 611                 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
 612                 resets = <&tegra_car 41>;
 613                 reset-names = "spi";
 614                 dmas = <&apbdma 15>, <&apbdma 15>;
 615                 dma-names = "rx", "tx";
 616                 status = "disabled";
 617         };
 618
 619         spi@7000d600 {
 620                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 621                 reg = <0x7000d600 0x200>;
 622                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 623                 #address-cells = <1>;
 624                 #size-cells = <0>;
 625                 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
 626                 resets = <&tegra_car 44>;
 627                 reset-names = "spi";
 628                 dmas = <&apbdma 16>, <&apbdma 16>;
 629                 dma-names = "rx", "tx";
 630                 status = "disabled";
 631         };
 632
 633         spi@7000d800 {
 634                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 635                 reg = <0x7000d800 0x200>;
 636                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 637                 #address-cells = <1>;
 638                 #size-cells = <0>;
 639                 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
 640                 resets = <&tegra_car 46>;
 641                 reset-names = "spi";
 642                 dmas = <&apbdma 17>, <&apbdma 17>;
 643                 dma-names = "rx", "tx";
 644                 status = "disabled";
 645         };
 646
 647         spi@7000da00 {
 648                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 649                 reg = <0x7000da00 0x200>;
 650                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 651                 #address-cells = <1>;
 652                 #size-cells = <0>;
 653                 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
 654                 resets = <&tegra_car 68>;
 655                 reset-names = "spi";
 656                 dmas = <&apbdma 18>, <&apbdma 18>;
 657                 dma-names = "rx", "tx";
 658                 status = "disabled";
 659         };
 660
 661         spi@7000dc00 {
 662                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 663                 reg = <0x7000dc00 0x200>;
 664                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 665                 #address-cells = <1>;
 666                 #size-cells = <0>;
 667                 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
 668                 resets = <&tegra_car 104>;
 669                 reset-names = "spi";
 670                 dmas = <&apbdma 27>, <&apbdma 27>;
 671                 dma-names = "rx", "tx";
 672                 status = "disabled";
 673         };
 674
 675         spi@7000de00 {
 676                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 677                 reg = <0x7000de00 0x200>;
 678                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 679                 #address-cells = <1>;
 680                 #size-cells = <0>;
 681                 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
 682                 resets = <&tegra_car 106>;
 683                 reset-names = "spi";
 684                 dmas = <&apbdma 28>, <&apbdma 28>;
 685                 dma-names = "rx", "tx";
 686                 status = "disabled";
 687         };
 688
 689         kbc@7000e200 {
 690                 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
 691                 reg = <0x7000e200 0x100>;
 692                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 693                 clocks = <&tegra_car TEGRA30_CLK_KBC>;
 694                 resets = <&tegra_car 36>;
 695                 reset-names = "kbc";
 696                 status = "disabled";
 697         };
 698
 699         pmc@7000e400 {
 700                 compatible = "nvidia,tegra30-pmc";
 701                 reg = <0x7000e400 0x400>;
 702                 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
 703                 clock-names = "pclk", "clk32k_in";
 704         };
 705
 706         mc: memory-controller@7000f000 {
 707                 compatible = "nvidia,tegra30-mc";
 708                 reg = <0x7000f000 0x400>;
 709                 clocks = <&tegra_car TEGRA30_CLK_MC>;
 710                 clock-names = "mc";
 711
 712                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 713
 714                 #iommu-cells = <1>;
 715         };
 716
 717         fuse@7000f800 {
 718                 compatible = "nvidia,tegra30-efuse";
 719                 reg = <0x7000f800 0x400>;
 720                 clocks = <&tegra_car TEGRA30_CLK_FUSE>;
 721                 clock-names = "fuse";
 722                 resets = <&tegra_car 39>;
 723                 reset-names = "fuse";
 724         };
 725
 726         hda@70030000 {
 727                 compatible = "nvidia,tegra30-hda";
 728                 reg = <0x70030000 0x10000>;
 729                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 730                 clocks = <&tegra_car TEGRA30_CLK_HDA>,
 731                          <&tegra_car TEGRA30_CLK_HDA2HDMI>,
 732                          <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
 733                 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
 734                 resets = <&tegra_car 125>, /* hda */
 735                          <&tegra_car 128>, /* hda2hdmi */
 736                          <&tegra_car 111>; /* hda2codec_2x */
 737                 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
 738                 status = "disabled";
 739         };
 740
 741         ahub@70080000 {
 742                 compatible = "nvidia,tegra30-ahub";
 743                 reg = <0x70080000 0x200
 744                        0x70080200 0x100>;
 745                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 746                 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
 747                          <&tegra_car TEGRA30_CLK_APBIF>;
 748                 clock-names = "d_audio", "apbif";
 749                 resets = <&tegra_car 106>, /* d_audio */
 750                          <&tegra_car 107>, /* apbif */
 751                          <&tegra_car 30>,  /* i2s0 */
 752                          <&tegra_car 11>,  /* i2s1 */
 753                          <&tegra_car 18>,  /* i2s2 */
 754                          <&tegra_car 101>, /* i2s3 */
 755                          <&tegra_car 102>, /* i2s4 */
 756                          <&tegra_car 108>, /* dam0 */
 757                          <&tegra_car 109>, /* dam1 */
 758                          <&tegra_car 110>, /* dam2 */
 759                          <&tegra_car 10>;  /* spdif */
 760                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 761                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 762                               "spdif";
 763                 dmas = <&apbdma 1>, <&apbdma 1>,
 764                        <&apbdma 2>, <&apbdma 2>,
 765                        <&apbdma 3>, <&apbdma 3>,
 766                        <&apbdma 4>, <&apbdma 4>;
 767                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 768                             "rx3", "tx3";
 769                 ranges;
 770                 #address-cells = <1>;
 771                 #size-cells = <1>;
 772
 773                 tegra_i2s0: i2s@70080300 {
 774                         compatible = "nvidia,tegra30-i2s";
 775                         reg = <0x70080300 0x100>;
 776                         nvidia,ahub-cif-ids = <4 4>;
 777                         clocks = <&tegra_car TEGRA30_CLK_I2S0>;
 778                         resets = <&tegra_car 30>;
 779                         reset-names = "i2s";
 780                         status = "disabled";
 781                 };
 782
 783                 tegra_i2s1: i2s@70080400 {
 784                         compatible = "nvidia,tegra30-i2s";
 785                         reg = <0x70080400 0x100>;
 786                         nvidia,ahub-cif-ids = <5 5>;
 787                         clocks = <&tegra_car TEGRA30_CLK_I2S1>;
 788                         resets = <&tegra_car 11>;
 789                         reset-names = "i2s";
 790                         status = "disabled";
 791                 };
 792
 793                 tegra_i2s2: i2s@70080500 {
 794                         compatible = "nvidia,tegra30-i2s";
 795                         reg = <0x70080500 0x100>;
 796                         nvidia,ahub-cif-ids = <6 6>;
 797                         clocks = <&tegra_car TEGRA30_CLK_I2S2>;
 798                         resets = <&tegra_car 18>;
 799                         reset-names = "i2s";
 800                         status = "disabled";
 801                 };
 802
 803                 tegra_i2s3: i2s@70080600 {
 804                         compatible = "nvidia,tegra30-i2s";
 805                         reg = <0x70080600 0x100>;
 806                         nvidia,ahub-cif-ids = <7 7>;
 807                         clocks = <&tegra_car TEGRA30_CLK_I2S3>;
 808                         resets = <&tegra_car 101>;
 809                         reset-names = "i2s";
 810                         status = "disabled";
 811                 };
 812
 813                 tegra_i2s4: i2s@70080700 {
 814                         compatible = "nvidia,tegra30-i2s";
 815                         reg = <0x70080700 0x100>;
 816                         nvidia,ahub-cif-ids = <8 8>;
 817                         clocks = <&tegra_car TEGRA30_CLK_I2S4>;
 818                         resets = <&tegra_car 102>;
 819                         reset-names = "i2s";
 820                         status = "disabled";
 821                 };
 822         };
 823
 824         sdhci@78000000 {
 825                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 826                 reg = <0x78000000 0x200>;
 827                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 828                 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
 829                 resets = <&tegra_car 14>;
 830                 reset-names = "sdhci";
 831                 status = "disabled";
 832         };
 833
 834         sdhci@78000200 {
 835                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 836                 reg = <0x78000200 0x200>;
 837                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 838                 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
 839                 resets = <&tegra_car 9>;
 840                 reset-names = "sdhci";
 841                 status = "disabled";
 842         };
 843
 844         sdhci@78000400 {
 845                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 846                 reg = <0x78000400 0x200>;
 847                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 848                 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
 849                 resets = <&tegra_car 69>;
 850                 reset-names = "sdhci";
 851                 status = "disabled";
 852         };
 853
 854         sdhci@78000600 {
 855                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 856                 reg = <0x78000600 0x200>;
 857                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 858                 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
 859                 resets = <&tegra_car 15>;
 860                 reset-names = "sdhci";
 861                 status = "disabled";
 862         };
 863
 864         usb@7d000000 {
 865                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 866                 reg = <0x7d000000 0x4000>;
 867                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 868                 phy_type = "utmi";
 869                 clocks = <&tegra_car TEGRA30_CLK_USBD>;
 870                 resets = <&tegra_car 22>;
 871                 reset-names = "usb";
 872                 nvidia,needs-double-reset;
 873                 nvidia,phy = <&phy1>;
 874                 status = "disabled";
 875         };
 876
 877         phy1: usb-phy@7d000000 {
 878                 compatible = "nvidia,tegra30-usb-phy";
 879                 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
 880                 phy_type = "utmi";
 881                 clocks = <&tegra_car TEGRA30_CLK_USBD>,
 882                          <&tegra_car TEGRA30_CLK_PLL_U>,
 883                          <&tegra_car TEGRA30_CLK_USBD>;
 884                 clock-names = "reg", "pll_u", "utmi-pads";
 885                 resets = <&tegra_car 22>, <&tegra_car 22>;
 886                 reset-names = "usb", "utmi-pads";
 887                 nvidia,hssync-start-delay = <9>;
 888                 nvidia,idle-wait-delay = <17>;
 889                 nvidia,elastic-limit = <16>;
 890                 nvidia,term-range-adj = <6>;
 891                 nvidia,xcvr-setup = <51>;
 892                 nvidia.xcvr-setup-use-fuses;
 893                 nvidia,xcvr-lsfslew = <1>;
 894                 nvidia,xcvr-lsrslew = <1>;
 895                 nvidia,xcvr-hsslew = <32>;
 896                 nvidia,hssquelch-level = <2>;
 897                 nvidia,hsdiscon-level = <5>;
 898                 nvidia,has-utmi-pad-registers;
 899                 status = "disabled";
 900         };
 901
 902         usb@7d004000 {
 903                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 904                 reg = <0x7d004000 0x4000>;
 905                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 906                 phy_type = "utmi";
 907                 clocks = <&tegra_car TEGRA30_CLK_USB2>;
 908                 resets = <&tegra_car 58>;
 909                 reset-names = "usb";
 910                 nvidia,phy = <&phy2>;
 911                 status = "disabled";
 912         };
 913
 914         phy2: usb-phy@7d004000 {
 915                 compatible = "nvidia,tegra30-usb-phy";
 916                 reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
 917                 phy_type = "utmi";
 918                 clocks = <&tegra_car TEGRA30_CLK_USB2>,
 919                          <&tegra_car TEGRA30_CLK_PLL_U>,
 920                          <&tegra_car TEGRA30_CLK_USBD>;
 921                 clock-names = "reg", "pll_u", "utmi-pads";
 922                 resets = <&tegra_car 58>, <&tegra_car 22>;
 923                 reset-names = "usb", "utmi-pads";
 924                 nvidia,hssync-start-delay = <9>;
 925                 nvidia,idle-wait-delay = <17>;
 926                 nvidia,elastic-limit = <16>;
 927                 nvidia,term-range-adj = <6>;
 928                 nvidia,xcvr-setup = <51>;
 929                 nvidia.xcvr-setup-use-fuses;
 930                 nvidia,xcvr-lsfslew = <2>;
 931                 nvidia,xcvr-lsrslew = <2>;
 932                 nvidia,xcvr-hsslew = <32>;
 933                 nvidia,hssquelch-level = <2>;
 934                 nvidia,hsdiscon-level = <5>;
 935                 status = "disabled";
 936         };
 937
 938         usb@7d008000 {
 939                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 940                 reg = <0x7d008000 0x4000>;
 941                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 942                 phy_type = "utmi";
 943                 clocks = <&tegra_car TEGRA30_CLK_USB3>;
 944                 resets = <&tegra_car 59>;
 945                 reset-names = "usb";
 946                 nvidia,phy = <&phy3>;
 947                 status = "disabled";
 948         };
 949
 950         phy3: usb-phy@7d008000 {
 951                 compatible = "nvidia,tegra30-usb-phy";
 952                 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
 953                 phy_type = "utmi";
 954                 clocks = <&tegra_car TEGRA30_CLK_USB3>,
 955                          <&tegra_car TEGRA30_CLK_PLL_U>,
 956                          <&tegra_car TEGRA30_CLK_USBD>;
 957                 clock-names = "reg", "pll_u", "utmi-pads";
 958                 resets = <&tegra_car 59>, <&tegra_car 22>;
 959                 reset-names = "usb", "utmi-pads";
 960                 nvidia,hssync-start-delay = <0>;
 961                 nvidia,idle-wait-delay = <17>;
 962                 nvidia,elastic-limit = <16>;
 963                 nvidia,term-range-adj = <6>;
 964                 nvidia,xcvr-setup = <51>;
 965                 nvidia.xcvr-setup-use-fuses;
 966                 nvidia,xcvr-lsfslew = <2>;
 967                 nvidia,xcvr-lsrslew = <2>;
 968                 nvidia,xcvr-hsslew = <32>;
 969                 nvidia,hssquelch-level = <2>;
 970                 nvidia,hsdiscon-level = <5>;
 971                 status = "disabled";
 972         };
 973
 974         cpus {
 975                 #address-cells = <1>;
 976                 #size-cells = <0>;
 977
 978                 cpu@0 {
 979                         device_type = "cpu";
 980                         compatible = "arm,cortex-a9";
 981                         reg = <0>;
 982                 };
 983
 984                 cpu@1 {
 985                         device_type = "cpu";
 986                         compatible = "arm,cortex-a9";
 987                         reg = <1>;
 988                 };
 989
 990                 cpu@2 {
 991                         device_type = "cpu";
 992                         compatible = "arm,cortex-a9";
 993                         reg = <2>;
 994                 };
 995
 996                 cpu@3 {
 997                         device_type = "cpu";
 998                         compatible = "arm,cortex-a9";
 999                         reg = <3>;
1000                 };
1001         };
1002
1003         pmu {
1004                 compatible = "arm,cortex-a9-pmu";
1005                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1006                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1007                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1008                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1009         };
1010 };