clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
resets = <&tegra_car 28>;
reset-names = "host1x";
+ iommus = <&mc TEGRA_SWGROUP_HC>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&tegra_car TEGRA30_CLK_MPE>;
resets = <&tegra_car 60>;
reset-names = "mpe";
+
+ iommus = <&mc TEGRA_SWGROUP_MPE>;
};
vi@54080000 {
clocks = <&tegra_car TEGRA30_CLK_VI>;
resets = <&tegra_car 20>;
reset-names = "vi";
+
+ iommus = <&mc TEGRA_SWGROUP_VI>;
};
epp@540c0000 {
clocks = <&tegra_car TEGRA30_CLK_EPP>;
resets = <&tegra_car 19>;
reset-names = "epp";
+
+ iommus = <&mc TEGRA_SWGROUP_EPP>;
};
isp@54100000 {
clocks = <&tegra_car TEGRA30_CLK_ISP>;
resets = <&tegra_car 23>;
reset-names = "isp";
+
+ iommus = <&mc TEGRA_SWGROUP_ISP>;
};
gr2d@54140000 {
clocks = <&tegra_car TEGRA30_CLK_GR2D>;
resets = <&tegra_car 21>;
reset-names = "2d";
+
+ iommus = <&mc TEGRA_SWGROUP_G2>;
};
gr3d@54180000 {
resets = <&tegra_car 24>,
<&tegra_car 98>;
reset-names = "3d", "3d2";
+
+ iommus = <&mc TEGRA_SWGROUP_NV>,
+ <&mc TEGRA_SWGROUP_NV2>;
};
dc@54200000 {