2 use IEEE.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
5 entity testbench_motones_sim is
6 end testbench_motones_sim;
8 architecture stimulus of testbench_motones_sim is
11 --logic analyzer reference clock
12 signal dbg_base_clk: out std_logic;
15 pi_base_clk : in std_logic;
16 pi_rst_n : in std_logic;
17 pi_joypad1 : in std_logic_vector(7 downto 0);
18 pi_joypad2 : in std_logic_vector(7 downto 0);
19 po_h_sync_n : out std_logic;
20 po_v_sync_n : out std_logic;
21 po_r : out std_logic_vector(3 downto 0);
22 po_g : out std_logic_vector(3 downto 0);
23 po_b : out std_logic_vector(3 downto 0);
24 pi_nt_v_mirror : in std_logic
28 signal dbg_base_clk : std_logic;
29 signal base_clk : std_logic;
30 signal reset_input : std_logic;
31 signal nmi_input : std_logic;
32 signal dbg_nmi : std_logic;
33 signal dummy_nmi : std_logic;
35 signal h_sync_n : std_logic;
36 signal v_sync_n : std_logic;
37 signal r : std_logic_vector(3 downto 0);
38 signal g : std_logic_vector(3 downto 0);
39 signal b : std_logic_vector(3 downto 0);
40 signal joypad1 : std_logic_vector(7 downto 0);
41 signal joypad2 : std_logic_vector(7 downto 0);
42 signal nt_v_mirror : std_logic;
44 constant powerup_time : time := 2 us;
45 constant reset_time : time := 890 ns;
47 ---clock frequency = 21,477,270 (21 MHz)
48 --constant base_clock_time : time := 46 ns;
50 --DE1 base clock = 50 MHz
51 constant base_clock_time : time := 20 ns;
55 sim_board : de0_cv_nes port map (
57 base_clk, reset_input, joypad1, joypad2,
58 h_sync_n, v_sync_n, r, g, b, nt_v_mirror);
64 wait for powerup_time;
73 --- generate base clock.
77 wait for base_clock_time / 2;
79 wait for base_clock_time / 2;
84 constant nmi_wait : time := 100657965 ps;
85 --constant nmi_wait : time := 10 ms;
86 constant vblank_time : time := 60 us;
87 variable wait_cnt : integer := 0;
90 if (wait_cnt = 0) then
92 wait for powerup_time + reset_time + nmi_wait;
93 wait_cnt := wait_cnt + 1;
96 wait for vblank_time ;
98 wait for vblank_time / 4;
102 dummy_nmi <= nmi_input;
105 --set chr rom mirror setting.