clock enabler update

diff --git a/de0_cv_nes/chip_selector.vhd b/de0_cv_nes/chip_selector.vhd
index 72628bb..6db7a1e 100644 (file)
--- a/de0_cv_nes/chip_selector.vhd
+++ b/de0_cv_nes/chip_selector.vhd
@@ -34,7 +34,7 @@ begin
     po_ppu_en <= reg_ppu_en;\r
     \r
     cpu_clk_p : process (pi_rst_n, pi_base_clk)\r
-    variable ref_cnt : integer range 0 to 15;\r
+    variable ref_cnt : integer range 0 to 31;\r
     begin\r
         if (pi_rst_n = '0') then\r
             reg_cpu_en <= (others => '0');\r
@@ -43,28 +43,33 @@ begin
             if (rising_edge(pi_base_clk)) then\r
                 if (ref_cnt = 0) then\r
                     reg_cpu_en <= "00000001";\r
-                elsif (ref_cnt = 3) then\r
+                elsif (ref_cnt = 4) then\r
                     reg_cpu_en <= "00000010";\r
-                elsif (ref_cnt = 7) then\r
+                elsif (ref_cnt = 8) then\r
                     reg_cpu_en <= "00000100";\r
-                elsif (ref_cnt = 11) then\r
+                elsif (ref_cnt = 12) then\r
                     reg_cpu_en <= "00001000";\r
-                elsif (ref_cnt = 15) then\r
+                elsif (ref_cnt = 16) then\r
                     reg_cpu_en <= "00010000";\r
-                elsif (ref_cnt = 19) then\r
+                elsif (ref_cnt = 20) then\r
                     reg_cpu_en <= "00100000";\r
-                elsif (ref_cnt = 23) then\r
+                elsif (ref_cnt = 24) then\r
                     reg_cpu_en <= "01000000";\r
-                elsif (ref_cnt = 27) then\r
+                elsif (ref_cnt = 28) then\r
                     reg_cpu_en <= "10000000";\r
                 end if;\r
-                ref_cnt := ref_cnt + 1;\r
+\r
+                if (ref_cnt = 31) then\r
+                    ref_cnt := 0;\r
+                else\r
+                    ref_cnt := ref_cnt + 1;\r
+                end if;\r
             end if;\r
         end if;\r
     end process;\r
 \r
     ppu_clk_p : process (pi_rst_n, pi_base_clk)\r
-    variable ref_cnt : integer range 0 to 31;\r
+    variable ref_cnt : integer range 0 to 15;\r
     begin\r
         if (pi_rst_n = '0') then\r
             reg_ppu_en <= (others => '0');\r
@@ -73,14 +78,21 @@ begin
             if (rising_edge(pi_base_clk)) then\r
                 if (ref_cnt = 0) then\r
                     reg_ppu_en <= "0001";\r
-                elsif (ref_cnt = 3) then\r
+                elsif (ref_cnt = 4) then\r
                     reg_ppu_en <= "0010";\r
-                elsif (ref_cnt = 7) then\r
+                elsif (ref_cnt = 8) then\r
                     reg_ppu_en <= "0100";\r
-                elsif (ref_cnt = 11) then\r
+                elsif (ref_cnt = 12) then\r
                     reg_ppu_en <= "1000";\r
+                else\r
+                    reg_ppu_en <= "0000";\r
+                end if;\r
+                \r
+                if (ref_cnt = 15) then\r
+                    ref_cnt := 0;\r
+                else\r
+                    ref_cnt := ref_cnt + 1;\r
                 end if;\r
-                ref_cnt := ref_cnt + 1;\r
             end if;\r
         end if;\r
     end process;\r

diff --git a/de0_cv_nes/de0_cv_nes.qsf b/de0_cv_nes/de0_cv_nes.qsf
index d450833..f8f1c86 100644 (file)
--- a/de0_cv_nes/de0_cv_nes.qsf
+++ b/de0_cv_nes/de0_cv_nes.qsf
@@ -42,7 +42,7 @@ set_global_assignment -name DEVICE 5CEBA4F23C7
 set_global_assignment -name TOP_LEVEL_ENTITY de0_cv_nes\r
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0\r
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:11:02  MAY 18, 2016"\r
-set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"\r
+set_global_assignment -name LAST_QUARTUS_VERSION 14.0\r
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files\r
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0\r
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85\r

diff --git a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
index bc1eabb..6b90a4c 100644 (file)
--- a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
+++ b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
@@ -15,20 +15,21 @@ vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -
 ##script custom part...\r
 \r
 \r
-#add wave -label rst_n sim:/testbench_motones_sim/sim_board/pi_rst_n;\r
+add wave -label rst_n sim:/testbench_motones_sim/sim_board/pi_rst_n;\r
 #add wave -label r_nw sim:/testbench_motones_sim/sim_board/wr_r_nw;\r
-#add wave -label base_clk sim:/testbench_motones_sim/sim_board/pi_base_clk;\r
+add wave -label base_clk sim:/testbench_motones_sim/sim_board/pi_base_clk;\r
 \r
 #add wave sim:/testbench_motones_sim/*;\r
 #add wave sim:/testbench_motones_sim/sim_board/*;\r
-add wave sim:/testbench_motones_sim/sim_board/chip_selector_inst/*;\r
+add wave sim:/testbench_motones_sim/sim_board/chip_selector_inst/reg_cpu_en;\r
+add wave sim:/testbench_motones_sim/sim_board/chip_selector_inst/reg_ppu_en;\r
 \r
 \r
 view structure\r
 view signals\r
 \r
-run 8 us\r
-run 100 us\r
+run 300 ns\r
 wave zoom full\r
 \r
+run 5 us\r
 \r

diff --git a/de0_cv_nes/testbench_motones_sim.vhd b/de0_cv_nes/testbench_motones_sim.vhd
new file mode 100644 (file)
index 0000000..d5282e0
--- /dev/null
+++ b/de0_cv_nes/testbench_motones_sim.vhd
@@ -0,0 +1,108 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity testbench_motones_sim is
+end testbench_motones_sim;
+
+architecture stimulus of testbench_motones_sim is 
+    component de0_cv_nes
+    port (
+--logic analyzer reference clock
+    signal dbg_base_clk: out std_logic;
+    
+--NES instance
+        pi_base_clk    : in std_logic;
+        pi_rst_n       : in std_logic;
+        pi_joypad1     : in std_logic_vector(7 downto 0);
+        pi_joypad2     : in std_logic_vector(7 downto 0);
+        po_h_sync_n    : out std_logic;
+        po_v_sync_n    : out std_logic;
+        po_r           : out std_logic_vector(3 downto 0);
+        po_g           : out std_logic_vector(3 downto 0);
+        po_b           : out std_logic_vector(3 downto 0);
+        pi_nt_v_mirror : in std_logic
+         );
+    end component;
+
+    signal dbg_base_clk     : std_logic;
+    signal base_clk         : std_logic;
+    signal reset_input      : std_logic;
+    signal nmi_input      : std_logic;
+    signal dbg_nmi      : std_logic;
+    signal dummy_nmi  : std_logic;
+
+    signal h_sync_n    : std_logic;
+    signal v_sync_n    : std_logic;
+    signal r           : std_logic_vector(3 downto 0);
+    signal g           : std_logic_vector(3 downto 0);
+    signal b           : std_logic_vector(3 downto 0);
+    signal joypad1     : std_logic_vector(7 downto 0);
+    signal joypad2     : std_logic_vector(7 downto 0);
+    signal nt_v_mirror : std_logic;
+
+    constant powerup_time   : time := 2 us;
+    constant reset_time     : time := 890 ns;
+
+    ---clock frequency = 21,477,270 (21 MHz)
+    --constant base_clock_time : time := 46 ns;
+
+    --DE1 base clock = 50 MHz
+    constant base_clock_time : time := 20 ns;
+
+begin
+
+    sim_board : de0_cv_nes port map (
+    dbg_base_clk,
+    base_clk, reset_input, joypad1, joypad2, 
+            h_sync_n, v_sync_n, r, g, b, nt_v_mirror);
+
+    --- input reset.
+    reset_p: process
+    begin
+        reset_input <= '1';
+        wait for powerup_time;
+
+        reset_input <= '0';
+        wait for reset_time;
+
+        reset_input <= '1';
+        wait;
+    end process;
+
+    --- generate base clock.
+    clock_p: process
+    begin
+        base_clk <= '1';
+        wait for base_clock_time / 2;
+        base_clk <= '0';
+        wait for base_clock_time / 2;
+    end process;
+
+    --- initiate nmi.
+    nmi_p: process
+    constant nmi_wait     : time := 100657965 ps;
+    --constant nmi_wait     : time := 10 ms;
+    constant vblank_time     : time := 60 us;
+    variable wait_cnt : integer := 0;
+    begin
+
+        if (wait_cnt = 0) then
+            nmi_input <= '1';
+            wait for powerup_time + reset_time + nmi_wait;
+            wait_cnt := wait_cnt + 1;
+        else
+            nmi_input <= '0';
+            wait for vblank_time ;
+            nmi_input <= '1';
+            wait for vblank_time / 4;
+        end if;
+    end process;
+    ---for test nmi...
+    dummy_nmi <= nmi_input;
+    --dummy_nmi <= 'Z';
+
+    --set chr rom mirror setting.
+    nt_v_mirror <= '1';
+end stimulus;
+