2 use IEEE.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
5 entity testbench_motones_sim is
6 end testbench_motones_sim;
8 architecture stimulus of testbench_motones_sim is
12 signal dbg_cpu_clk : out std_logic;
13 signal dbg_ppu_clk : out std_logic;
14 signal dbg_mem_clk : out std_logic;
15 signal dbg_r_nw : out std_logic;
16 signal dbg_addr : out std_logic_vector( 16 - 1 downto 0);
17 signal dbg_d_io : out std_logic_vector( 8 - 1 downto 0);
18 signal dbg_vram_ad : out std_logic_vector (7 downto 0);
19 signal dbg_vram_a : out std_logic_vector (13 downto 8);
22 signal dbg_instruction : out std_logic_vector(7 downto 0);
23 signal dbg_int_d_bus : out std_logic_vector(7 downto 0);
24 signal dbg_exec_cycle : out std_logic_vector (5 downto 0);
25 signal dbg_ea_carry : out std_logic;
26 signal dbg_status : out std_logic_vector(7 downto 0);
27 signal dbg_sp, dbg_x, dbg_y, dbg_acc : out std_logic_vector(7 downto 0);
28 signal dbg_dec_oe_n : out std_logic;
31 signal dbg_ppu_ce_n : out std_logic;
32 signal dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status : out std_logic_vector (7 downto 0);
33 signal dbg_ppu_addr : out std_logic_vector (13 downto 0);
34 signal dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y : out std_logic_vector (7 downto 0);
35 signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0);
36 signal dbg_nmi : out std_logic;
40 base_clk : in std_logic;
42 joypad1 : in std_logic_vector(7 downto 0);
43 joypad2 : in std_logic_vector(7 downto 0);
44 h_sync_n : out std_logic;
45 v_sync_n : out std_logic;
46 r : out std_logic_vector(3 downto 0);
47 g : out std_logic_vector(3 downto 0);
48 b : out std_logic_vector(3 downto 0)
52 constant powerup_time : time := 2 us;
53 constant reset_time : time := 890 ns;
55 ---clock frequency = 21,477,270 (21 MHz)
56 --constant base_clock_time : time := 46 ns;
58 --DE1 base clock = 50 MHz
59 constant base_clock_time : time := 20 ns;
62 signal dbg_cpu_clk : std_logic;
63 signal dbg_ppu_clk : std_logic;
64 signal dbg_mem_clk : std_logic;
65 signal dbg_r_nw : std_logic;
66 signal dbg_addr : std_logic_vector( 16 - 1 downto 0);
67 signal dbg_d_io : std_logic_vector( 8 - 1 downto 0);
68 signal dbg_vram_ad : std_logic_vector (7 downto 0);
69 signal dbg_vram_a : std_logic_vector (13 downto 8);
72 signal dbg_instruction : std_logic_vector(7 downto 0);
73 signal dbg_int_d_bus : std_logic_vector(7 downto 0);
74 signal dbg_exec_cycle : std_logic_vector (5 downto 0);
75 signal dbg_ea_carry : std_logic;
76 signal dbg_status : std_logic_vector(7 downto 0);
77 signal dbg_sp, dbg_x, dbg_y, dbg_acc : std_logic_vector(7 downto 0);
78 signal dbg_dec_oe_n : std_logic;
81 signal dbg_ppu_ce_n : std_logic;
82 signal dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status : std_logic_vector (7 downto 0);
83 signal dbg_ppu_addr : std_logic_vector (13 downto 0);
84 signal dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y : std_logic_vector (7 downto 0);
85 signal dbg_disp_nt, dbg_disp_attr : std_logic_vector (7 downto 0);
86 signal dbg_nmi : std_logic;
90 signal base_clk : std_logic;
91 signal rst_n : std_logic;
92 signal joypad1 : std_logic_vector(7 downto 0);
93 signal joypad2 : std_logic_vector(7 downto 0);
94 signal h_sync_n : std_logic;
95 signal v_sync_n : std_logic;
96 signal r : std_logic_vector(3 downto 0);
97 signal g : std_logic_vector(3 downto 0);
98 signal b : std_logic_vector(3 downto 0);
101 sim_board : de0_cv_nes port map (
112 ---monitor inside cpu
118 dbg_sp, dbg_x, dbg_y, dbg_acc ,
123 dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status ,
125 dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y ,
126 dbg_disp_nt, dbg_disp_attr ,
146 wait for powerup_time;
155 --- generate base clock.
159 wait for base_clock_time / 2;
161 wait for base_clock_time / 2;
166 -- constant nmi_wait : time := 100 us;
167 -- constant vblank_time : time := 60 us;
168 -- variable wait_cnt : integer := 0;
171 -- if (wait_cnt = 0) then
173 -- wait for powerup_time + reset_time + nmi_wait;
174 -- wait_cnt := wait_cnt + 1;
177 -- wait for vblank_time ;
179 -- wait for vblank_time / 4;