*.bak\r
*.qws\r
+*.rpt\r
output_files/*\r
db/*\r
incremental_db/*\r
simulation/modelsim/*.do.bak*\r
simulation/modelsim/msim_transcript\r
simulation/modelsim/*.vho\r
+simulation/modelsim/*.mti\r
simulation/modelsim/*.xrf\r
simulation/modelsim/*.sdo*\r
simulation/modelsim/*.sft\r
+simulation/modelsim/*.mif\r
+simulation/modelsim/*.hex\r
simulation/modelsim/vsim.wlf\r
simulation/modelsim/work/*\r
simulation/modelsim/transcript\r
phi1, phi2, addr, d_io);
--main ROM/RAM instance
--- prg_rom_inst : prg_rom generic map (rom_32k, data_size)
--- port map (mem_clk, rom_ce_n, addr(rom_32k - 1 downto 0), d_io);
-
- prg_rom_inst : prg_rom generic map (rom_8k, data_size)
- port map (mem_clk, rom_ce_n, addr(rom_8k - 1 downto 0), d_io);
+ prg_rom_inst : prg_rom generic map (rom_32k, data_size)
+ port map (mem_clk, rom_ce_n, addr(rom_32k - 1 downto 0), d_io);
ram_oe_n <= not R_nW;
prg_ram_inst : ram generic map (ram_2k, data_size)
--- /dev/null
+[Library]\r
+others = $MODEL_TECH/../modelsim.ini\r
+\r
+; Altera specific primitive library mappings \r
+\r
+work = work\r
+[vcom]\r
+; Turn on VHDL-1993 as the default. Normally is off.\r
+; VHDL93 = 1\r
+\r
+; Show source line containing error. Default is off.\r
+; Show_source = 1\r
+\r
+; Turn off unbound-component warnings. Default is on.\r
+; Show_Warning1 = 0\r
+\r
+; Turn off process-without-a-wait-statement warnings. Default is on.\r
+; Show_Warning2 = 0\r
+\r
+; Turn off null-range warnings. Default is on.\r
+; Show_Warning3 = 0\r
+\r
+; Turn off no-space-in-time-literal warnings. Default is on.\r
+; Show_Warning4 = 0\r
+\r
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.\r
+; Show_Warning5 = 0\r
+\r
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.\r
+; Optimize_1164 = 0\r
+\r
+; Turn on resolving of ambiguous function overloading in favor of the\r
+; "explicit" function declaration (not the one automatically created by\r
+; the compiler for each type declaration). Default is off.\r
+; .ini file has Explict enable so that std_logic_signed/unsigned\r
+; will match synthesis tools behavior.\r
+ Explicit = 1\r
+\r
+; Turn off VITAL compliance checking. Default is checking on.\r
+; NoVitalCheck = 1\r
+\r
+; Ignore VITAL compliance checking errors. Default is to not ignore.\r
+; IgnoreVitalErrors = 1\r
+\r
+; Turn off VITAL compliance checking warnings. Default is to show warnings.\r
+; Show_VitalChecksWarnings = false\r
+\r
+; Turn off acceleration of the VITAL packages. Default is to accelerate.\r
+; NoVital = 1\r
+\r
+; Turn off inclusion of debugging info within design units. Default is to include.\r
+; NoDebug = 1\r
+\r
+; Turn off "loading..." messages. Default is messages on.\r
+; Quiet = 1\r
+\r
+; Turn on some limited synthesis rule compliance checking. Checks only:\r
+; -- signals used (read) by a process must be in the sensitivity list\r
+; CheckSynthesis = 1\r
+\r
+; Require the user to specify a configuration for all bindings,\r
+; and do not generate a compile time default binding for the\r
+; component. This will result in an elaboration error of\r
+; 'component not bound' if the user fails to do so. Avoids the rare\r
+; issue of a false dependency upon the unused default binding.\r
+\r
+; RequireConfigForAllDefaultBinding = 1 \r
+\r
+[vlog]\r
+\r
+; Turn off inclusion of debugging info within design units. Default is to include.\r
+; NoDebug = 1\r
+\r
+; Turn off "loading..." messages. Default is messages on.\r
+; Quiet = 1\r
+\r
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).\r
+; Default is off.\r
+; Hazard = 1\r
+\r
+; Turn on converting regular Verilog identifiers to uppercase. Allows case\r
+; insensitivity for module names. Default is no conversion.\r
+; UpCase = 1\r
+\r
+; Turns on incremental compilation of modules \r
+; Incremental = 1\r
+\r
+[vsim]\r
+; Simulator resolution\r
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.\r
+Resolution = ps\r
+\r
+; User time unit for run commands\r
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the\r
+; unit specified for Resolution. For example, if Resolution is 100ps,\r
+; then UserTimeUnit defaults to ps.\r
+UserTimeUnit = default\r
+\r
+; Default run length\r
+RunLength = 100\r
+\r
+; Maximum iterations that can be run without advancing simulation time\r
+IterationLimit = 5000\r
+\r
+; Directive to license manager:\r
+; vhdl Immediately reserve a VHDL license\r
+; vlog Immediately reserve a Verilog license\r
+; plus Immediately reserve a VHDL and Verilog license\r
+; nomgc Do not look for Mentor Graphics Licenses\r
+; nomti Do not look for Model Technology Licenses\r
+; noqueue Do not wait in the license queue when a license isn't available\r
+; License = plus\r
+\r
+; Stop the simulator after an assertion message\r
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal\r
+BreakOnAssertion = 3\r
+\r
+; Assertion Message Format\r
+; %S - Severity Level \r
+; %R - Report Message\r
+; %T - Time of assertion\r
+; %D - Delta\r
+; %I - Instance or Region pathname (if available)\r
+; %% - print '%' character\r
+; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"\r
+\r
+; Assertion File - alternate file for storing assertion messages\r
+; AssertFile = assert.log\r
+\r
+; Default radix for all windows and commands...\r
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned\r
+DefaultRadix = symbolic\r
+\r
+; VSIM Startup command\r
+; Startup = do startup.do\r
+\r
+; File for saving command transcript\r
+TranscriptFile = transcript\r
+\r
+; File for saving command history \r
+;CommandHistory = cmdhist.log\r
+\r
+; Specify whether paths in simulator commands should be described \r
+; in VHDL or Verilog format. For VHDL, PathSeparator = /\r
+; for Verilog, PathSeparator = .\r
+PathSeparator = /\r
+\r
+; Specify the dataset separator for fully rooted contexts.\r
+; The default is ':'. For example, sim:/top\r
+; Must not be the same character as PathSeparator.\r
+DatasetSeparator = :\r
+\r
+; Disable assertion messages\r
+; IgnoreNote = 1\r
+; IgnoreWarning = 1\r
+; IgnoreError = 1\r
+; IgnoreFailure = 1\r
+\r
+; Default force kind. May be freeze, drive, or deposit \r
+; or in other terms, fixed, wired or charged.\r
+; DefaultForceKind = freeze\r
+\r
+; If zero, open files when elaborated\r
+; else open files on first read or write\r
+; DelayFileOpen = 0\r
+\r
+; Control VHDL files opened for write\r
+; 0 = Buffered, 1 = Unbuffered\r
+UnbufferedOutput = 0\r
+\r
+; Control number of VHDL files open concurrently\r
+; This number should always be less then the \r
+; current ulimit setting for max file descriptors\r
+; 0 = unlimited\r
+ConcurrentFileLimit = 40\r
+\r
+; This controls the number of hierarchical regions displayed as\r
+; part of a signal name shown in the waveform window. The default\r
+; value or a value of zero tells VSIM to display the full name.\r
+; WaveSignalNameWidth = 0\r
+\r
+; Turn off warnings from the std_logic_arith, std_logic_unsigned\r
+; and std_logic_signed packages.\r
+; StdArithNoWarnings = 1\r
+\r
+; Turn off warnings from the IEEE numeric_std and numeric_bit\r
+; packages.\r
+; NumericStdNoWarnings = 1\r
+\r
+; Control the format of a generate statement label. Don't quote it.\r
+; GenerateFormat = %s__%d\r
+\r
+; Specify whether checkpoint files should be compressed.\r
+; The default is to be compressed.\r
+; CheckpointCompressMode = 0\r
+\r
+; List of dynamically loaded objects for Verilog PLI applications\r
+; Veriuser = veriuser.sl\r
+[Project]\r
+; Warning -- Do not edit the project properties directly.\r
+; Property names are dynamic in nature and property\r
+; values have special syntax. Changing property data directly\r
+; can result in a corrupt MPF file. All project properties\r
+; can be modified through project window dialogs.\r
+Project_Version = 6\r
+Project_DefaultLib = work\r
+Project_SortMethod = unused\r
+Project_Files_Count = 0\r
+Project_Sim_Count = 1\r
+Project_Sim_0 = Simulation 1\r
+Project_Sim_P_0 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {Top Level} +pulse_e {} additional_dus de0_cv_nes -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}\r
+Project_Folder_Count = 0\r
+Echo_Compile_Output = 0\r
+Save_Compile_Report = 1\r
+Project_Opt_Count = 0\r
+ForceSoftPaths = 0\r
+ProjectStatusDelay = 5000\r
+VERILOG_DoubleClick = Edit\r
+VERILOG_CustomDoubleClick = \r
+SYSTEMVERILOG_DoubleClick = Edit\r
+SYSTEMVERILOG_CustomDoubleClick = \r
+VHDL_DoubleClick = Edit\r
+VHDL_CustomDoubleClick = \r
+PSL_DoubleClick = Edit\r
+PSL_CustomDoubleClick = \r
+TEXT_DoubleClick = Edit\r
+TEXT_CustomDoubleClick = \r
+SYSTEMC_DoubleClick = Edit\r
+SYSTEMC_CustomDoubleClick = \r
+TCL_DoubleClick = Edit\r
+TCL_CustomDoubleClick = \r
+MACRO_DoubleClick = Edit\r
+MACRO_CustomDoubleClick = \r
+VCD_DoubleClick = Edit\r
+VCD_CustomDoubleClick = \r
+SDF_DoubleClick = Edit\r
+SDF_CustomDoubleClick = \r
+XML_DoubleClick = Edit\r
+XML_CustomDoubleClick = \r
+LOGFILE_DoubleClick = Edit\r
+LOGFILE_CustomDoubleClick = \r
+UCDB_DoubleClick = Edit\r
+UCDB_CustomDoubleClick = \r
+UPF_DoubleClick = Edit\r
+UPF_CustomDoubleClick = \r
+PCF_DoubleClick = Edit\r
+PCF_CustomDoubleClick = \r
+PROJECT_DoubleClick = Edit\r
+PROJECT_CustomDoubleClick = \r
+VRM_DoubleClick = Edit\r
+VRM_CustomDoubleClick = \r
+DEBUGDATABASE_DoubleClick = Edit\r
+DEBUGDATABASE_CustomDoubleClick = \r
+DEBUGARCHIVE_DoubleClick = Edit\r
+DEBUGARCHIVE_CustomDoubleClick = \r
+Project_Major_Version = 10\r
+Project_Minor_Version = 1\r
--- /dev/null
+transcript on\r
+if {[file exists gate_work]} {\r
+ vdel -lib gate_work -all\r
+}\r
+vlib gate_work\r
+vmap work gate_work\r
+\r
+vcom -93 -work work {de0_cv_nes.vho}\r
+\r
+vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de0_cv_nes/testbench_motones_sim.vhd}\r
+\r
+vsim -t 1ps +transport_int_delays +transport_path_delays -sdftyp /NA=de0_cv_nes_vhd.sdo -L altera -L altera_lnsim -L cyclonev -L gate_work -L work -voptargs="+acc" testbench_motones_sim\r
+\r
+add wave *\r
+view structure\r
+view signals\r
+run -all\r
--- /dev/null
+transcript on\r
+if {[file exists rtl_work]} {\r
+ vdel -lib rtl_work -all\r
+}\r
+vlib rtl_work\r
+vmap work rtl_work\r
+\r
+vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/address_decoder.vhd}\r
+vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/motonesfpga_common.vhd}\r
+vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/clock/clock_divider.vhd}\r
+vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/mem/ram.vhd}\r
+vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/apu/apu.vhd}\r
+vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/ppu/ppu_registers.vhd}\r
+vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/cpu/cpu_registers.vhd}\r
+vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/cpu/mos6502.vhd}\r
+vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de0_cv_nes/de0_cv_nes.vhd}\r
+vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/mem/chr_rom.vhd}\r
+vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/ppu/ppu.vhd}\r
+vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/ppu/vga_ppu.vhd}\r
+vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/mem/prg_rom.vhd}\r
+vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/cpu/alu.vhd}\r
+vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de1_nes/cpu/decoder.vhd}\r
+\r
+vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de0_cv_nes/testbench_motones_sim.vhd}\r
+\r
+vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -L rtl_work -L work -voptargs="+acc" testbench_motones_sim\r
+\r
+#add wave *\r
+#view structure\r
+#view signals\r
+#run -all\r
+\r
+\r
+##script custom part...\r
+\r
+\r
+add wave -label rst_n sim:/testbench_motones_sim/sim_board/rst_n;\r
+add wave -label r_nw sim:/testbench_motones_sim/sim_board/r_nw;\r
+add wave -label cpu_clk sim:/testbench_motones_sim/sim_board/cpu_clk\r
+add wave -label addr -radix hex sim:/testbench_motones_sim/sim_board/addr\r
+add wave -label d_io -radix hex sim:/testbench_motones_sim/sim_board/d_io\r
+\r
+add wave -label instruction -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/instruction\r
+add wave -label int_d_bus -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/int_d_bus\r
+add wave -label exec_cycle -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/exec_cycle\r
+\r
+add wave -divider regs\r
+add wave -label acc -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/acc/q\r
+add wave -label status_val -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/status_register/status_val\r
+add wave -label sp -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/sp/q\r
+add wave -label x -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/x/q\r
+add wave -label y -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/y/q\r
+\r
+\r
+##add wave -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/status_reg\r
+\r
+add wave -divider ppu\r
+add wave -label cpu_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/cpu_addr\r
+add wave -label cpu_d -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/cpu_d\r
+add wave -label ppu_ce_n sim:/testbench_motones_sim/sim_board/ppu_inst/ce_n\r
+add wave -label ppu_clk sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk\r
+add wave -label ppu_clk_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk_cnt\r
+add wave -label ppu_ctl -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_ctrl\r
+add wave -label ppu_mask -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_mask\r
+add wave -label ppu_status -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_status\r
+#add wave -label ppu_addr_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_cnt\r
+#add wave -label ppu_addr_we_n -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_we_n\r
+#add wave -label ppu_addr_in -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_in\r
+#add wave -label ppu_addr_inc1 -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_inc1\r
+#add wave -label ppu_addr_inc32 -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_inc32\r
+add wave -label ppu_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr\r
+add wave -label ppu_data -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_data\r
+\r
+\r
+add wave -divider ppu_scrl\r
+add wave -label ppu_ce_n sim:/testbench_motones_sim/sim_board/ppu_inst/ce_n\r
+add wave -label ppu_clk sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk\r
+add wave -label ppu_scroll_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_cnt\r
+\r
+add wave -label ppu_clk_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk_cnt\r
+\r
+add wave -label ppu_scroll_cnt_ce_n sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_cnt_ce_n\r
+add wave -label ppu_scroll_x_we_n sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_x_we_n\r
+add wave -label ppu_scroll_y_we_n sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_y_we_n\r
+add wave -label ppu_scr_x -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_x\r
+add wave -label ppu_scr_y -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_y\r
+\r
+\r
+#add wave -divider render\r
+#\r
+##add wave -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/pos_x \\r
+##sim:/testbench_motones_sim/sim_board/ppu_inst/pos_y \r
+#\r
+##add wave -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/nes_r \\r
+##sim:/testbench_motones_sim/sim_board/ppu_inst/nes_g \\r
+##sim:/testbench_motones_sim/sim_board/ppu_inst/nes_b\r
+#\r
+#add wave -label h_sync_n sim:/testbench_motones_sim/sim_board/ppu_inst/h_sync_n\r
+#add wave -label v_sync_n sim:/testbench_motones_sim/sim_board/ppu_inst/v_sync_n\r
+\r
+\r
+\r
+#add wave -divider apu\r
+#add wave -label cpu_addr sim:/testbench_motones_sim/sim_board/apu_inst/dma_start_n\r
+#add wave -label dma_next_status -radix hex sim:/testbench_motones_sim/sim_board/apu_inst/dma_next_status\r
+#add wave -label dma_status -radix hex sim:/testbench_motones_sim/sim_board/apu_inst/dma_status\r
+#add wave -label dma_cnt_ce sim:/testbench_motones_sim/sim_board/apu_inst/dma_cnt_ce\r
+#add wave -label rdy sim:/testbench_motones_sim/sim_board/apu_inst/rdy\r
+#add wave -label dma_write_we_n sim:/testbench_motones_sim/sim_board/apu_inst/dma_write_we_n\r
+#add wave -label dma_addr -radix hex sim:/testbench_motones_sim/sim_board/apu_inst/dma_addr\r
+#add wave -label dma_start_n sim:/testbench_motones_sim/sim_board/apu_inst/dma_start_n\r
+#add wave -label dma_end_n sim:/testbench_motones_sim/sim_board/apu_inst/dma_end_n\r
+\r
+\r
+\r
+view structure\r
+view signals\r
+\r
+run 8 us\r
+wave zoom full\r
+\r
+#run 430 us\r
+\r
--- /dev/null
+; Copyright 1991-2009 Mentor Graphics Corporation\r
+;\r
+; All Rights Reserved.\r
+;\r
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF \r
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.\r
+; \r
+\r
+[Library]\r
+others = $MODEL_TECH/../modelsim.ini\r
+\r
+; Altera Primitive libraries\r
+;\r
+; VHDL Section\r
+;\r
+;\r
+; Verilog Section\r
+;\r
+\r
+work = gate_work\r
+[vcom]\r
+; VHDL93 variable selects language version as the default. \r
+; Default is VHDL-2002.\r
+; Value of 0 or 1987 for VHDL-1987.\r
+; Value of 1 or 1993 for VHDL-1993.\r
+; Default or value of 2 or 2002 for VHDL-2002.\r
+; Default or value of 3 or 2008 for VHDL-2008.\r
+VHDL93 = 2002\r
+\r
+; Show source line containing error. Default is off.\r
+; Show_source = 1\r
+\r
+; Turn off unbound-component warnings. Default is on.\r
+; Show_Warning1 = 0\r
+\r
+; Turn off process-without-a-wait-statement warnings. Default is on.\r
+; Show_Warning2 = 0\r
+\r
+; Turn off null-range warnings. Default is on.\r
+; Show_Warning3 = 0\r
+\r
+; Turn off no-space-in-time-literal warnings. Default is on.\r
+; Show_Warning4 = 0\r
+\r
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.\r
+; Show_Warning5 = 0\r
+\r
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.\r
+; Optimize_1164 = 0\r
+\r
+; Turn on resolving of ambiguous function overloading in favor of the\r
+; "explicit" function declaration (not the one automatically created by\r
+; the compiler for each type declaration). Default is off.\r
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned\r
+; will match the behavior of synthesis tools.\r
+Explicit = 1\r
+\r
+; Turn off acceleration of the VITAL packages. Default is to accelerate.\r
+; NoVital = 1\r
+\r
+; Turn off VITAL compliance checking. Default is checking on.\r
+; NoVitalCheck = 1\r
+\r
+; Ignore VITAL compliance checking errors. Default is to not ignore.\r
+; IgnoreVitalErrors = 1\r
+\r
+; Turn off VITAL compliance checking warnings. Default is to show warnings.\r
+; Show_VitalChecksWarnings = 0\r
+\r
+; Keep silent about case statement static warnings.\r
+; Default is to give a warning.\r
+; NoCaseStaticError = 1\r
+\r
+; Keep silent about warnings caused by aggregates that are not locally static.\r
+; Default is to give a warning.\r
+; NoOthersStaticError = 1\r
+\r
+; Turn off inclusion of debugging info within design units.\r
+; Default is to include debugging info.\r
+; NoDebug = 1\r
+\r
+; Turn off "Loading..." messages. Default is messages on.\r
+; Quiet = 1\r
+\r
+; Turn on some limited synthesis rule compliance checking. Checks only:\r
+; -- signals used (read) by a process must be in the sensitivity list\r
+; CheckSynthesis = 1\r
+\r
+; Activate optimizations on expressions that do not involve signals,\r
+; waits, or function/procedure/task invocations. Default is off.\r
+; ScalarOpts = 1\r
+\r
+; Require the user to specify a configuration for all bindings,\r
+; and do not generate a compile time default binding for the\r
+; component. This will result in an elaboration error of\r
+; 'component not bound' if the user fails to do so. Avoids the rare\r
+; issue of a false dependency upon the unused default binding.\r
+; RequireConfigForAllDefaultBinding = 1\r
+\r
+; Inhibit range checking on subscripts of arrays. Range checking on\r
+; scalars defined with subtypes is inhibited by default.\r
+; NoIndexCheck = 1\r
+\r
+; Inhibit range checks on all (implicit and explicit) assignments to\r
+; scalar objects defined with subtypes.\r
+; NoRangeCheck = 1\r
+\r
+[vlog]\r
+\r
+; Turn off inclusion of debugging info within design units.\r
+; Default is to include debugging info.\r
+; NoDebug = 1\r
+\r
+; Turn off "loading..." messages. Default is messages on.\r
+; Quiet = 1\r
+\r
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).\r
+; Default is off.\r
+; Hazard = 1\r
+\r
+; Turn on converting regular Verilog identifiers to uppercase. Allows case\r
+; insensitivity for module names. Default is no conversion.\r
+; UpCase = 1\r
+\r
+; Turn on incremental compilation of modules. Default is off.\r
+; Incremental = 1\r
+\r
+; Turns on lint-style checking.\r
+; Show_Lint = 1\r
+\r
+[vsim]\r
+; Simulator resolution\r
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.\r
+Resolution = ps\r
+\r
+; User time unit for run commands\r
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the\r
+; unit specified for Resolution. For example, if Resolution is 100ps,\r
+; then UserTimeUnit defaults to ps.\r
+; Should generally be set to default.\r
+UserTimeUnit = default\r
+\r
+; Default run length\r
+RunLength = 100\r
+\r
+; Maximum iterations that can be run without advancing simulation time\r
+IterationLimit = 5000\r
+\r
+; Directive to license manager:\r
+; vhdl Immediately reserve a VHDL license\r
+; vlog Immediately reserve a Verilog license\r
+; plus Immediately reserve a VHDL and Verilog license\r
+; nomgc Do not look for Mentor Graphics Licenses\r
+; nomti Do not look for Model Technology Licenses\r
+; noqueue Do not wait in the license queue when a license isn't available\r
+; viewsim Try for viewer license but accept simulator license(s) instead\r
+; of queuing for viewer license\r
+; License = plus\r
+\r
+; Stop the simulator after a VHDL/Verilog assertion message\r
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal\r
+BreakOnAssertion = 3\r
+\r
+; Assertion Message Format\r
+; %S - Severity Level \r
+; %R - Report Message\r
+; %T - Time of assertion\r
+; %D - Delta\r
+; %I - Instance or Region pathname (if available)\r
+; %% - print '%' character\r
+; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"\r
+\r
+; Assertion File - alternate file for storing VHDL/Verilog assertion messages\r
+; AssertFile = assert.log\r
+\r
+; Default radix for all windows and commands...\r
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned\r
+DefaultRadix = symbolic\r
+\r
+; VSIM Startup command\r
+; Startup = do startup.do\r
+\r
+; File for saving command transcript\r
+TranscriptFile = transcript\r
+\r
+; File for saving command history\r
+; CommandHistory = cmdhist.log\r
+\r
+; Specify whether paths in simulator commands should be described\r
+; in VHDL or Verilog format.\r
+; For VHDL, PathSeparator = /\r
+; For Verilog, PathSeparator = .\r
+; Must not be the same character as DatasetSeparator.\r
+PathSeparator = /\r
+\r
+; Specify the dataset separator for fully rooted contexts.\r
+; The default is ':'. For example, sim:/top\r
+; Must not be the same character as PathSeparator.\r
+DatasetSeparator = :\r
+\r
+; Disable VHDL assertion messages\r
+; IgnoreNote = 1\r
+; IgnoreWarning = 1\r
+; IgnoreError = 1\r
+; IgnoreFailure = 1\r
+\r
+; Default force kind. May be freeze, drive, deposit, or default\r
+; or in other terms, fixed, wired, or charged.\r
+; A value of "default" will use the signal kind to determine the\r
+; force kind, drive for resolved signals, freeze for unresolved signals\r
+; DefaultForceKind = freeze\r
+\r
+; If zero, open files when elaborated; otherwise, open files on\r
+; first read or write. Default is 0.\r
+; DelayFileOpen = 1\r
+\r
+; Control VHDL files opened for write.\r
+; 0 = Buffered, 1 = Unbuffered\r
+UnbufferedOutput = 0\r
+\r
+; Control the number of VHDL files open concurrently.\r
+; This number should always be less than the current ulimit\r
+; setting for max file descriptors.\r
+; 0 = unlimited\r
+ConcurrentFileLimit = 40\r
+\r
+; Control the number of hierarchical regions displayed as\r
+; part of a signal name shown in the Wave window.\r
+; A value of zero tells VSIM to display the full name.\r
+; The default is 0.\r
+; WaveSignalNameWidth = 0\r
+\r
+; Turn off warnings from the std_logic_arith, std_logic_unsigned\r
+; and std_logic_signed packages.\r
+; StdArithNoWarnings = 1\r
+\r
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.\r
+; NumericStdNoWarnings = 1\r
+\r
+; Control the format of the (VHDL) FOR generate statement label\r
+; for each iteration. Do not quote it.\r
+; The format string here must contain the conversion codes %s and %d,\r
+; in that order, and no other conversion codes. The %s represents\r
+; the generate_label; the %d represents the generate parameter value\r
+; at a particular generate iteration (this is the position number if\r
+; the generate parameter is of an enumeration type). Embedded whitespace\r
+; is allowed (but discouraged); leading and trailing whitespace is ignored.\r
+; Application of the format must result in a unique scope name over all\r
+; such names in the design so that name lookup can function properly.\r
+; GenerateFormat = %s__%d\r
+\r
+; Specify whether checkpoint files should be compressed.\r
+; The default is 1 (compressed).\r
+; CheckpointCompressMode = 0\r
+\r
+; List of dynamically loaded objects for Verilog PLI applications\r
+; Veriuser = veriuser.sl\r
+\r
+; Specify default options for the restart command. Options can be one\r
+; or more of: -force -nobreakpoint -nolist -nolog -nowave\r
+; DefaultRestartOptions = -force\r
+\r
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs\r
+; (> 500 megabyte memory footprint). Default is disabled.\r
+; Specify number of megabytes to lock.\r
+; LockedMemory = 1000\r
+\r
+; Turn on (1) or off (0) WLF file compression.\r
+; The default is 1 (compress WLF file).\r
+; WLFCompress = 0\r
+\r
+; Specify whether to save all design hierarchy (1) in the WLF file\r
+; or only regions containing logged signals (0).\r
+; The default is 0 (save only regions with logged signals).\r
+; WLFSaveAllRegions = 1\r
+\r
+; WLF file time limit. Limit WLF file by time, as closely as possible,\r
+; to the specified amount of simulation time. When the limit is exceeded\r
+; the earliest times get truncated from the file.\r
+; If both time and size limits are specified the most restrictive is used.\r
+; UserTimeUnits are used if time units are not specified.\r
+; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}\r
+; WLFTimeLimit = 0\r
+\r
+; WLF file size limit. Limit WLF file size, as closely as possible,\r
+; to the specified number of megabytes. If both time and size limits\r
+; are specified then the most restrictive is used.\r
+; The default is 0 (no limit).\r
+; WLFSizeLimit = 1000\r
+\r
+; Specify whether or not a WLF file should be deleted when the\r
+; simulation ends. A value of 1 will cause the WLF file to be deleted.\r
+; The default is 0 (do not delete WLF file when simulation ends).\r
+; WLFDeleteOnQuit = 1\r
+\r
+; Automatic SDF compilation\r
+; Disables automatic compilation of SDF files in flows that support it.\r
+; Default is on, uncomment to turn off.\r
+; NoAutoSDFCompile = 1\r
+\r
+[lmc]\r
+\r
+[msg_system]\r
+; Change a message severity or suppress a message.\r
+; The format is: <msg directive> = <msg number>[,<msg number>...]\r
+; Examples:\r
+; note = 3009\r
+; warning = 3033\r
+; error = 3010,3016\r
+; fatal = 3016,3033\r
+; suppress = 3009,3016,3043\r
+; The command verror <msg number> can be used to get the complete\r
+; description of a message.\r
+\r
+; Control transcripting of elaboration/runtime messages.\r
+; The default is to have messages appear in the transcript and \r
+; recorded in the wlf file (messages that are recorded in the\r
+; wlf file can be viewed in the MsgViewer). The other settings\r
+; are to send messages only to the transcript or only to the \r
+; wlf file. The valid values are\r
+; both {default}\r
+; tran {transcript only}\r
+; wlf {wlf file only}\r
+; msgmode = both\r
--- /dev/null
+library IEEE;
+use IEEE.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity testbench_motones_sim is
+end testbench_motones_sim;
+
+architecture stimulus of testbench_motones_sim is
+ component de0_cv_nes
+ port (
+--debug signal
+ signal dbg_cpu_clk : out std_logic;
+ signal dbg_ppu_clk : out std_logic;
+ signal dbg_mem_clk : out std_logic;
+ signal dbg_r_nw : out std_logic;
+ signal dbg_addr : out std_logic_vector( 16 - 1 downto 0);
+ signal dbg_d_io : out std_logic_vector( 8 - 1 downto 0);
+ signal dbg_vram_ad : out std_logic_vector (7 downto 0);
+ signal dbg_vram_a : out std_logic_vector (13 downto 8);
+
+---monitor inside cpu
+ signal dbg_instruction : out std_logic_vector(7 downto 0);
+ signal dbg_int_d_bus : out std_logic_vector(7 downto 0);
+ signal dbg_exec_cycle : out std_logic_vector (5 downto 0);
+ signal dbg_ea_carry : out std_logic;
+ signal dbg_status : out std_logic_vector(7 downto 0);
+ signal dbg_sp, dbg_x, dbg_y, dbg_acc : out std_logic_vector(7 downto 0);
+ signal dbg_dec_oe_n : out std_logic;
+
+--ppu debug pins
+ signal dbg_ppu_ce_n : out std_logic;
+ signal dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status : out std_logic_vector (7 downto 0);
+ signal dbg_ppu_addr : out std_logic_vector (13 downto 0);
+ signal dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y : out std_logic_vector (7 downto 0);
+ signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0);
+ signal dbg_nmi : out std_logic;
+
+
+--NES instance
+ base_clk : in std_logic;
+ rst_n : in std_logic;
+ joypad1 : in std_logic_vector(7 downto 0);
+ joypad2 : in std_logic_vector(7 downto 0);
+ h_sync_n : out std_logic;
+ v_sync_n : out std_logic;
+ r : out std_logic_vector(3 downto 0);
+ g : out std_logic_vector(3 downto 0);
+ b : out std_logic_vector(3 downto 0)
+ );
+ end component;
+
+ constant powerup_time : time := 2 us;
+ constant reset_time : time := 890 ns;
+
+ ---clock frequency = 21,477,270 (21 MHz)
+ --constant base_clock_time : time := 46 ns;
+
+ --DE1 base clock = 50 MHz
+ constant base_clock_time : time := 20 ns;
+
+--debug signal
+ signal dbg_cpu_clk : std_logic;
+ signal dbg_ppu_clk : std_logic;
+ signal dbg_mem_clk : std_logic;
+ signal dbg_r_nw : std_logic;
+ signal dbg_addr : std_logic_vector( 16 - 1 downto 0);
+ signal dbg_d_io : std_logic_vector( 8 - 1 downto 0);
+ signal dbg_vram_ad : std_logic_vector (7 downto 0);
+ signal dbg_vram_a : std_logic_vector (13 downto 8);
+
+---monitor inside cpu
+ signal dbg_instruction : std_logic_vector(7 downto 0);
+ signal dbg_int_d_bus : std_logic_vector(7 downto 0);
+ signal dbg_exec_cycle : std_logic_vector (5 downto 0);
+ signal dbg_ea_carry : std_logic;
+ signal dbg_status : std_logic_vector(7 downto 0);
+ signal dbg_sp, dbg_x, dbg_y, dbg_acc : std_logic_vector(7 downto 0);
+ signal dbg_dec_oe_n : std_logic;
+
+--ppu debug pins
+ signal dbg_ppu_ce_n : std_logic;
+ signal dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status : std_logic_vector (7 downto 0);
+ signal dbg_ppu_addr : std_logic_vector (13 downto 0);
+ signal dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y : std_logic_vector (7 downto 0);
+ signal dbg_disp_nt, dbg_disp_attr : std_logic_vector (7 downto 0);
+ signal dbg_nmi : std_logic;
+
+
+--NES instance
+ signal base_clk : std_logic;
+ signal rst_n : std_logic;
+ signal joypad1 : std_logic_vector(7 downto 0);
+ signal joypad2 : std_logic_vector(7 downto 0);
+ signal h_sync_n : std_logic;
+ signal v_sync_n : std_logic;
+ signal r : std_logic_vector(3 downto 0);
+ signal g : std_logic_vector(3 downto 0);
+ signal b : std_logic_vector(3 downto 0);
+begin
+
+ sim_board : de0_cv_nes port map (
+--debug signal
+ dbg_cpu_clk ,
+ dbg_ppu_clk ,
+ dbg_mem_clk ,
+ dbg_r_nw ,
+ dbg_addr ,
+ dbg_d_io ,
+ dbg_vram_ad ,
+ dbg_vram_a ,
+
+---monitor inside cpu
+ dbg_instruction ,
+ dbg_int_d_bus ,
+ dbg_exec_cycle ,
+ dbg_ea_carry ,
+ dbg_status ,
+ dbg_sp, dbg_x, dbg_y, dbg_acc ,
+ dbg_dec_oe_n ,
+
+--ppu debug pins
+ dbg_ppu_ce_n ,
+ dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status ,
+ dbg_ppu_addr ,
+ dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y ,
+ dbg_disp_nt, dbg_disp_attr ,
+ dbg_nmi ,
+
+
+--NES instance
+ base_clk ,
+ rst_n ,
+ joypad1 ,
+ joypad2 ,
+ h_sync_n ,
+ v_sync_n ,
+ r ,
+ g ,
+ b
+);
+
+ --- input reset.
+ reset_p: process
+ begin
+ rst_n <= '1';
+ wait for powerup_time;
+
+ rst_n <= '0';
+ wait for reset_time;
+
+ rst_n <= '1';
+ wait;
+ end process;
+
+ --- generate base clock.
+ clock_p: process
+ begin
+ base_clk <= '1';
+ wait for base_clock_time / 2;
+ base_clk <= '0';
+ wait for base_clock_time / 2;
+ end process;
+
+-- --- initiate nmi.
+-- nmi_p: process
+-- constant nmi_wait : time := 100 us;
+-- constant vblank_time : time := 60 us;
+-- variable wait_cnt : integer := 0;
+-- begin
+--
+-- if (wait_cnt = 0) then
+-- nmi_input <= '1';
+-- wait for powerup_time + reset_time + nmi_wait;
+-- wait_cnt := wait_cnt + 1;
+-- else
+-- nmi_input <= '0';
+-- wait for vblank_time ;
+-- nmi_input <= '1';
+-- wait for vblank_time / 4;
+-- end if;
+-- end process;
+
+end stimulus;
+
OSDN Git Service
