2 ----------------------------------------
3 --- d-flipflop with set/reset
4 ----------------------------------------
7 use ieee.std_logic_1164.all;
18 d : in std_logic_vector (dsize - 1 downto 0);
19 q : out std_logic_vector (dsize - 1 downto 0)
23 architecture rtl of d_flip_flop is
26 process (clk, res_n, set_n, d)
30 elsif (set_n = '0') then
32 elsif (clk'event and clk = '1') then
41 --------- 1 bit d-flipflop.
43 use ieee.std_logic_1164.all;
45 entity d_flip_flop_bit is
56 architecture rtl of d_flip_flop_bit is
59 process (clk, res_n, set_n, d)
63 elsif (set_n = '0') then
65 elsif (clk'event and clk = '1') then
73 ----------------------------------------
74 --- data latch declaration
75 ----------------------------------------
78 use ieee.std_logic_1164.all;
86 d : in std_logic_vector (dsize - 1 downto 0);
87 q : out std_logic_vector (dsize - 1 downto 0)
91 architecture rtl of data_latch is
97 --latch only when clock is high
103 ----------------------------------------
105 ----------------------------------------
108 use ieee.std_logic_1164.all;
110 entity tri_state_buffer is
116 d : in std_logic_vector (dsize - 1 downto 0);
117 q : out std_logic_vector (dsize - 1 downto 0)
119 end tri_state_buffer;
121 architecture rtl of tri_state_buffer is
123 q <= d when oe_n = '0' else
128 ----------------------------------------
129 --- dual port d flip flop w/ tri-state buffer
130 ----------------------------------------
133 use ieee.std_logic_1164.all;
141 res_n : in std_logic;
142 set_n : in std_logic;
143 gate_cmd : in std_logic_vector (3 downto 0);
144 front_port : inout std_logic_vector (dsize - 1 downto 0);
145 back_in_port : in std_logic_vector (dsize - 1 downto 0);
146 back_out_port : out std_logic_vector (dsize - 1 downto 0)
150 architecture rtl of dual_dff is
152 component d_flip_flop
158 res_n : in std_logic;
159 set_n : in std_logic;
161 d : in std_logic_vector (dsize - 1 downto 0);
162 q : out std_logic_vector (dsize - 1 downto 0)
166 component tri_state_buffer
172 d : in std_logic_vector (dsize - 1 downto 0);
173 q : out std_logic_vector (dsize - 1 downto 0)
177 signal we_n : std_logic;
178 signal q : std_logic_vector (dsize - 1 downto 0);
179 signal d : std_logic_vector (dsize - 1 downto 0);
182 ----------gate_cmd format
183 ------3 : front port oe_n
184 ------2 : front port we_n
185 ------1 : back port oe_n
186 ------0 : back port we_n
187 we_n <= (gate_cmd(2) and gate_cmd(0));
189 d <= front_port when gate_cmd(2) = '0' else
190 back_in_port when gate_cmd(0) = '0' else
193 dff_inst : d_flip_flop generic map (dsize)
194 port map(clk, res_n, set_n, we_n, d, q);
196 front_tsb : tri_state_buffer generic map (dsize)
197 port map(gate_cmd(3), q, front_port);
199 back_tsb : tri_state_buffer generic map (dsize)
200 port map(gate_cmd(1), q, back_out_port);
204 ----------------------------------------
206 ----------------------------------------
209 use ieee.std_logic_1164.all;
211 entity data_bus_buffer is
218 int_oe_n : in std_logic;
219 int_dbus : inout std_logic_vector (dsize - 1 downto 0);
220 ext_dbus : inout std_logic_vector (dsize - 1 downto 0)
224 architecture rtl of data_bus_buffer is
231 d : in std_logic_vector (dsize - 1 downto 0);
232 q : out std_logic_vector (dsize - 1 downto 0)
236 component tri_state_buffer
242 d : in std_logic_vector (dsize - 1 downto 0);
243 q : out std_logic_vector (dsize - 1 downto 0)
247 signal rd_clk : std_logic;
248 signal wr_clk : std_logic;
249 signal read_buf : std_logic_vector (dsize - 1 downto 0);
250 signal write_buf : std_logic_vector (dsize - 1 downto 0);
252 rd_clk <= r_nw and clk;
253 wr_clk <= (not r_nw) and clk;
255 --read from i/o to cpu
256 latch_r : data_latch generic map (dsize)
257 port map(rd_clk, ext_dbus, read_buf);
258 read_tsb : tri_state_buffer generic map (dsize)
259 port map(int_oe_n, read_buf, int_dbus);
260 --write from cpu to io
261 latch_w : data_latch generic map (dsize)
262 port map(wr_clk, int_dbus, write_buf);
263 write_tsb : tri_state_buffer generic map (dsize)
264 port map(r_nw, write_buf, ext_dbus);
267 ------------------------------------------
268 ----- input data latch register
269 ------------------------------------------
272 use ieee.std_logic_1164.all;
274 entity input_data_latch is
282 int_dbus : in std_logic_vector (dsize - 1 downto 0);
283 alu_bus : out std_logic_vector (dsize - 1 downto 0)
285 end input_data_latch;
287 architecture rtl of input_data_latch is
295 d : in std_logic_vector (dsize - 1 downto 0);
296 q : out std_logic_vector (dsize - 1 downto 0)
300 component tri_state_buffer
306 d : in std_logic_vector (dsize - 1 downto 0);
307 q : out std_logic_vector (dsize - 1 downto 0)
311 signal latch_clk : std_logic;
312 signal latch_buf : std_logic_vector (dsize - 1 downto 0);
315 latch_clk <= (not we_n) and clk;
316 latch_inst : data_latch generic map (dsize)
317 port map(latch_clk, int_dbus, latch_buf);
318 iput_data_tsb : tri_state_buffer generic map (dsize)
319 port map(oe_n, latch_buf, alu_bus);
323 ----------------------------------------
324 --- status register component
325 ----------------------------------------
328 use ieee.std_logic_1164.all;
330 entity processor_status is
336 res_n : in std_logic;
337 dec_oe_n : in std_logic;
338 bus_oe_n : in std_logic;
339 set_flg_n : in std_logic;
340 flg_val : in std_logic;
341 load_bus_all_n : in std_logic;
342 load_bus_nz_n : in std_logic;
343 set_from_alu_n : in std_logic;
344 alu_n : in std_logic;
345 alu_v : in std_logic;
346 alu_z : in std_logic;
347 alu_c : in std_logic;
348 stat_c : out std_logic;
349 dec_val : inout std_logic_vector (dsize - 1 downto 0);
350 int_dbus : inout std_logic_vector (dsize - 1 downto 0)
352 end processor_status;
354 architecture rtl of processor_status is
356 component d_flip_flop
362 res_n : in std_logic;
363 set_n : in std_logic;
365 d : in std_logic_vector (dsize - 1 downto 0);
366 q : out std_logic_vector (dsize - 1 downto 0)
370 component tri_state_buffer
376 d : in std_logic_vector (dsize - 1 downto 0);
377 q : out std_logic_vector (dsize - 1 downto 0)
381 signal we_n : std_logic;
382 signal d : std_logic_vector (dsize - 1 downto 0);
383 signal status_val : std_logic_vector (dsize - 1 downto 0);
386 dec_tsb : tri_state_buffer generic map (dsize)
387 port map(dec_oe_n, status_val, dec_val);
388 dbus_tsb : tri_state_buffer generic map (dsize)
389 port map(bus_oe_n, status_val, int_dbus);
391 we_n <= set_flg_n and load_bus_all_n and
392 load_bus_nz_n and set_from_alu_n;
394 dff_inst : d_flip_flop generic map (dsize)
395 port map(clk, '1', res_n, we_n, d, status_val);
397 --carry status for adc/sbc.
398 stat_c <= status_val(0);
400 main_p : process (clk, res_n, we_n, dec_val, int_dbus,
401 alu_n, alu_v, alu_z, alu_c)
402 variable tmp : std_logic_vector (dsize - 1 downto 0);
404 -- SR Flags (bit 7 to bit 0):
410 -- D .... Decimal (use BCD for arithmetics)
411 -- I .... Interrupt (IRQ disable)
415 ---only interrupt flag is set on reset.
416 if (res_n = '0') then
419 d <= (others => 'Z');
422 ---from flag set/clear instructions
423 if (set_flg_n = '0') then
424 if flg_val = '1' then
425 tmp := (dec_val and "11111111");
429 d <= tmp or (status_val and not dec_val);
431 ---status flag set from the data on the internal data bus.
432 ---interpret the input data by the dec_val input.
433 ---load/pop/rti/t[asxy]
434 elsif (load_bus_all_n = '0') then
435 ---set the data bus data as they are.
437 elsif (load_bus_nz_n = '0') then
439 d (6 downto 2) <= tmp (6 downto 2);
442 ---other case: n/z data must be interpreted.
444 if int_dbus(7) = '1' then
450 ---nor outputs 1 when all inputs are 0.
451 if (int_dbus(7) or int_dbus(6) or
452 int_dbus(5) or int_dbus(4) or int_dbus(3) or
453 int_dbus(2) or int_dbus(1) or int_dbus(0)) = '0' then
459 ---status set from alu
460 elsif (set_from_alu_n = '0') then
462 d (5 downto 2) <= tmp (5 downto 2);
465 if (dec_val(7) = '1') then
471 if (dec_val(6) = '1') then
477 if (dec_val(1) = '1') then
483 if (dec_val(0) = '1') then
488 end if; --if (set_flg_n = '0') then