pcl_inc_n, pch_inc_n, sp_oe_n, sp_push_n, sp_pop_n,
abs_xy_n, pg_next_n, zp_n, zp_xy_n, rel_calc_n,
indir_n, indir_x_n, indir_y_n,
- index_bus, bal, bal, addr_c_in, addr_out, addr_c,
+ index_bus, bal, bah, addr_c_in, addr_out, addr_c,
--for arithmatic operation.
arith_en_n,
d1 <= arith_reg_out;
int_d_bus <= d_out;
- if (clk = '0') then
- --d_print("clk hi");
- if (m2m_stat_1 = '0') then
- --first cycle. keep input variable.
- --d_print("inc first.");
- m2m_stat_1 <= '1';
- arith_buf_we_n <= '0';
- arith_buf_oe_n <= '1';
- d_oe_n <= '1';
-
- end if;
- end if;
-
- if (clk'event and clk = '0') then
- if (m2m_stat_2 = '0') then
- --second cycle read from register, output modified data.
- --d_print("inc second...");
- m2m_stat_2 <= '1';
- arith_buf_we_n <= '1';
- arith_buf_oe_n <= '0';
- d_oe_n <= '0';
- end if;
- end if;
+-- if (clk = '0') then
+-- --d_print("clk hi");
+-- if (m2m_stat_1 = '0') then
+-- --first cycle. keep input variable.
+-- --d_print("inc first.");
+-- m2m_stat_1 <= '1';
+-- arith_buf_we_n <= '0';
+-- arith_buf_oe_n <= '1';
+-- d_oe_n <= '1';
+--
+-- end if;
+-- end if;
+--
+-- if (clk'event and clk = '0') then
+-- if (m2m_stat_2 = '0') then
+-- --second cycle read from register, output modified data.
+-- --d_print("inc second...");
+-- m2m_stat_2 <= '1';
+-- arith_buf_we_n <= '1';
+-- arith_buf_oe_n <= '0';
+-- d_oe_n <= '0';
+-- end if;
+-- end if;
if instruction (7 downto 5) = "000" then
library ieee;
use ieee.std_logic_1164.all;
-entity latch is
+entity data_latch is
generic (
dsize : integer := 8
);
d : in std_logic_vector (dsize - 1 downto 0);
q : out std_logic_vector (dsize - 1 downto 0)
);
-end latch;
+end data_latch;
-architecture rtl of latch is
+architecture rtl of data_latch is
begin
process (clk, d)
end data_bus_buffer;
architecture rtl of data_bus_buffer is
-component latch
+component data_latch
generic (
dsize : integer := 8
);
wr_clk <= (not r_nw) and clk;
--read from i/o to cpu
- latch_r : latch generic map (dsize)
+ latch_r : data_latch generic map (dsize)
port map(rd_clk, ext_dbus, read_buf);
read_tsb : tri_state_buffer generic map (dsize)
port map(int_oe_n, read_buf, int_dbus);
--write from cpu to io
- latch_w : latch generic map (dsize)
+ latch_w : data_latch generic map (dsize)
port map(wr_clk, int_dbus, write_buf);
write_tsb : tri_state_buffer generic map (dsize)
port map(r_nw, write_buf, ext_dbus);
architecture rtl of input_data_latch is
-component latch
+component data_latch
generic (
dsize : integer := 8
);
begin
latch_clk <= (not we_n) and clk;
- latch_inst : latch generic map (dsize)
+ latch_inst : data_latch generic map (dsize)
port map(latch_clk, int_dbus, latch_buf);
iput_data_tsb : tri_state_buffer generic map (dsize)
port map(oe_n, latch_buf, alu_bus);
\r
begin
- if (res_n = '0') then
- --pc l/h is reset vector.
- pcl_cmd <= "1110";
- pch_cmd <= "1110";
- next_cycle <= R0;
- elsif (res_n'event and res_n = '1') then
- pcl_cmd <= "1111";
- pch_cmd <= "1111";
- end if;
-
- if (nmi_n'event and nmi_n = '1') then
- --reset nmi handle status
- nmi_handled_n := '1';
- end if;
+-- if (res_n = '0') then
+-- --pc l/h is reset vector.
+-- pcl_cmd <= "1110";
+-- pch_cmd <= "1110";
+-- next_cycle <= R0;
+-- elsif (res_n'event and res_n = '1') then
+-- pcl_cmd <= "1111";
+-- pch_cmd <= "1111";
+-- end if;
+--
+-- if (nmi_n'event and nmi_n = '1') then
+-- --reset nmi handle status
+-- nmi_handled_n := '1';
+-- end if;
-- if (a2_abs_xy_next_cycle'event) then
--if (set_clk'event and set_clk = '1' and res_n = '1') then\r
if (res_n = '0') then\r
- --nothing...\r
+ --pc l/h is reset vector.\r
+ pcl_cmd <= "1110";\r
+ pch_cmd <= "1110";\r
+ next_cycle <= R0;\r
elsif (rising_edge(set_clk)) then\r
d_print(string'("-"));
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE de1_nes.vwf\r
set_global_assignment -name VHDL_FILE mem/prg_rom.vhd\r
set_global_assignment -name VHDL_FILE mem/ram.vhd\r
+set_global_assignment -name VHDL_FILE ppu/ppu_registers.vhd\r
+set_global_assignment -name VHDL_FILE cpu/cpu_registers.vhd\r
+set_global_assignment -name VHDL_FILE clock/clock_divider.vhd\r
set_global_assignment -name VHDL_FILE ppu/ppu.vhd\r
set_global_assignment -name VHDL_FILE ppu/render.vhd\r
-set_global_assignment -name VHDL_FILE cpu/mos6502.vhd\r
set_global_assignment -name VHDL_FILE cpu/decoder.vhd\r
set_global_assignment -name VHDL_FILE cpu/alu.vhd\r
-set_global_assignment -name VHDL_FILE ppu/ppu_registers.vhd\r
-set_global_assignment -name VHDL_FILE cpu/cpu_registers.vhd\r
-set_global_assignment -name VHDL_FILE clock/clock_divider.vhd\r
+set_global_assignment -name VHDL_FILE cpu/mos6502.vhd\r
set_global_assignment -name VHDL_FILE address_decoder.vhd\r
set_global_assignment -name VHDL_FILE de1_nes.vhd\r
set_global_assignment -name VECTOR_WAVEFORM_FILE de1_nes.vwf
\ No newline at end of file
clock_inst : clock_divider port map \r
(base_clk, rst_n, cpu_clk, ppu_clk, vga_clk);\r
\r
--- --mos 6502 cpu instance\r
--- cpu_inst : mos6502 generic map (data_size, addr_size) \r
--- port map (cpu_clk, rdy, rst_n, irq_n, nmi_n, dbe, r_nw, \r
--- phi1, phi2, addr, d_io);\r
+ --mos 6502 cpu instance\r
+ cpu_inst : mos6502 generic map (data_size, addr_size) \r
+ port map (cpu_clk, rdy, rst_n, irq_n, nmi_n, dbe, r_nw, \r
+ phi1, phi2, addr, d_io);\r
\r
addr_dec_inst : address_decoder generic map (addr_size, data_size) \r
port map (phi2, r_nw, addr, d_io, ppu_ce_n);\r
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.conv_integer;
-use ieee.std_logic_arith.conv_std_logic_vector;
+--use ieee.std_logic_arith.conv_std_logic_vector;\r
+use ieee.numeric_std.to_unsigned;\r
use std.textio.all;
--asyncronous rom
constant ROM_TACE : time := 100 ns; --output enable access time
constant ROM_TOH : time := 10 ns; --output hold time
---function is called only once at the array initialize.
-function rom_fill return rom_array is
- type binary_file is file of character;
- FILE nes_file : binary_file OPEN read_mode IS "rom-file.nes" ;
- variable read_data : character;
- variable i : integer;
- variable out_line : line;
- variable ret : rom_array;
- begin
- --skip first 16 bit data(NES cardridge header part.)
- for i in 0 to 15 loop
- read(nes_file, read_data);
- end loop;
-
- for i in ret'range loop
- read(nes_file, read_data);
- ret(i) :=
- conv_std_logic_vector(character'pos(read_data), 8);
- end loop;
- write(out_line, string'("file load success."));
- writeline(output, out_line);
- return ret;
- end rom_fill;
+----function is called only once at the array initialize.
+--function rom_fill return rom_array is
+-- type binary_file is file of character;
+-- FILE nes_file : binary_file OPEN read_mode IS "rom-file.nes" ;
+-- variable read_data : character;
+-- variable i : integer;
+-- variable out_line : line;
+-- variable ret : rom_array;
+-- begin
+-- --skip first 16 bit data(NES cardridge header part.)
+-- for i in 0 to 15 loop
+-- read(nes_file, read_data);
+-- end loop;
+--
+-- for i in ret'range loop
+-- read(nes_file, read_data);
+-- ret(i) :=
+-- conv_std_logic_vector(character'pos(read_data), 8);
+-- end loop;
+-- write(out_line, string'("file load success."));
+-- writeline(output, out_line);
+-- return ret;
+-- end rom_fill;
+\r
+ function init_rom\r
+ return rom_array is \r
+ variable tmp : rom_array := (others => (others => '0'));\r
+ begin \r
+ for addr_pos in 0 to 2**abus_size - 1 loop \r
+ -- Initialize each address with the address itself\r
+ tmp(addr_pos) := std_logic_vector(to_unsigned(addr_pos, dbus_size));\r
+ end loop;\r
+ return tmp;\r
+ end init_rom; \r
+\r
+ -- Declare the ROM signal and specify a default value. Quartus II\r
+ -- will create a memory initialization file (.mif) based on the \r
+ -- default value.\r
--itinialize with the rom_fill function.
-constant p_rom : rom_array := rom_fill;
+--constant p_rom : rom_array := rom_fill;\r
+signal p_rom : rom_array := init_rom;\r
+\r
+attribute ram_init_file : string;\r
+attribute ram_init_file of p_rom : signal is "sample1-prg.hex11111";\r
+\r
+\r
begin
architecture rtl of ls373 is
-component latch
+component data_latch
generic (
dsize : integer := 8
);
signal q_out : std_logic_vector (dsize - 1 downto 0);
begin
- ls373_inst : latch generic map (dsize)
+ ls373_inst : data_latch generic map (dsize)
port map (c, d, q_out);
tsb_inst : tri_state_buffer generic map (dsize)
port map (oc_n, q_out, q);
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