de1_nes/cpu/decoder.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_arith.conv_std_logic_vector;
   4 use ieee.std_logic_unsigned.conv_integer;
   5
   6 entity decoder is
   7     generic (dsize : integer := 8);
   8     port (  set_clk         : in std_logic;
   9             trig_clk        : in std_logic;
  10             res_n           : in std_logic;
  11             irq_n           : in std_logic;
  12             nmi_n           : in std_logic;
  13             rdy             : in std_logic;
  14             instruction     : in std_logic_vector (dsize - 1 downto 0);
  15             exec_cycle      : in std_logic_vector (5 downto 0);
  16             next_cycle      : out std_logic_vector (5 downto 0);
  17             status_reg      : inout std_logic_vector (dsize - 1 downto 0);
  18             inst_we_n       : out std_logic;
  19             ad_oe_n         : out std_logic;
  20             dbuf_int_oe_n   : out std_logic;
  21             dl_al_we_n      : out std_logic;
  22             dl_ah_we_n      : out std_logic;
  23             dl_al_oe_n      : out std_logic;
  24             dl_ah_oe_n      : out std_logic;
  25             dl_dh_oe_n      : out std_logic;
  26             pcl_inc_n       : out std_logic;
  27             pch_inc_n       : out std_logic;
  28             pcl_cmd         : out std_logic_vector(3 downto 0);
  29             pch_cmd         : out std_logic_vector(3 downto 0);
  30             sp_cmd          : out std_logic_vector(3 downto 0);
  31             sp_oe_n         : out std_logic;
  32             sp_push_n       : out std_logic;
  33             sp_pop_n        : out std_logic;
  34             acc_cmd         : out std_logic_vector(3 downto 0);
  35             x_cmd           : out std_logic_vector(3 downto 0);
  36             y_cmd           : out std_logic_vector(3 downto 0);
  37             abs_xy_n        : out std_logic;
  38             ea_carry        : in  std_logic;
  39             pg_next_n       : out std_logic;
  40             zp_n            : out std_logic;
  41             zp_xy_n         : out std_logic;
  42             rel_calc_n      : out std_logic;
  43             indir_n         : out std_logic;
  44             indir_x_n       : out std_logic;
  45             indir_y_n       : out std_logic;
  46             arith_en_n      : out std_logic;
  47             stat_dec_oe_n   : out std_logic;
  48             stat_bus_oe_n   : out std_logic;
  49             stat_set_flg_n  : out std_logic;
  50             stat_flg        : out std_logic;
  51             stat_bus_all_n  : out std_logic;
  52             stat_bus_nz_n   : out std_logic;
  53             stat_alu_we_n   : out std_logic;
  54             r_vec_oe_n      : out std_logic;
  55             n_vec_oe_n      : out std_logic;
  56             i_vec_oe_n      : out std_logic;
  57             r_nw            : out std_logic
  58             ;---for parameter check purpose!!!
  59             check_bit     : out std_logic_vector(1 to 5)
  60         );
  61 end decoder;
  62
  63 architecture rtl of decoder is
  64
  65 component d_flip_flop_bit
  66     port (
  67             clk     : in std_logic;
  68             res_n   : in std_logic;
  69             set_n   : in std_logic;
  70             we_n    : in std_logic;
  71             d       : in std_logic;
  72             q       : out std_logic
  73         );
  74 end component;
  75
  76 procedure d_print(msg : string) is
  77 use std.textio.all;
  78 --use ieee.std_logic_textio.all;
  79 variable out_l : line;
  80 begin
  81 --    write(out_l, msg);
  82 --    writeline(output, out_l);
  83 end  procedure;
  84
  85 ---ival : 0x0000 - 0xffff
  86 function conv_hex8(ival : integer) return string is
  87 variable tmp1, tmp2 : integer;
  88 variable hex_chr: string (1 to 16) := "0123456789abcdef";
  89 begin
  90     tmp2 := (ival mod 16 ** 2) / 16 ** 1;
  91     tmp1 := ival mod 16 ** 1;
  92     return hex_chr(tmp2 + 1) & hex_chr(tmp1 + 1);
  93 end;
  94
  95 --cycle bit format
  96 -- bit 5    : pcl increment carry flag
  97 -- bit 4,3  : cycle type: 00 normal, 01 reset , 10 nmi, 11 irq
  98 -- bit 2-0  : cycle
  99
 100 --00xxx : exec cycle : T0 > T1 > T2 > T3 > T4 > T5 > T6 > T0
 101 constant T0 : std_logic_vector (5 downto 0) := "000000";
 102 constant T1 : std_logic_vector (5 downto 0) := "000001";
 103 constant T2 : std_logic_vector (5 downto 0) := "000010";
 104 constant T3 : std_logic_vector (5 downto 0) := "000011";
 105 constant T4 : std_logic_vector (5 downto 0) := "000100";
 106 constant T5 : std_logic_vector (5 downto 0) := "000101";
 107 constant T6 : std_logic_vector (5 downto 0) := "000110";
 108
 109 --01xxx : reset cycle : R0 > R1 > R2 > R3 > R4 > R5 > T0
 110 constant R0 : std_logic_vector (5 downto 0) := "001000";
 111 constant R1 : std_logic_vector (5 downto 0) := "001001";
 112 constant R2 : std_logic_vector (5 downto 0) := "001010";
 113 constant R3 : std_logic_vector (5 downto 0) := "001011";
 114 constant R4 : std_logic_vector (5 downto 0) := "001100";
 115 constant R5 : std_logic_vector (5 downto 0) := "001101";
 116
 117 --10xxx : nmi cycle : T0 > N1 > N2 > N3 > N4 > N5 > T0
 118 constant N1 : std_logic_vector (5 downto 0) := "010001";
 119 constant N2 : std_logic_vector (5 downto 0) := "010010";
 120 constant N3 : std_logic_vector (5 downto 0) := "010011";
 121 constant N4 : std_logic_vector (5 downto 0) := "010100";
 122 constant N5 : std_logic_vector (5 downto 0) := "010101";
 123
 124 --11xxx : irq cycle : T0 > I1 > I2 > I3 > I4 > I5 > T0
 125 constant I1 : std_logic_vector (5 downto 0) := "011001";
 126 constant I2 : std_logic_vector (5 downto 0) := "011010";
 127 constant I3 : std_logic_vector (5 downto 0) := "011011";
 128 constant I4 : std_logic_vector (5 downto 0) := "011100";
 129 constant I5 : std_logic_vector (5 downto 0) := "011101";
 130
 131 constant ERROR_CYCLE : std_logic_vector (5 downto 0) := "111111";
 132
 133 -- SR Flags (bit 7 to bit 0):
 134 --  7   N   ....    Negative
 135 --  6   V   ....    Overflow
 136 --  5   -   ....    ignored
 137 --  4   B   ....    Break
 138 --  3   D   ....    Decimal (use BCD for arithmetics)
 139 --  2   I   ....    Interrupt (IRQ disable)
 140 --  1   Z   ....    Zero
 141 --  0   C   ....    Carry
 142 constant st_N : integer := 7;
 143 constant st_V : integer := 6;
 144 constant st_B : integer := 4;
 145 constant st_D : integer := 3;
 146 constant st_I : integer := 2;
 147 constant st_Z : integer := 1;
 148 constant st_C : integer := 0;
 149
 150 ---for pch_inc_n.
 151 signal pch_inc_input : std_logic;
 152
 153 -- page boundary handling
 154 signal a2_abs_xy_next_cycle     : std_logic_vector (5 downto 0);
 155 signal a2_indir_y_next_cycle    : std_logic_vector (5 downto 0);
 156 signal a58_branch_next_cycle    : std_logic_vector (5 downto 0);
 157 signal wait_a2_abs_xy_next      : std_logic;
 158 signal wait_a2_indir_y_next     : std_logic;
 159 signal wait_a58_branch_next     : std_logic;
 160
 161 begin
 162
 163     ---pc page next is connected to top bit of exec_cycle
 164     pch_inc_input <= not exec_cycle(5);
 165     pch_inc_reg : d_flip_flop_bit
 166             port map(set_clk, '1', '1', '0', pch_inc_input, pch_inc_n);
 167
 168     a2_abs_xy_next_cycle <= T4 when ea_carry = '1' else
 169                     T0;
 170     a2_indir_y_next_cycle <= T5 when ea_carry = '1' else
 171                     T0;
 172     a58_branch_next_cycle <= T3 when ea_carry = '1' else
 173                     T0;
 174
 175     main_p : process (set_clk, res_n, nmi_n,
 176                      a2_abs_xy_next_cycle, a2_indir_y_next_cycle, a58_branch_next_cycle)
 177 \r
 178 ---for nmi handling\r
 179 variable nmi_handled_n : std_logic;\r
 180 \r
 181
 182 -------------------------------------------------------------
 183 -------------------------------------------------------------
 184 ----------------------- comon routines ----------------------
 185 -------------------------------------------------------------
 186 -------------------------------------------------------------
 187
 188 ----------gate_cmd format
 189 ------3 : front port oe_n
 190 ------2 : front port we_n
 191 ------1 : back port oe_n
 192 ------0 : back port we_n
 193 procedure front_oe (signal cmd : out std_logic_vector(3 downto 0);
 194     val : in std_logic) is
 195 begin
 196     cmd(3) <= val;
 197 end;
 198 procedure front_we (signal cmd : out std_logic_vector(3 downto 0);
 199     val : in std_logic) is
 200 begin
 201     cmd(2) <= val;
 202 end;
 203 procedure back_oe (signal cmd : out std_logic_vector(3 downto 0);
 204     val : in std_logic) is
 205 begin
 206     cmd(1) <= val;
 207 end;
 208 procedure back_we (signal cmd : out std_logic_vector(3 downto 0);
 209     val : in std_logic) is
 210 begin
 211     cmd(0) <= val;
 212 end;
 213
 214 procedure fetch_next is
 215 begin
 216     pcl_inc_n <= '0';
 217     back_oe(pcl_cmd, '0');
 218     back_oe(pch_cmd, '0');
 219     back_we(pcl_cmd, '0');
 220     back_we(pch_cmd, '1');
 221 end procedure;
 222
 223 procedure fetch_stop is
 224 begin
 225     pcl_inc_n <= '1';
 226     back_oe(pcl_cmd, '1');
 227     back_oe(pch_cmd, '1');
 228     back_we(pcl_cmd, '1');
 229 end procedure;
 230
 231 procedure read_status is
 232 begin
 233     status_reg <= (others => 'Z');
 234     stat_dec_oe_n <= '0';
 235 end  procedure;
 236
 237 procedure disable_pins is
 238 begin
 239     --disable the last opration pins.
 240     dbuf_int_oe_n <= '1';
 241     dl_al_we_n <= '1';
 242     dl_ah_we_n <= '1';
 243     dl_ah_oe_n <= '1';
 244     dl_dh_oe_n <= '1';
 245     sp_cmd <= "1111";
 246     sp_oe_n <= '1';
 247     sp_push_n <= '1';
 248     sp_pop_n <= '1';
 249     acc_cmd <= "1111";
 250     x_cmd <= "1111";
 251     y_cmd <= "1111";
 252
 253     abs_xy_n <= '1';
 254     pg_next_n <= '1';
 255     zp_n <= '1';
 256     zp_xy_n <= '1';
 257     rel_calc_n <= '1';
 258     indir_n <= '1';
 259     indir_x_n <= '1';
 260     indir_y_n <= '1';
 261     arith_en_n <= '1';
 262
 263     read_status;
 264     stat_bus_oe_n <= '1';
 265     stat_set_flg_n <= '1';
 266     stat_flg <= '1';
 267     stat_bus_all_n <= '1';
 268     stat_bus_nz_n <= '1';
 269     stat_alu_we_n <= '1';
 270
 271     r_vec_oe_n <= '1';
 272     n_vec_oe_n <= '1';
 273     i_vec_oe_n <= '1';
 274
 275     wait_a2_abs_xy_next <= '0';
 276     wait_a2_indir_y_next <= '0';
 277     wait_a58_branch_next <= '0';
 278 end  procedure;
 279
 280 procedure fetch_inst (inc_pcl : in std_logic) is
 281 begin
 282     if instruction = conv_std_logic_vector(16#4c#, dsize) then
 283         --if prior cycle is jump instruction,
 284         --fetch opcode from where the latch is pointing to.
 285
 286         --latch > al.
 287         dl_al_oe_n <= '0';
 288         pcl_cmd <= "1110";
 289     else
 290         --fetch opcode and pcl increment.
 291         pcl_cmd <= "1100";
 292         dl_al_oe_n <= '1';
 293     end if;
 294
 295     ad_oe_n <= '0';
 296     pch_cmd <= "1101";
 297     inst_we_n <= '0';
 298     pcl_inc_n <= inc_pcl;
 299     r_nw <= '1';
 300
 301     d_print(string'("fetch 1"));
 302 end  procedure;
 303
 304 ---T0 cycle routine
 305 ---(along with the page boundary condition, the last
 306 ---cycle is bypassed and slided to T0.)
 307 procedure t0_cycle is
 308 begin
 309     disable_pins;
 310     if (nmi_n = '0' and nmi_handled_n = '1') then
 311         --start nmi handling...
 312         fetch_inst('1');
 313         next_cycle <= N1;
 314     else
 315         fetch_inst('0');
 316         next_cycle <= T1;
 317     end if;
 318 end  procedure;
 319
 320 ---common routine for single byte instruction.
 321 procedure single_inst is
 322 begin
 323     fetch_stop;
 324     next_cycle <= T0;
 325 end  procedure;
 326
 327 procedure fetch_imm is
 328 begin
 329     d_print("immediate");
 330     fetch_next;
 331     --send data from data bus buffer.
 332     --receiver is instruction dependent.
 333     dbuf_int_oe_n <= '0';
 334     next_cycle <= T0;
 335 end  procedure;
 336
 337 procedure set_nz_from_bus is
 338 begin
 339     --status register n/z bit update.
 340     stat_bus_nz_n <= '0';
 341 end  procedure;
 342
 343 procedure set_zc_from_alu is
 344 begin
 345     --status register n/z bit update.
 346     stat_alu_we_n <= '0';
 347     stat_dec_oe_n <= '1';
 348     status_reg <= "00000011";
 349 end  procedure;
 350
 351 procedure set_nz_from_alu is
 352 begin
 353     --status register n/z/c bit update.
 354     stat_alu_we_n <= '0';
 355     stat_dec_oe_n <= '1';
 356     status_reg <= "10000010";
 357 end  procedure;
 358
 359 procedure set_nzc_from_alu is
 360 begin
 361     --status register n/z/c bit update.
 362     stat_alu_we_n <= '0';
 363     stat_dec_oe_n <= '1';
 364     status_reg <= "10000011";
 365 end  procedure;
 366
 367 procedure set_nvz_from_alu is
 368 begin
 369     --status register n/z/v bit update.
 370     stat_alu_we_n <= '0';
 371     stat_dec_oe_n <= '1';
 372     status_reg <= "11000010";
 373 end  procedure;
 374
 375 procedure set_nvzc_from_alu is
 376 begin
 377     stat_alu_we_n <= '0';
 378     stat_dec_oe_n <= '1';
 379     status_reg <= "11000011";
 380 end  procedure;
 381
 382 --flag on/off instruction
 383 procedure set_flag (int_flg : in integer; val : in std_logic) is
 384 begin
 385     stat_dec_oe_n <= '1';
 386     stat_set_flg_n <= '0';
 387     --specify which to set.
 388     status_reg(7 downto int_flg + 1)
 389         <= (others =>'0');
 390     status_reg(int_flg - 1 downto 0)
 391         <= (others =>'0');
 392     status_reg(int_flg) <= '1';
 393     stat_flg <= val;
 394 end  procedure;
 395
 396 --for sec/clc
 397 procedure set_flag0 (val : in std_logic) is
 398 begin
 399     stat_dec_oe_n <= '1';
 400     stat_set_flg_n <= '0';
 401     status_reg <= "00000001";
 402     stat_flg <= val;
 403 end  procedure;
 404
 405 procedure fetch_low is
 406 begin
 407     d_print("fetch low 2");
 408     --fetch next opcode (abs low).
 409     fetch_next;
 410     --latch abs low data.
 411     dbuf_int_oe_n <= '0';
 412     dl_al_we_n <= '0';
 413     next_cycle <= T2;
 414 end  procedure;
 415
 416 procedure abs_fetch_high is
 417 begin
 418     d_print("abs (xy) 3");
 419     dl_al_we_n <= '1';
 420
 421     --latch abs hi data.
 422     fetch_next;
 423     dbuf_int_oe_n <= '0';
 424     dl_ah_we_n <= '0';
 425     next_cycle <= T3;
 426 end  procedure;
 427
 428 procedure abs_latch_out is
 429 begin
 430     --d_print("abs 4");
 431     fetch_stop;
 432     dl_ah_we_n <= '1';
 433
 434     --latch > al/ah.
 435     dl_al_oe_n <= '0';
 436     dl_ah_oe_n <= '0';
 437 end  procedure;
 438
 439 procedure ea_x_out is
 440 begin
 441     -----calucurate and output effective addr
 442     back_oe(x_cmd, '0');
 443     abs_xy_n <= '0';
 444 end  procedure;
 445
 446 procedure ea_y_out is
 447 begin
 448     back_oe(y_cmd, '0');
 449     abs_xy_n <= '0';
 450 end  procedure;
 451
 452 --A.2. internal execution on memory data
 453
 454 procedure a2_zp is
 455 begin
 456     if exec_cycle = T1 then
 457         fetch_low;
 458     elsif exec_cycle = T2 then
 459         fetch_stop;
 460         dbuf_int_oe_n <= '0';
 461         dl_al_we_n <= '1';
 462
 463         --calc zp.
 464         dl_al_oe_n <= '0';
 465         zp_n <= '0';
 466         next_cycle <= T0;
 467     end if;
 468 end  procedure;
 469
 470 procedure a2_abs is
 471 begin
 472     if exec_cycle = T1 then
 473         fetch_low;
 474     elsif exec_cycle = T2 then
 475         abs_fetch_high;
 476     elsif exec_cycle = T3 then
 477         abs_latch_out;
 478         dbuf_int_oe_n <= '0';
 479         next_cycle <= T0;
 480     end if;
 481 end  procedure;
 482
 483 procedure a2_page_next is
 484 begin
 485     --close open gate if page boundary crossed.
 486     back_we(acc_cmd, '1');
 487     front_we(acc_cmd, '1');
 488     front_we(x_cmd, '1');
 489     front_we(y_cmd, '1');
 490     stat_alu_we_n <= '1';
 491 end  procedure;
 492
 493 procedure a2_abs_xy (is_x : in boolean) is
 494 begin
 495     if exec_cycle = T1 then
 496         fetch_low;
 497     elsif exec_cycle = T2 then
 498         abs_fetch_high;
 499     elsif exec_cycle = T3 then
 500         --ea calc & lda
 501         pg_next_n <= '1';
 502         abs_latch_out;
 503         if (is_x = true) then
 504             ea_x_out;
 505         else
 506             ea_y_out;
 507         end if;
 508         dbuf_int_oe_n <= '0';
 509
 510         wait_a2_abs_xy_next <= '1';
 511         next_cycle <= a2_abs_xy_next_cycle;
 512         d_print("absx step 1");
 513     elsif exec_cycle = T4 then
 514         --case page boundary crossed.
 515         --redo inst.
 516         d_print("absx 5 (page boudary crossed.)");
 517         --next page.
 518         pg_next_n <= not ea_carry;
 519         next_cycle <= T0;
 520     end if;
 521 end  procedure;
 522
 523 procedure a2_zp_xy (is_x : in boolean) is
 524 begin
 525     if exec_cycle = T1 then
 526         fetch_low;
 527     elsif exec_cycle = T2 then
 528         fetch_stop;
 529         --output BAL only
 530         dbuf_int_oe_n <= '0';
 531         dl_al_we_n <= '1';
 532
 533         --calc zp.
 534         dl_al_oe_n <= '0';
 535         zp_n <= '0';
 536         next_cycle <= T3;
 537     elsif exec_cycle = T3 then
 538         --t3 zp, xy
 539         zp_xy_n <= '0';
 540         if (is_x = true) then
 541             back_oe(x_cmd, '0');
 542         else
 543             back_oe(y_cmd, '0');
 544         end if;
 545         next_cycle <= T0;
 546     end if;
 547 end  procedure;
 548
 549 procedure a2_indir_y is
 550 begin
 551     if exec_cycle = T1 then
 552         fetch_low;
 553         --get IAL
 554         dl_al_we_n <= '0';
 555
 556     elsif exec_cycle = T2 then
 557         fetch_stop;
 558         dl_al_we_n <= '1';
 559
 560         ---address is 00:IAL
 561         --output BAL @IAL
 562         indir_y_n <= '0';
 563         dl_al_oe_n <= '0';
 564         dbuf_int_oe_n <= '0';
 565         next_cycle <= T3;
 566
 567     elsif exec_cycle = T3 then
 568         indir_y_n <= '0';
 569         dl_al_oe_n <= '0';
 570         --output BAH @IAL+1
 571         dbuf_int_oe_n <= '0';
 572         next_cycle <= T4;
 573
 574     elsif exec_cycle = T4 then
 575         dl_al_oe_n <= '1';
 576         dbuf_int_oe_n <= '1';
 577
 578         --add index y.
 579         pg_next_n <= '1';
 580         back_oe(y_cmd, '0');
 581         indir_y_n <= '0';
 582         dbuf_int_oe_n <= '0';
 583
 584         wait_a2_indir_y_next <= '1';
 585         next_cycle <= a2_indir_y_next_cycle;
 586     elsif exec_cycle = T5 then
 587         --case page boundary crossed.
 588         --redo inst.
 589         d_print("(indir), y (page boudary crossed.)");
 590         --next page.
 591         pg_next_n <= not ea_carry;
 592         next_cycle <= T0;
 593     end if;
 594 end  procedure;
 595
 596 --A.3. store operation.
 597
 598 procedure a3_zp is
 599 begin
 600     if exec_cycle = T1 then
 601         fetch_low;
 602     elsif exec_cycle = T2 then
 603         fetch_stop;
 604         dbuf_int_oe_n <= '1';
 605         dl_al_we_n <= '1';
 606
 607         --calc zp.
 608         dl_al_oe_n <= '0';
 609         zp_n <= '0';
 610         r_nw <= '0';
 611         next_cycle <= T0;
 612     end if;
 613 end  procedure;
 614
 615 procedure a3_zp_xy (is_x : in boolean) is
 616 begin
 617     if exec_cycle = T1 then
 618         fetch_low;
 619     elsif exec_cycle = T2 then
 620         fetch_stop;
 621         dbuf_int_oe_n <= '1';
 622         dl_al_we_n <= '1';
 623
 624         --calc zp.
 625         dl_al_oe_n <= '0';
 626         zp_n <= '0';
 627         next_cycle <= T3;
 628     elsif exec_cycle = T3 then
 629         --calc zp + index.
 630         dl_al_oe_n <= '0';
 631         zp_n <= '0';
 632         zp_xy_n <= '0';
 633         if (is_x = true) then
 634             back_oe(x_cmd, '0');
 635         else
 636             back_oe(y_cmd, '0');
 637         end if;
 638
 639         --write data
 640         r_nw <= '0';
 641         next_cycle <= T0;
 642     end if;
 643 end  procedure;
 644
 645 procedure a3_abs is
 646 begin
 647     if exec_cycle = T1 then
 648         fetch_low;
 649     elsif exec_cycle = T2 then
 650         abs_fetch_high;
 651     elsif exec_cycle = T3 then
 652         abs_latch_out;
 653         dbuf_int_oe_n <= '1';
 654         r_nw <= '0';
 655         next_cycle <= T0;
 656     end if;
 657 end  procedure;
 658
 659 procedure a3_abs_xy (is_x : in boolean) is
 660 begin
 661     if exec_cycle = T1 then
 662         fetch_low;
 663     elsif exec_cycle = T2 then
 664         abs_fetch_high;
 665     elsif exec_cycle = T3 then
 666         --ea calc & lda
 667         pg_next_n <= '1';
 668         abs_latch_out;
 669         dbuf_int_oe_n <= '1';
 670         if (is_x = true) then
 671             ea_x_out;
 672         else
 673             ea_y_out;
 674         end if;
 675         next_cycle <= T4;
 676     elsif exec_cycle = T4 then
 677         pg_next_n <= not ea_carry;
 678         abs_latch_out;
 679         if (is_x = true) then
 680             ea_x_out;
 681         else
 682             ea_y_out;
 683         end if;
 684         r_nw <= '0';
 685         next_cycle <= T0;
 686     end if;
 687 end  procedure;
 688
 689
 690 procedure a3_indir_y is
 691 begin
 692     if exec_cycle = T1 then
 693         fetch_low;
 694         --get IAL
 695         dl_al_we_n <= '0';
 696
 697     elsif exec_cycle = T2 then
 698         fetch_stop;
 699         dl_al_we_n <= '1';
 700
 701         ---address is 00:IAL
 702         --output BAL @IAL
 703         indir_y_n <= '0';
 704         dl_al_oe_n <= '0';
 705         dbuf_int_oe_n <= '0';
 706         next_cycle <= T3;
 707
 708     elsif exec_cycle = T3 then
 709         indir_y_n <= '0';
 710         dl_al_oe_n <= '0';
 711         --output BAH @IAL+1
 712         dbuf_int_oe_n <= '0';
 713         next_cycle <= T4;
 714
 715     elsif exec_cycle = T4 then
 716         dl_al_oe_n <= '1';
 717         dbuf_int_oe_n <= '1';
 718
 719         --add index y.
 720         pg_next_n <= '1';
 721         back_oe(y_cmd, '0');
 722         indir_y_n <= '0';
 723         next_cycle <= T5;
 724
 725     elsif exec_cycle = T5 then
 726         --page handling.
 727         back_oe(y_cmd, '1');
 728         indir_y_n <= '0';
 729         pg_next_n <= not ea_carry;
 730         r_nw <= '0';
 731         next_cycle <= T0;
 732     end if;
 733 end  procedure;
 734
 735
 736 ---A.4. read-modify-write operation
 737
 738 procedure a4_zp is
 739 begin
 740     if exec_cycle = T1 then
 741         fetch_low;
 742     elsif exec_cycle = T2 then
 743         fetch_stop;
 744         dbuf_int_oe_n <= '1';
 745         dl_al_we_n <= '1';
 746
 747         --t2 cycle only read
 748         dl_al_oe_n <= '0';
 749         zp_n <= '0';
 750         next_cycle <= T3;
 751     elsif exec_cycle = T3 then
 752         dl_al_oe_n <= '0';
 753         zp_n <= '0';
 754         --keep data in the alu reg.
 755         arith_en_n <= '0';
 756         dbuf_int_oe_n <= '0';
 757         next_cycle <= T4;
 758     elsif exec_cycle = T4 then
 759         dbuf_int_oe_n <= '1';
 760
 761         --t5 cycle writes modified value.
 762         dl_al_oe_n <= '0';
 763         zp_n <= '0';
 764         r_nw <= '0';
 765         arith_en_n <= '0';
 766         next_cycle <= T0;
 767     end if;
 768 end  procedure;
 769
 770 procedure a4_zp_x is
 771 begin
 772     if exec_cycle = T1 then
 773         fetch_low;
 774     elsif exec_cycle = T2 then
 775         fetch_stop;
 776         dbuf_int_oe_n <= '1';
 777         dl_al_we_n <= '1';
 778
 779         --t2 cycle read bal only.
 780         dl_al_oe_n <= '0';
 781         zp_n <= '0';
 782         next_cycle <= T3;
 783     elsif exec_cycle = T3 then
 784         --t3 cycle read bal + x
 785         dl_al_oe_n <= '0';
 786         zp_n <= '0';
 787         zp_xy_n <= '0';
 788         back_oe(x_cmd, '0');
 789         next_cycle <= T4;
 790     elsif exec_cycle = T4 then
 791         dl_al_oe_n <= '0';
 792         zp_n <= '0';
 793         zp_xy_n <= '0';
 794         back_oe(x_cmd, '0');
 795
 796         --keep data in the alu reg.
 797         arith_en_n <= '0';
 798         dbuf_int_oe_n <= '0';
 799         next_cycle <= T5;
 800     elsif exec_cycle = T5 then
 801         dbuf_int_oe_n <= '1';
 802
 803         --t5 cycle writes modified value.
 804         dl_al_oe_n <= '0';
 805         zp_n <= '0';
 806         zp_xy_n <= '0';
 807         back_oe(x_cmd, '0');
 808         r_nw <= '0';
 809         arith_en_n <= '0';
 810         next_cycle <= T0;
 811     end if;
 812 end  procedure;
 813
 814
 815 procedure a4_abs is
 816 begin
 817     if exec_cycle = T1 then
 818         fetch_low;
 819     elsif exec_cycle = T2 then
 820         abs_fetch_high;
 821     elsif exec_cycle = T3 then
 822         --T3 cycle do nothing.
 823         abs_latch_out;
 824         next_cycle <= T4;
 825     elsif exec_cycle = T4 then
 826         abs_latch_out;
 827
 828         --t4 cycle save data in the alu register only.
 829         --hardware maunual says write original data,
 830         --but this implementation doesn't write because bus shortage....
 831         arith_en_n <= '0';
 832         next_cycle <= T5;
 833     elsif exec_cycle = T5 then
 834         dbuf_int_oe_n <= '1';
 835
 836         --t5 cycle writes modified value.
 837         r_nw <= '0';
 838         arith_en_n <= '0';
 839         next_cycle <= T0;
 840     end if;
 841 end  procedure;
 842
 843 procedure a4_abs_x is
 844 begin
 845     if exec_cycle = T1 then
 846         fetch_low;
 847     elsif exec_cycle = T2 then
 848         abs_fetch_high;
 849     elsif exec_cycle = T3 then
 850         --T3 cycle discarded.
 851         pg_next_n <= '1';
 852         abs_latch_out;
 853         ea_x_out;
 854         dbuf_int_oe_n <= '0';
 855         next_cycle <= T4;
 856
 857     elsif exec_cycle = T4 then
 858         --t4 cycle fetch only.
 859         abs_latch_out;
 860         ea_x_out;
 861         pg_next_n <= not ea_carry;
 862         next_cycle <= T5;
 863
 864     elsif exec_cycle = T5 then
 865         --t4 cycle redo fetch and save data in the alu register only.
 866         arith_en_n <= '0';
 867         next_cycle <= T6;
 868
 869     elsif exec_cycle = T6 then
 870         --t5 cycle writes modified value.
 871         r_nw <= '0';
 872         arith_en_n <= '0';
 873         dbuf_int_oe_n <= '1';
 874         next_cycle <= T0;
 875
 876     end if;
 877 end  procedure;
 878
 879
 880 -- A.5.1 push stack
 881 procedure a51_push is
 882 begin
 883     if exec_cycle = T1 then
 884         fetch_stop;
 885         next_cycle <= T2;
 886     elsif exec_cycle = T2 then
 887         back_oe(sp_cmd, '0');
 888         back_we(sp_cmd, '0');
 889         sp_push_n <= '0';
 890         sp_oe_n <= '0';
 891         r_nw <= '0';
 892         next_cycle <= T0;
 893     end if;
 894 end procedure;
 895
 896 -- A.5.2 pull stack
 897 procedure a52_pull is
 898 begin
 899     if exec_cycle = T1 then
 900         fetch_stop;
 901         next_cycle <= T2;
 902
 903     elsif exec_cycle = T2 then
 904         --stack decrement first.
 905         back_oe(sp_cmd, '0');
 906         back_we(sp_cmd, '0');
 907         sp_pop_n <= '0';
 908         sp_oe_n <= '0';
 909         next_cycle <= T3;
 910
 911     elsif exec_cycle = T3 then
 912         sp_pop_n <= '1';
 913         back_we(sp_cmd, '1');
 914
 915         ---pop data from stack.
 916         back_oe(sp_cmd, '0');
 917         sp_oe_n <= '0';
 918         dbuf_int_oe_n <= '0';
 919         next_cycle <= T0;
 920     end if;
 921 end procedure;
 922
 923
 924 -- A.5.8 branch operations
 925
 926 procedure a58_branch (int_flg : in integer; br_cond : in std_logic) is
 927 begin
 928     if exec_cycle = T1 then
 929         fetch_next;
 930         if status_reg(int_flg) = br_cond then
 931             d_print("get rel");
 932
 933             --latch rel value.
 934             dbuf_int_oe_n <= '0';
 935             dl_ah_we_n <= '0';
 936             next_cycle <= T2;
 937         else
 938             d_print("no branch");
 939             next_cycle <= T0;
 940         end if;
 941     elsif exec_cycle = T2 then
 942         d_print("rel ea");
 943         fetch_stop;
 944         dbuf_int_oe_n <= '1';
 945         dl_ah_we_n <= '1';
 946
 947         --calc relative addr.
 948         rel_calc_n <= '0';
 949         pg_next_n <= '1';
 950         dl_dh_oe_n <= '0';
 951         back_oe(pcl_cmd, '0');
 952         back_oe(pch_cmd, '0');
 953         back_we(pcl_cmd, '0');
 954
 955         wait_a58_branch_next <= '1';
 956         next_cycle <= a58_branch_next_cycle;
 957     elsif exec_cycle = T3 then
 958         d_print("page crossed.");
 959         --page crossed. adh calc.
 960         back_we(pcl_cmd, '1');
 961         back_oe(pcl_cmd, '0');
 962         back_oe(pch_cmd, '0');
 963         back_we(pch_cmd, '0');
 964         dl_dh_oe_n <= '0';
 965
 966         rel_calc_n <= '0';
 967         pg_next_n <= '0';
 968         next_cycle <= T0;
 969     end if;
 970 end  procedure;
 971
 972 -------------------------------------------------------------
 973 -------------------------------------------------------------
 974 ---------------- main state machine start.... ---------------
 975 -------------------------------------------------------------
 976 -------------------------------------------------------------
 977 \r
 978     begin
 979
 980 --        if (res_n = '0') then
 981 --            --pc l/h is reset vector.
 982 --            pcl_cmd <= "1110";
 983 --            pch_cmd <= "1110";
 984 --            next_cycle <= R0;
 985 --        elsif (res_n'event and res_n = '1') then
 986 --            pcl_cmd <= "1111";
 987 --            pch_cmd <= "1111";
 988 --        end if;
 989 --
 990 --        if (nmi_n'event and nmi_n = '1') then
 991 --            --reset nmi handle status
 992 --            nmi_handled_n := '1';
 993 --        end if;
 994
 995
 996 --        if (a2_abs_xy_next_cycle'event) then
 997 --            if (wait_a2_abs_xy_next = '1') then
 998 --                d_print("absx step 2");
 999 --                next_cycle <= a2_abs_xy_next_cycle;
1000 --                if (ea_carry = '1') then
1001 --                    a2_page_next;
1002 --                end if;
1003 --            end if;
1004 --        end if;
1005 --
1006 --        if (a2_indir_y_next_cycle'event) then
1007 --            if (wait_a2_indir_y_next = '1') then
1008 --                d_print("indir step 2");
1009 --                next_cycle <= a2_indir_y_next_cycle;
1010 --                if (ea_carry = '1') then
1011 --                    a2_page_next;
1012 --                end if;
1013 --            end if;
1014 --        end if;
1015 --
1016 --        if (a58_branch_next_cycle'event) then
1017 --            if (wait_a58_branch_next = '1') then
1018 --                d_print("branch step 2");
1019 --                next_cycle <= a58_branch_next_cycle;
1020 --                if (ea_carry = '1') then
1021 --                    a2_page_next;
1022 --                end if;
1023 --            end if;
1024 --        end if;
1025
1026         --if (set_clk'event and set_clk = '1' and res_n = '1') then\r
1027         if (res_n = '0') then\r
1028             --pc l/h is reset vector.\r
1029             pcl_cmd <= "1110";\r
1030             pch_cmd <= "1110";\r
1031             next_cycle <= R0;\r
1032                 elsif (rising_edge(set_clk)) then\r
1033             d_print(string'("-"));
1034
1035             if exec_cycle = T0 then
1036                 --cycle #1
1037                 t0_cycle;
1038
1039             elsif exec_cycle = T1 or exec_cycle = T2 or exec_cycle = T3 or
1040                 exec_cycle = T4 or exec_cycle = T5 or exec_cycle = T6 then
1041                 --execute inst.
1042
1043                 ---asyncronous page change might happen.
1044                 back_we(pch_cmd, '1');
1045
1046                 if exec_cycle = T1 then
1047                     d_print("decode and execute inst: "
1048                             & conv_hex8(conv_integer(instruction)));
1049                     --disable pin for jmp instruction
1050                     dl_al_oe_n <= '1';
1051                     back_we(pcl_cmd, '1');
1052                     front_we(pch_cmd, '1');
1053
1054                     --grab instruction register data.
1055                     inst_we_n <= '1';
1056                 end if;
1057
1058                 --imelementation is wriiten in the order of hardware manual
1059                 --appendix A.
1060
1061                 ----------------------------------------
1062                 --A.1. Single byte instruction.
1063                 ----------------------------------------
1064                 if instruction = conv_std_logic_vector(16#0a#, dsize) then
1065                     --asl acc mode.
1066                     d_print("asl");
1067                     arith_en_n <= '0';
1068                     back_oe(acc_cmd, '0');
1069                     front_we(acc_cmd, '0');
1070                     set_nzc_from_alu;
1071                     single_inst;
1072
1073                 elsif instruction = conv_std_logic_vector(16#18#, dsize) then
1074                     d_print("clc");
1075                     set_flag0 ('0');
1076                     single_inst;
1077
1078                 elsif instruction = conv_std_logic_vector(16#d8#, dsize) then
1079                     d_print("cld");
1080                     set_flag (st_D, '0');
1081                     single_inst;
1082
1083                 elsif instruction = conv_std_logic_vector(16#58#, dsize) then
1084                     d_print("cli");
1085                     set_flag (st_I, '0');
1086                     single_inst;
1087
1088                 elsif instruction = conv_std_logic_vector(16#b8#, dsize) then
1089                     d_print("clv");
1090                     set_flag (st_V, '0');
1091                     single_inst;
1092
1093                 elsif instruction = conv_std_logic_vector(16#ca#, dsize) then
1094                     d_print("dex");
1095                     arith_en_n <= '0';
1096                     back_oe(x_cmd, '0');
1097                     front_we(x_cmd, '0');
1098                     --set nz bit.
1099                     set_nz_from_bus;
1100                     single_inst;
1101
1102                 elsif instruction = conv_std_logic_vector(16#88#, dsize) then
1103                     d_print("dey");
1104                     arith_en_n <= '0';
1105                     back_oe(y_cmd, '0');
1106                     front_we(y_cmd, '0');
1107                     --set nz bit.
1108                     set_nz_from_bus;
1109                     single_inst;
1110
1111                 elsif instruction = conv_std_logic_vector(16#e8#, dsize) then
1112                     d_print("inx");
1113                     arith_en_n <= '0';
1114                     back_oe(x_cmd, '0');
1115                     front_we(x_cmd, '0');
1116                     --set nz bit.
1117                     set_nz_from_bus;
1118                     single_inst;
1119
1120                 elsif instruction = conv_std_logic_vector(16#c8#, dsize) then
1121                     d_print("iny");
1122                     arith_en_n <= '0';
1123                     back_oe(y_cmd, '0');
1124                     front_we(y_cmd, '0');
1125                     set_nz_from_bus;
1126                     single_inst;
1127
1128                 elsif instruction = conv_std_logic_vector(16#4a#, dsize) then
1129                     --lsr acc mode
1130                     d_print("lsr");
1131                     arith_en_n <= '0';
1132                     back_oe(acc_cmd, '0');
1133                     front_we(acc_cmd, '0');
1134                     set_zc_from_alu;
1135                     single_inst;
1136
1137                 elsif instruction = conv_std_logic_vector(16#ea#, dsize) then
1138                     d_print("nop");
1139                     single_inst;
1140
1141                 elsif instruction = conv_std_logic_vector(16#2a#, dsize) then
1142                     --rol acc
1143                     d_print("rol");
1144                     arith_en_n <= '0';
1145                     back_oe(acc_cmd, '0');
1146                     front_we(acc_cmd, '0');
1147                     set_nzc_from_alu;
1148                     single_inst;
1149
1150                 elsif instruction = conv_std_logic_vector(16#6a#, dsize) then
1151                     --ror acc
1152                     d_print("ror");
1153                     arith_en_n <= '0';
1154                     back_oe(acc_cmd, '0');
1155                     front_we(acc_cmd, '0');
1156                     set_nzc_from_alu;
1157                     single_inst;
1158
1159                 elsif instruction = conv_std_logic_vector(16#38#, dsize) then
1160                     d_print("sec");
1161                     set_flag0 ('1');
1162                     single_inst;
1163
1164                 elsif instruction = conv_std_logic_vector(16#f8#, dsize) then
1165                     d_print("sed");
1166                     set_flag (st_D, '1');
1167                     single_inst;
1168
1169                 elsif instruction = conv_std_logic_vector(16#78#, dsize) then
1170                     d_print("sei");
1171                     set_flag (st_I, '1');
1172                     single_inst;
1173
1174                 elsif instruction = conv_std_logic_vector(16#aa#, dsize) then
1175                     d_print("tax");
1176                     set_nz_from_bus;
1177                     single_inst;
1178                     front_oe(acc_cmd, '0');
1179                     front_we(x_cmd, '0');
1180
1181                 elsif instruction = conv_std_logic_vector(16#a8#, dsize) then
1182                     d_print("tay");
1183                     set_nz_from_bus;
1184                     single_inst;
1185                     front_oe(acc_cmd, '0');
1186                     front_we(y_cmd, '0');
1187
1188                 elsif instruction = conv_std_logic_vector(16#ba#, dsize) then
1189                     d_print("tsx");
1190                     set_nz_from_bus;
1191
1192                 elsif instruction = conv_std_logic_vector(16#8a#, dsize) then
1193                     d_print("txa");
1194                     set_nz_from_bus;
1195                     single_inst;
1196                     front_oe(x_cmd, '0');
1197                     front_we(acc_cmd, '0');
1198
1199                 elsif instruction = conv_std_logic_vector(16#9a#, dsize) then
1200                     d_print("txs");
1201                     set_nz_from_bus;
1202                     single_inst;
1203                     front_oe(x_cmd, '0');
1204                     front_we(sp_cmd, '0');
1205
1206                 elsif instruction = conv_std_logic_vector(16#98#, dsize) then
1207                     d_print("tya");
1208                     set_nz_from_bus;
1209                     single_inst;
1210                     front_oe(y_cmd, '0');
1211                     front_we(acc_cmd, '0');
1212
1213
1214
1215                 ----------------------------------------
1216                 --A.2. internal execution on memory data
1217                 ----------------------------------------
1218                 elsif instruction  = conv_std_logic_vector(16#69#, dsize) then
1219                     --imm
1220                     d_print("adc");
1221                     fetch_imm;
1222                     arith_en_n <= '0';
1223                     back_oe(acc_cmd, '0');
1224                     back_we(acc_cmd, '0');
1225                     set_nvzc_from_alu;
1226
1227                 elsif instruction  = conv_std_logic_vector(16#65#, dsize) then
1228                     --zp
1229                     d_print("adc");
1230                     a2_zp;
1231                     if exec_cycle = T2 then
1232                         arith_en_n <= '0';
1233                         back_oe(acc_cmd, '0');
1234                         back_we(acc_cmd, '0');
1235                         set_nvzc_from_alu;
1236                     end if;
1237
1238                 elsif instruction  = conv_std_logic_vector(16#75#, dsize) then
1239                     --zp, x
1240                     d_print("adc");
1241                     a2_zp_xy(true);
1242                     if exec_cycle = T3 then
1243                         arith_en_n <= '0';
1244                         back_oe(acc_cmd, '0');
1245                         back_we(acc_cmd, '0');
1246                         set_nvzc_from_alu;
1247                     end if;
1248
1249                 elsif instruction  = conv_std_logic_vector(16#6d#, dsize) then
1250                     --abs
1251                     d_print("adc");
1252                     a2_abs;
1253                     if exec_cycle = T3 then
1254                         arith_en_n <= '0';
1255                         back_oe(acc_cmd, '0');
1256                         back_we(acc_cmd, '0');
1257                         set_nvzc_from_alu;
1258                     end if;
1259
1260                 elsif instruction  = conv_std_logic_vector(16#7d#, dsize) then
1261                     --abs, x
1262                     d_print("adc");
1263                     a2_abs_xy(true);
1264                     if exec_cycle = T3 or exec_cycle = T4 then
1265                         arith_en_n <= '0';
1266                         back_oe(acc_cmd, '0');
1267                         back_we(acc_cmd, '0');
1268                         set_nvzc_from_alu;
1269                     end if;
1270
1271                 elsif instruction  = conv_std_logic_vector(16#79#, dsize) then
1272                     --abs, y
1273                     d_print("adc");
1274                     a2_abs_xy(false);
1275                     if exec_cycle = T3 or exec_cycle = T4 then
1276                         arith_en_n <= '0';
1277                         back_oe(acc_cmd, '0');
1278                         back_we(acc_cmd, '0');
1279                         set_nvzc_from_alu;
1280                     end if;
1281
1282                 elsif instruction  = conv_std_logic_vector(16#61#, dsize) then
1283                     --(indir, x)
1284                     d_print("adc");
1285
1286                 elsif instruction  = conv_std_logic_vector(16#71#, dsize) then
1287                     --(indir), y
1288                     d_print("adc");
1289                     a2_indir_y;
1290                     if exec_cycle = T4 or exec_cycle = T5 then
1291                         arith_en_n <= '0';
1292                         back_oe(acc_cmd, '0');
1293                         back_we(acc_cmd, '0');
1294                         set_nvzc_from_alu;
1295                     end if;
1296
1297                 elsif instruction  = conv_std_logic_vector(16#29#, dsize) then
1298                     --imm
1299                     d_print("and");
1300                     fetch_imm;
1301                     arith_en_n <= '0';
1302                     back_oe(acc_cmd, '0');
1303                     back_we(acc_cmd, '0');
1304                     set_nz_from_alu;
1305
1306                 elsif instruction  = conv_std_logic_vector(16#25#, dsize) then
1307                     --zp
1308                     d_print("and");
1309                     a2_zp;
1310                     if exec_cycle = T2 then
1311                         arith_en_n <= '0';
1312                         back_oe(acc_cmd, '0');
1313                         back_we(acc_cmd, '0');
1314                         set_nz_from_alu;
1315                     end if;
1316
1317                 elsif instruction  = conv_std_logic_vector(16#35#, dsize) then
1318                     --zp, x
1319                     d_print("and");
1320                     a2_zp_xy(true);
1321                     if exec_cycle = T3 then
1322                         arith_en_n <= '0';
1323                         back_oe(acc_cmd, '0');
1324                         back_we(acc_cmd, '0');
1325                         set_nz_from_alu;
1326                     end if;
1327
1328                 elsif instruction  = conv_std_logic_vector(16#2d#, dsize) then
1329                     --abs
1330                     d_print("and");
1331                     a2_abs;
1332                     if exec_cycle = T3 then
1333                         arith_en_n <= '0';
1334                         back_oe(acc_cmd, '0');
1335                         back_we(acc_cmd, '0');
1336                         set_nz_from_alu;
1337                     end if;
1338
1339                 elsif instruction  = conv_std_logic_vector(16#3d#, dsize) then
1340                     --abs, x
1341                     d_print("and");
1342                     a2_abs_xy(true);
1343                     if exec_cycle = T3 or exec_cycle = T4 then
1344                         arith_en_n <= '0';
1345                         back_oe(acc_cmd, '0');
1346                         back_we(acc_cmd, '0');
1347                         set_nz_from_alu;
1348                     end if;
1349
1350                 elsif instruction  = conv_std_logic_vector(16#39#, dsize) then
1351                     --abs, y
1352                     d_print("and");
1353                     a2_abs_xy(false);
1354                     if exec_cycle = T3 or exec_cycle = T4 then
1355                         arith_en_n <= '0';
1356                         back_oe(acc_cmd, '0');
1357                         back_we(acc_cmd, '0');
1358                         set_nz_from_alu;
1359                     end if;
1360
1361                 elsif instruction  = conv_std_logic_vector(16#21#, dsize) then
1362                     --(indir, x)
1363                     d_print("and");
1364
1365                 elsif instruction  = conv_std_logic_vector(16#31#, dsize) then
1366                     --(indir), y
1367                     d_print("and");
1368                     a2_indir_y;
1369                     if exec_cycle = T4 or exec_cycle = T5 then
1370                         arith_en_n <= '0';
1371                         back_oe(acc_cmd, '0');
1372                         back_we(acc_cmd, '0');
1373                         set_nz_from_alu;
1374                     end if;
1375
1376                 elsif instruction  = conv_std_logic_vector(16#24#, dsize) then
1377                     --zp
1378                     d_print("bit");
1379                     a2_zp;
1380                     if exec_cycle = T2 then
1381                         arith_en_n <= '0';
1382                         back_oe(acc_cmd, '0');
1383                         set_nvz_from_alu;
1384                     end if;
1385
1386                 elsif instruction  = conv_std_logic_vector(16#2c#, dsize) then
1387                     --abs
1388                     d_print("bit");
1389                     a2_abs;
1390                     if exec_cycle = T3 then
1391                         arith_en_n <= '0';
1392                         back_oe(acc_cmd, '0');
1393                         set_nvz_from_alu;
1394                     end if;
1395
1396                 elsif instruction  = conv_std_logic_vector(16#c9#, dsize) then
1397                     --imm
1398                     d_print("cmp");
1399                     fetch_imm;
1400                     arith_en_n <= '0';
1401                     back_oe(acc_cmd, '0');
1402                     set_nzc_from_alu;
1403
1404                 elsif instruction  = conv_std_logic_vector(16#c5#, dsize) then
1405                     --zp
1406                     d_print("cmp");
1407                     a2_zp;
1408                     if exec_cycle = T2 then
1409                         arith_en_n <= '0';
1410                         back_oe(acc_cmd, '0');
1411                         set_nzc_from_alu;
1412                     end if;
1413
1414                 elsif instruction  = conv_std_logic_vector(16#d5#, dsize) then
1415                     --zp, x
1416                     d_print("cmp");
1417                     a2_zp_xy(true);
1418                     if exec_cycle = T3 then
1419                         arith_en_n <= '0';
1420                         back_oe(acc_cmd, '0');
1421                         set_nzc_from_alu;
1422                     end if;
1423
1424                 elsif instruction  = conv_std_logic_vector(16#cd#, dsize) then
1425                     --abs
1426                     d_print("cmp");
1427                     a2_abs;
1428                     if exec_cycle = T3 then
1429                         arith_en_n <= '0';
1430                         back_oe(acc_cmd, '0');
1431                         set_nzc_from_alu;
1432                     end if;
1433
1434                 elsif instruction  = conv_std_logic_vector(16#dd#, dsize) then
1435                     --abs, x
1436                     d_print("cmp");
1437                     a2_abs_xy(true);
1438                     if exec_cycle = T3 or exec_cycle = T4 then
1439                         arith_en_n <= '0';
1440                         back_oe(acc_cmd, '0');
1441                         set_nzc_from_alu;
1442                     end if;
1443
1444                 elsif instruction  = conv_std_logic_vector(16#d9#, dsize) then
1445                     --abs, y
1446                     d_print("cmp");
1447                     a2_abs_xy(false);
1448                     if exec_cycle = T3 or exec_cycle = T4 then
1449                         arith_en_n <= '0';
1450                         back_oe(acc_cmd, '0');
1451                         set_nzc_from_alu;
1452                     end if;
1453
1454                 elsif instruction  = conv_std_logic_vector(16#c1#, dsize) then
1455                     --(indir, x)
1456                     d_print("cmp");
1457
1458                 elsif instruction  = conv_std_logic_vector(16#d1#, dsize) then
1459                     --(indir), y
1460                     d_print("cmp");
1461                     a2_indir_y;
1462                     if exec_cycle = T4 or exec_cycle = T5 then
1463                         arith_en_n <= '0';
1464                         back_oe(acc_cmd, '0');
1465                         set_nzc_from_alu;
1466                     end if;
1467
1468                 elsif instruction  = conv_std_logic_vector(16#e0#, dsize) then
1469                     --imm
1470                     d_print("cpx");
1471                     fetch_imm;
1472                     arith_en_n <= '0';
1473                     back_oe(x_cmd, '0');
1474                     set_nzc_from_alu;
1475
1476                 elsif instruction  = conv_std_logic_vector(16#e4#, dsize) then
1477                     --zp
1478                     d_print("cpx");
1479                     a2_zp;
1480                     if exec_cycle = T2 then
1481                         arith_en_n <= '0';
1482                         back_oe(x_cmd, '0');
1483                         set_nzc_from_alu;
1484                     end if;
1485
1486                 elsif instruction  = conv_std_logic_vector(16#ec#, dsize) then
1487                     --abs
1488                     d_print("cpx");
1489                     a2_abs;
1490                     if exec_cycle = T3 then
1491                         arith_en_n <= '0';
1492                         back_oe(x_cmd, '0');
1493                         set_nzc_from_alu;
1494                     end if;
1495
1496                 elsif instruction  = conv_std_logic_vector(16#c0#, dsize) then
1497                     --imm
1498                     d_print("cpy");
1499                     fetch_imm;
1500                     arith_en_n <= '0';
1501                     back_oe(y_cmd, '0');
1502                     set_nzc_from_alu;
1503
1504                 elsif instruction  = conv_std_logic_vector(16#c4#, dsize) then
1505                     --zp
1506                     d_print("cpy");
1507                     a2_zp;
1508                     if exec_cycle = T2 then
1509                         arith_en_n <= '0';
1510                         back_oe(y_cmd, '0');
1511                         set_nzc_from_alu;
1512                     end if;
1513
1514                 elsif instruction  = conv_std_logic_vector(16#cc#, dsize) then
1515                     --abs
1516                     d_print("cpy");
1517                     a2_abs;
1518                     if exec_cycle = T3 then
1519                         arith_en_n <= '0';
1520                         back_oe(y_cmd, '0');
1521                         set_nzc_from_alu;
1522                     end if;
1523
1524                 elsif instruction  = conv_std_logic_vector(16#49#, dsize) then
1525                     --imm
1526                     d_print("eor");
1527                     fetch_imm;
1528                     arith_en_n <= '0';
1529                     back_oe(acc_cmd, '0');
1530                     back_we(acc_cmd, '0');
1531                     set_nz_from_alu;
1532
1533                 elsif instruction  = conv_std_logic_vector(16#45#, dsize) then
1534                     --zp
1535                     d_print("eor");
1536                     a2_zp;
1537                     if exec_cycle = T2 then
1538                         arith_en_n <= '0';
1539                         back_oe(acc_cmd, '0');
1540                         back_we(acc_cmd, '0');
1541                         set_nz_from_alu;
1542                     end if;
1543
1544                 elsif instruction  = conv_std_logic_vector(16#55#, dsize) then
1545                     --zp, x
1546                     d_print("eor");
1547                     a2_zp_xy(true);
1548                     if exec_cycle = T3 then
1549                         arith_en_n <= '0';
1550                         back_oe(acc_cmd, '0');
1551                         back_we(acc_cmd, '0');
1552                         set_nz_from_alu;
1553                     end if;
1554
1555                 elsif instruction  = conv_std_logic_vector(16#4d#, dsize) then
1556                     --abs
1557                     d_print("eor");
1558                     a2_abs;
1559                     if exec_cycle = T3 then
1560                         arith_en_n <= '0';
1561                         back_oe(acc_cmd, '0');
1562                         back_we(acc_cmd, '0');
1563                         set_nz_from_alu;
1564                     end if;
1565
1566                 elsif instruction  = conv_std_logic_vector(16#5d#, dsize) then
1567                     --abs, x
1568                     d_print("eor");
1569                     a2_abs_xy(true);
1570                     if exec_cycle = T3 or exec_cycle = T4 then
1571                         arith_en_n <= '0';
1572                         back_oe(acc_cmd, '0');
1573                         back_we(acc_cmd, '0');
1574                         set_nz_from_alu;
1575                     end if;
1576
1577                 elsif instruction  = conv_std_logic_vector(16#59#, dsize) then
1578                     --abs, y
1579                     d_print("eor");
1580                     a2_abs_xy(false);
1581                     if exec_cycle = T3 or exec_cycle = T4 then
1582                         arith_en_n <= '0';
1583                         back_oe(acc_cmd, '0');
1584                         back_we(acc_cmd, '0');
1585                         set_nz_from_alu;
1586                     end if;
1587
1588                 elsif instruction  = conv_std_logic_vector(16#41#, dsize) then
1589                     --(indir, x)
1590                     d_print("eor");
1591
1592                 elsif instruction  = conv_std_logic_vector(16#51#, dsize) then
1593                     --(indir), y
1594                     d_print("eor");
1595                     a2_indir_y;
1596                     if exec_cycle = T4 or exec_cycle = T5 then
1597                         arith_en_n <= '0';
1598                         back_oe(acc_cmd, '0');
1599                         back_we(acc_cmd, '0');
1600                         set_nz_from_alu;
1601                     end if;
1602
1603                 elsif instruction  = conv_std_logic_vector(16#a9#, dsize) then
1604                     --imm
1605                     d_print("lda");
1606                     fetch_imm;
1607                     front_we(acc_cmd, '0');
1608                     set_nz_from_bus;
1609
1610                 elsif instruction  = conv_std_logic_vector(16#a5#, dsize) then
1611                     --zp
1612                     d_print("lda");
1613                     a2_zp;
1614                     if exec_cycle = T2 then
1615                         front_we(acc_cmd, '0');
1616                         set_nz_from_bus;
1617                     end if;
1618
1619                 elsif instruction  = conv_std_logic_vector(16#b5#, dsize) then
1620                     --zp, x
1621                     d_print("lda");
1622                     a2_zp_xy(true);
1623                     if exec_cycle = T3 then
1624                         front_we(acc_cmd, '0');
1625                         set_nz_from_bus;
1626                     end if;
1627
1628                 elsif instruction  = conv_std_logic_vector(16#ad#, dsize) then
1629                     --abs
1630                     d_print("lda");
1631                     a2_abs;
1632                     if exec_cycle = T3 then
1633                         set_nz_from_bus;
1634                         front_we(acc_cmd, '0');
1635                     end if;
1636
1637                 elsif instruction  = conv_std_logic_vector(16#bd#, dsize) then
1638                     --abs, x
1639                     d_print("lda");
1640                     a2_abs_xy(true);
1641                     if exec_cycle = T3 or exec_cycle = T4 then
1642                         --lda.
1643                         front_we(acc_cmd, '0');
1644                         set_nz_from_bus;
1645                     end if;
1646
1647                 elsif instruction  = conv_std_logic_vector(16#b9#, dsize) then
1648                     --abs, y
1649                     d_print("lda");
1650                     a2_abs_xy(false);
1651                     if exec_cycle = T3 or exec_cycle = T4 then
1652                         --lda.
1653                         front_we(acc_cmd, '0');
1654                         set_nz_from_bus;
1655                     end if;
1656
1657                 elsif instruction  = conv_std_logic_vector(16#a1#, dsize) then
1658                     --(indir, x)
1659                     d_print("lda");
1660
1661                 elsif instruction  = conv_std_logic_vector(16#b1#, dsize) then
1662                     --(indir), y
1663                     d_print("lda");
1664                     a2_indir_y;
1665                     if exec_cycle = T4 or exec_cycle = T5 then
1666                         --lda.
1667                         front_we(acc_cmd, '0');
1668                         set_nz_from_bus;
1669                     end if;
1670
1671                 elsif instruction  = conv_std_logic_vector(16#a2#, dsize) then
1672                     --imm
1673                     d_print("ldx");
1674                     fetch_imm;
1675                     set_nz_from_bus;
1676                     front_we(x_cmd, '0');
1677
1678                 elsif instruction  = conv_std_logic_vector(16#a6#, dsize) then
1679                     --zp
1680                     d_print("ldx");
1681                     a2_zp;
1682                     if exec_cycle = T2 then
1683                         front_we(x_cmd, '0');
1684                         set_nz_from_bus;
1685                     end if;
1686
1687                 elsif instruction  = conv_std_logic_vector(16#b6#, dsize) then
1688                     --zp, y
1689                     d_print("ldx");
1690                     a2_zp_xy(false);
1691                     if exec_cycle = T3 then
1692                         front_we(x_cmd, '0');
1693                         set_nz_from_bus;
1694                     end if;
1695
1696                 elsif instruction  = conv_std_logic_vector(16#ae#, dsize) then
1697                     --abs
1698                     d_print("ldx");
1699                     a2_abs;
1700                     if exec_cycle = T3 then
1701                         set_nz_from_bus;
1702                         front_we(x_cmd, '0');
1703                     end if;
1704
1705                 elsif instruction  = conv_std_logic_vector(16#be#, dsize) then
1706                     --abs, y
1707                     d_print("ldx");
1708                     a2_abs_xy(false);
1709                     if exec_cycle = T3 or exec_cycle = T4 then
1710                         front_we(x_cmd, '0');
1711                         set_nz_from_bus;
1712                     end if;
1713
1714                 elsif instruction  = conv_std_logic_vector(16#a0#, dsize) then
1715                     --imm
1716                     d_print("ldy");
1717                     fetch_imm;
1718                     set_nz_from_bus;
1719                     front_we(y_cmd, '0');
1720
1721                 elsif instruction  = conv_std_logic_vector(16#a4#, dsize) then
1722                     --zp
1723                     d_print("ldy");
1724                     a2_zp;
1725                     if exec_cycle = T2 then
1726                         front_we(y_cmd, '0');
1727                         set_nz_from_bus;
1728                     end if;
1729
1730                 elsif instruction  = conv_std_logic_vector(16#b4#, dsize) then
1731                     --zp, x
1732                     d_print("ldy");
1733                     a2_zp_xy(true);
1734                     if exec_cycle = T3 then
1735                         front_we(y_cmd, '0');
1736                         set_nz_from_bus;
1737                     end if;
1738
1739                 elsif instruction  = conv_std_logic_vector(16#ac#, dsize) then
1740                     --abs
1741                     d_print("ldy");
1742                     a2_abs;
1743                     if exec_cycle = T3 then
1744                         set_nz_from_bus;
1745                         front_we(y_cmd, '0');
1746                     end if;
1747
1748                 elsif instruction  = conv_std_logic_vector(16#bc#, dsize) then
1749                     --abs, x
1750                     d_print("ldy");
1751                     a2_abs_xy(true);
1752                     if exec_cycle = T3 or exec_cycle = T4 then
1753                         set_nz_from_bus;
1754                         front_we(y_cmd, '0');
1755                     end if;
1756
1757                 elsif instruction  = conv_std_logic_vector(16#09#, dsize) then
1758                     --imm
1759                     d_print("ora");
1760                     fetch_imm;
1761                     arith_en_n <= '0';
1762                     back_oe(acc_cmd, '0');
1763                     back_we(acc_cmd, '0');
1764                     set_nz_from_alu;
1765
1766                 elsif instruction  = conv_std_logic_vector(16#05#, dsize) then
1767                     --zp
1768                     d_print("ora");
1769                     a2_zp;
1770                     if exec_cycle = T2 then
1771                         arith_en_n <= '0';
1772                         back_oe(acc_cmd, '0');
1773                         back_we(acc_cmd, '0');
1774                         set_nz_from_alu;
1775                     end if;
1776
1777                 elsif instruction  = conv_std_logic_vector(16#15#, dsize) then
1778                     --zp, x
1779                     d_print("ora");
1780                     a2_zp_xy(true);
1781                     if exec_cycle = T3 then
1782                         arith_en_n <= '0';
1783                         back_oe(acc_cmd, '0');
1784                         back_we(acc_cmd, '0');
1785                         set_nz_from_alu;
1786                     end if;
1787
1788                 elsif instruction  = conv_std_logic_vector(16#0d#, dsize) then
1789                     --abs
1790                     d_print("ora");
1791                     a2_abs;
1792                     if exec_cycle = T3 then
1793                         arith_en_n <= '0';
1794                         back_oe(acc_cmd, '0');
1795                         back_we(acc_cmd, '0');
1796                         set_nz_from_alu;
1797                     end if;
1798
1799                 elsif instruction  = conv_std_logic_vector(16#1d#, dsize) then
1800                     --abs, x
1801                     d_print("ora");
1802                     a2_abs_xy(true);
1803                     if exec_cycle = T3 or exec_cycle = T4 then
1804                         arith_en_n <= '0';
1805                         back_oe(acc_cmd, '0');
1806                         back_we(acc_cmd, '0');
1807                         set_nz_from_alu;
1808                     end if;
1809
1810                 elsif instruction  = conv_std_logic_vector(16#19#, dsize) then
1811                     --abs, y
1812                     d_print("ora");
1813                     a2_abs_xy(false);
1814                     if exec_cycle = T3 or exec_cycle = T4 then
1815                         arith_en_n <= '0';
1816                         back_oe(acc_cmd, '0');
1817                         back_we(acc_cmd, '0');
1818                         set_nz_from_alu;
1819                     end if;
1820
1821                 elsif instruction  = conv_std_logic_vector(16#01#, dsize) then
1822                     --(indir, x)
1823                     d_print("ora");
1824
1825                 elsif instruction  = conv_std_logic_vector(16#11#, dsize) then
1826                     --(indir), y
1827                     d_print("ora");
1828                     a2_indir_y;
1829                     if exec_cycle = T4 or exec_cycle = T5 then
1830                         arith_en_n <= '0';
1831                         back_oe(acc_cmd, '0');
1832                         back_we(acc_cmd, '0');
1833                         set_nz_from_alu;
1834                     end if;
1835
1836                 elsif instruction  = conv_std_logic_vector(16#e9#, dsize) then
1837                     --imm
1838                     d_print("sbc");
1839                     fetch_imm;
1840                     arith_en_n <= '0';
1841                     back_oe(acc_cmd, '0');
1842                     back_we(acc_cmd, '0');
1843                     set_nvzc_from_alu;
1844
1845                 elsif instruction  = conv_std_logic_vector(16#e5#, dsize) then
1846                     --zp
1847                     d_print("sbc");
1848                     a2_zp;
1849                     if exec_cycle = T2 then
1850                         arith_en_n <= '0';
1851                         back_oe(acc_cmd, '0');
1852                         back_we(acc_cmd, '0');
1853                         set_nvzc_from_alu;
1854                     end if;
1855
1856                 elsif instruction  = conv_std_logic_vector(16#f5#, dsize) then
1857                     --zp, x
1858                     d_print("sbc");
1859                     a2_zp_xy(true);
1860                     if exec_cycle = T3 then
1861                         arith_en_n <= '0';
1862                         back_oe(acc_cmd, '0');
1863                         back_we(acc_cmd, '0');
1864                         set_nvzc_from_alu;
1865                     end if;
1866
1867                 elsif instruction  = conv_std_logic_vector(16#ed#, dsize) then
1868                     --abs
1869                     d_print("sbc");
1870                     a2_abs;
1871                     if exec_cycle = T3 then
1872                         arith_en_n <= '0';
1873                         back_oe(acc_cmd, '0');
1874                         back_we(acc_cmd, '0');
1875                         set_nvzc_from_alu;
1876                     end if;
1877
1878                 elsif instruction  = conv_std_logic_vector(16#fd#, dsize) then
1879                     --abs, x
1880                     d_print("sbc");
1881                     a2_abs_xy(true);
1882                     if exec_cycle = T3 or exec_cycle = T4 then
1883                         arith_en_n <= '0';
1884                         back_oe(acc_cmd, '0');
1885                         back_we(acc_cmd, '0');
1886                         set_nvzc_from_alu;
1887                     end if;
1888
1889                 elsif instruction  = conv_std_logic_vector(16#f9#, dsize) then
1890                     --abs, y
1891                     d_print("sbc");
1892                     a2_abs_xy(false);
1893                     if exec_cycle = T3 or exec_cycle = T4 then
1894                         arith_en_n <= '0';
1895                         back_oe(acc_cmd, '0');
1896                         back_we(acc_cmd, '0');
1897                         set_nvzc_from_alu;
1898                     end if;
1899
1900                 elsif instruction  = conv_std_logic_vector(16#e1#, dsize) then
1901                     --(indir, x)
1902                     d_print("sbc");
1903
1904                 elsif instruction  = conv_std_logic_vector(16#f1#, dsize) then
1905                     --(indir), y
1906                     d_print("sbc");
1907                     a2_indir_y;
1908                     if exec_cycle = T4 or exec_cycle = T5 then
1909                         arith_en_n <= '0';
1910                         back_oe(acc_cmd, '0');
1911                         back_we(acc_cmd, '0');
1912                         set_nvzc_from_alu;
1913                     end if;
1914
1915
1916
1917                 ----------------------------------------
1918                 ---A.3. store operation.
1919                 ----------------------------------------
1920                 elsif instruction  = conv_std_logic_vector(16#85#, dsize) then
1921                     --zp
1922                     d_print("sta");
1923                     a3_zp;
1924                     if exec_cycle = T2 then
1925                         front_oe(acc_cmd, '0');
1926                     end if;
1927
1928                 elsif instruction  = conv_std_logic_vector(16#95#, dsize) then
1929                     --zp, x
1930                     d_print("sta");
1931                     a3_zp_xy(true);
1932                     if exec_cycle = T2 then
1933                         front_oe(acc_cmd, '0');
1934                     end if;
1935
1936                 elsif instruction  = conv_std_logic_vector(16#8d#, dsize) then
1937                     --abs
1938                     d_print("sta");
1939                     a3_abs;
1940                     if exec_cycle = T3 then
1941                         front_oe(acc_cmd, '0');
1942                     end if;
1943
1944                 elsif instruction  = conv_std_logic_vector(16#9d#, dsize) then
1945                     --abs, x
1946                     d_print("sta");
1947                     a3_abs_xy (true);
1948                     if exec_cycle = T4 then
1949                         front_oe(acc_cmd, '0');
1950                     end if;
1951
1952                 elsif instruction  = conv_std_logic_vector(16#99#, dsize) then
1953                     --abs, y
1954                     d_print("sta");
1955                     a3_abs_xy (false);
1956                     if exec_cycle = T4 then
1957                         front_oe(acc_cmd, '0');
1958                     end if;
1959
1960                 elsif instruction  = conv_std_logic_vector(16#81#, dsize) then
1961                     --(indir, x)
1962                     d_print("sta");
1963
1964                 elsif instruction  = conv_std_logic_vector(16#91#, dsize) then
1965                     --(indir), y
1966                     d_print("sta");
1967                     a3_indir_y;
1968                     if exec_cycle = T5 then
1969                         front_oe(acc_cmd, '0');
1970                     end if;
1971
1972                 elsif instruction  = conv_std_logic_vector(16#86#, dsize) then
1973                     --zp
1974                     d_print("stx");
1975                     a3_zp;
1976                     if exec_cycle = T2 then
1977                         front_oe(x_cmd, '0');
1978                     end if;
1979
1980                 elsif instruction  = conv_std_logic_vector(16#96#, dsize) then
1981                     --zp, y
1982                     d_print("stx");
1983                     a3_zp_xy(false);
1984                     if exec_cycle = T2 then
1985                         front_oe(x_cmd, '0');
1986                     end if;
1987
1988                 elsif instruction  = conv_std_logic_vector(16#8e#, dsize) then
1989                     --abs
1990                     d_print("stx");
1991                     a3_abs;
1992                     if exec_cycle = T3 then
1993                         front_oe(x_cmd, '0');
1994                     end if;
1995
1996                 elsif instruction  = conv_std_logic_vector(16#84#, dsize) then
1997                     --zp
1998                     d_print("sty");
1999                     a3_zp;
2000                     if exec_cycle = T2 then
2001                         front_oe(y_cmd, '0');
2002                     end if;
2003
2004                 elsif instruction  = conv_std_logic_vector(16#94#, dsize) then
2005                     --zp, x
2006                     d_print("sty");
2007                     a3_zp_xy(true);
2008                     if exec_cycle = T2 then
2009                         front_oe(y_cmd, '0');
2010                     end if;
2011
2012                 elsif instruction  = conv_std_logic_vector(16#8c#, dsize) then
2013                     --abs
2014                     d_print("sty");
2015                     a3_abs;
2016                     if exec_cycle = T3 then
2017                         front_oe(y_cmd, '0');
2018                     end if;
2019
2020
2021                 ----------------------------------------
2022                 ---A.4. read-modify-write operation
2023                 ----------------------------------------
2024                 elsif instruction  = conv_std_logic_vector(16#06#, dsize) then
2025                     --zp
2026                     d_print("asl");
2027                     a4_zp;
2028                     if exec_cycle = T4 then
2029                         set_nzc_from_alu;
2030                     end if;
2031
2032                 elsif instruction  = conv_std_logic_vector(16#16#, dsize) then
2033                     --zp, x
2034                     d_print("asl");
2035                     a4_zp_x;
2036                     if exec_cycle = T5 then
2037                         set_nzc_from_alu;
2038                     end if;
2039
2040                 elsif instruction  = conv_std_logic_vector(16#0e#, dsize) then
2041                     --abs
2042                     d_print("asl");
2043                     a4_abs;
2044                     if exec_cycle = T5 then
2045                         set_nzc_from_alu;
2046                     end if;
2047
2048                 elsif instruction  = conv_std_logic_vector(16#1e#, dsize) then
2049                     --abs, x
2050                     d_print("asl");
2051                     a4_abs_x;
2052                     if exec_cycle = T6 then
2053                         set_nzc_from_alu;
2054                     end if;
2055
2056                 elsif instruction  = conv_std_logic_vector(16#c6#, dsize) then
2057                     --zp
2058                     d_print("dec");
2059                     a4_zp;
2060                     if exec_cycle = T4 then
2061                         set_nz_from_bus;
2062                     end if;
2063
2064                 elsif instruction  = conv_std_logic_vector(16#d6#, dsize) then
2065                     --zp, x
2066                     d_print("dec");
2067                     a4_zp_x;
2068                     if exec_cycle = T5 then
2069                         set_nz_from_bus;
2070                     end if;
2071
2072                 elsif instruction  = conv_std_logic_vector(16#ce#, dsize) then
2073                     --abs
2074                     d_print("dec");
2075                     a4_abs;
2076                     if exec_cycle = T5 then
2077                         set_nz_from_bus;
2078                     end if;
2079
2080                 elsif instruction  = conv_std_logic_vector(16#de#, dsize) then
2081                     --abs, x
2082                     d_print("dec");
2083                     a4_abs_x;
2084                     if exec_cycle = T6 then
2085                         set_nz_from_bus;
2086                     end if;
2087
2088                 elsif instruction  = conv_std_logic_vector(16#e6#, dsize) then
2089                     --zp
2090                     d_print("inc");
2091                     a4_zp;
2092                     if exec_cycle = T4 then
2093                         set_nz_from_bus;
2094                     end if;
2095
2096                 elsif instruction  = conv_std_logic_vector(16#f6#, dsize) then
2097                     --zp, x
2098                     d_print("inc");
2099                     a4_zp_x;
2100                     if exec_cycle = T5 then
2101                         set_nz_from_bus;
2102                     end if;
2103
2104                 elsif instruction  = conv_std_logic_vector(16#ee#, dsize) then
2105                     --abs
2106                     d_print("inc");
2107                     a4_abs;
2108                     if exec_cycle = T5 then
2109                         set_nz_from_bus;
2110                     end if;
2111
2112                 elsif instruction  = conv_std_logic_vector(16#fe#, dsize) then
2113                     --abs, x
2114                     d_print("inc");
2115                     a4_abs_x;
2116                     if exec_cycle = T6 then
2117                         set_nz_from_bus;
2118                     end if;
2119
2120                 elsif instruction  = conv_std_logic_vector(16#46#, dsize) then
2121                     --zp
2122                     d_print("lsr");
2123                     a4_zp;
2124                     if exec_cycle = T4 then
2125                         set_zc_from_alu;
2126                     end if;
2127
2128                 elsif instruction  = conv_std_logic_vector(16#56#, dsize) then
2129                     --zp, x
2130                     d_print("lsr");
2131                     a4_zp_x;
2132                     if exec_cycle = T5 then
2133                         set_zc_from_alu;
2134                     end if;
2135
2136                 elsif instruction  = conv_std_logic_vector(16#4e#, dsize) then
2137                     --abs
2138                     d_print("lsr");
2139                     a4_abs;
2140                     if exec_cycle = T5 then
2141                         set_zc_from_alu;
2142                     end if;
2143
2144                 elsif instruction  = conv_std_logic_vector(16#5e#, dsize) then
2145                     --abs, x
2146                     d_print("lsr");
2147                     a4_abs_x;
2148                     if exec_cycle = T6 then
2149                         set_zc_from_alu;
2150                     end if;
2151
2152                 elsif instruction  = conv_std_logic_vector(16#26#, dsize) then
2153                     --zp
2154                     d_print("rol");
2155                     a4_zp;
2156                     if exec_cycle = T4 then
2157                         set_nzc_from_alu;
2158                     end if;
2159
2160                 elsif instruction  = conv_std_logic_vector(16#36#, dsize) then
2161                     --zp, x
2162                     d_print("rol");
2163                     a4_zp_x;
2164                     if exec_cycle = T5 then
2165                         set_nzc_from_alu;
2166                     end if;
2167
2168                 elsif instruction  = conv_std_logic_vector(16#2e#, dsize) then
2169                     --abs
2170                     d_print("rol");
2171                     a4_abs;
2172                     if exec_cycle = T5 then
2173                         set_nzc_from_alu;
2174                     end if;
2175
2176                 elsif instruction  = conv_std_logic_vector(16#3e#, dsize) then
2177                     --abs, x
2178                     d_print("rol");
2179                     a4_abs_x;
2180                     if exec_cycle = T6 then
2181                         set_nzc_from_alu;
2182                     end if;
2183
2184                 elsif instruction  = conv_std_logic_vector(16#66#, dsize) then
2185                     --zp
2186                     d_print("ror");
2187                     a4_zp;
2188                     if exec_cycle = T4 then
2189                         set_nzc_from_alu;
2190                     end if;
2191
2192                 elsif instruction  = conv_std_logic_vector(16#76#, dsize) then
2193                     --zp, x
2194                     d_print("ror");
2195                     a4_zp_x;
2196                     if exec_cycle = T5 then
2197                         set_nzc_from_alu;
2198                     end if;
2199
2200                 elsif instruction  = conv_std_logic_vector(16#6e#, dsize) then
2201                     --abs
2202                     d_print("ror");
2203                     a4_abs;
2204                     if exec_cycle = T5 then
2205                         set_nzc_from_alu;
2206                     end if;
2207
2208                 elsif instruction  = conv_std_logic_vector(16#7e#, dsize) then
2209                     --abs, x
2210                     d_print("ror");
2211                     a4_abs_x;
2212                     if exec_cycle = T6 then
2213                         set_nzc_from_alu;
2214                     end if;
2215
2216
2217                 ----------------------------------------
2218                 --A.5. miscellaneous oprations.
2219                 ----------------------------------------
2220
2221                 -- A.5.1 push/pull
2222                 elsif instruction = conv_std_logic_vector(16#08#, dsize) then
2223                     d_print("php");
2224                     a51_push;
2225                     if exec_cycle = T2 then
2226                         stat_bus_oe_n <= '0';
2227                     end if;
2228
2229                 elsif instruction = conv_std_logic_vector(16#48#, dsize) then
2230                     d_print("pha");
2231                     a51_push;
2232                     if exec_cycle = T2 then
2233                         front_oe(acc_cmd, '0');
2234                     end if;
2235
2236                 elsif instruction = conv_std_logic_vector(16#28#, dsize) then
2237                     d_print("plp");
2238                     a52_pull;
2239                     if exec_cycle = T3 then
2240                         stat_dec_oe_n <= '1';
2241                         stat_bus_all_n <= '0';
2242                     end if;
2243
2244                 elsif instruction = conv_std_logic_vector(16#68#, dsize) then
2245                     d_print("pla");
2246                     a52_pull;
2247                     if exec_cycle = T3 then
2248                         front_we(acc_cmd, '0');
2249                         set_nz_from_bus;
2250                     end if;
2251
2252
2253                 ----------------------------------------
2254                 -- A.5.3 jsr
2255                 ----------------------------------------
2256                 elsif instruction = conv_std_logic_vector(16#20#, dsize) then
2257                     if exec_cycle = T1 then
2258                         d_print("jsr abs 2");
2259                         --fetch opcode.
2260                         fetch_next;
2261                         dbuf_int_oe_n <= '0';
2262                         --latch adl
2263                         dl_al_we_n <= '0';
2264                         next_cycle <= T2;
2265                     elsif exec_cycle = T2 then
2266                         d_print("jsr 3");
2267                         fetch_stop;
2268                         dbuf_int_oe_n <= '1';
2269                         dl_al_we_n <= '1';
2270
2271                        --push return addr high into stack.
2272                         sp_push_n <= '0';
2273                         sp_oe_n <= '0';
2274                         front_oe(pch_cmd, '0');
2275                         back_oe(sp_cmd, '0');
2276                         back_we(sp_cmd, '0');
2277                         r_nw <= '0';
2278                         next_cycle <= T3;
2279                     elsif exec_cycle = T3 then
2280                         d_print("jsr 4");
2281                         front_oe(pch_cmd, '1');
2282
2283                        --push return addr low into stack.
2284                         sp_push_n <= '0';
2285                         sp_oe_n <= '0';
2286                         front_oe(pcl_cmd, '0');
2287                         back_oe(sp_cmd, '0');
2288                         back_we(sp_cmd, '0');
2289                         r_nw <= '0';
2290
2291                         next_cycle <= T4;
2292                     elsif exec_cycle = T4 then
2293                         d_print("jsr 5");
2294                         sp_push_n <= '1';
2295                         sp_oe_n <= '1';
2296                         front_oe(pcl_cmd, '1');
2297                         back_oe(sp_cmd, '1');
2298                         back_we(sp_cmd, '1');
2299                         r_nw <= '1';
2300
2301                         --fetch last op.
2302                         back_oe(pch_cmd, '0');
2303                         back_oe(pcl_cmd, '0');
2304                         dbuf_int_oe_n <= '0';
2305                         dl_ah_we_n <= '0';
2306
2307                         next_cycle <= T5;
2308                     elsif exec_cycle = T5 then
2309                         d_print("jsr 6");
2310
2311                         back_oe(pch_cmd, '1');
2312                         back_oe(pcl_cmd, '1');
2313                         dbuf_int_oe_n <= '1';
2314                         dl_ah_we_n <= '1';
2315
2316                         --load/output  pch
2317                         ad_oe_n <= '1';
2318                         dl_dh_oe_n <= '0';
2319                         front_we(pch_cmd, '0');
2320
2321                         --load pcl.
2322                         dl_al_oe_n <= '0';
2323                         back_we(pcl_cmd, '0');
2324
2325                         next_cycle <= T0;
2326                     end if; --if exec_cycle = T1 then
2327
2328                 -- A.5.4 break
2329                 elsif instruction = conv_std_logic_vector(16#00#, dsize) then
2330
2331                 ----------------------------------------
2332                 -- A.5.5 return from interrupt
2333                 ----------------------------------------
2334                 elsif instruction = conv_std_logic_vector(16#40#, dsize) then
2335                     if exec_cycle = T1 then
2336                         d_print("rti 2");
2337                         fetch_stop;
2338
2339                         --pop stack (decrement only)
2340                         back_oe(sp_cmd, '0');
2341                         back_we(sp_cmd, '0');
2342                         sp_pop_n <= '0';
2343                         sp_oe_n <= '0';
2344
2345                         next_cycle <= T2;
2346                     elsif exec_cycle = T2 then
2347                         d_print("rti 3");
2348
2349                         --pop p (status)
2350                         back_oe(sp_cmd, '0');
2351                         back_we(sp_cmd, '0');
2352                         sp_pop_n <= '0';
2353                         sp_oe_n <= '0';
2354
2355                         --load status reg
2356                         stat_dec_oe_n <= '1';
2357                         dbuf_int_oe_n <= '0';
2358                         stat_bus_all_n <= '0';
2359
2360                         next_cycle <= T3;
2361                     elsif exec_cycle = T3 then
2362                         d_print("rti 4");
2363                         stat_bus_all_n <= '1';
2364
2365                         --pop pcl
2366                         back_oe(sp_cmd, '0');
2367                         back_we(sp_cmd, '0');
2368                         sp_pop_n <= '0';
2369                         sp_oe_n <= '0';
2370
2371                         --load lo addr.
2372                         dbuf_int_oe_n <= '0';
2373                         front_we(pcl_cmd, '0');
2374
2375                         next_cycle <= T4;
2376                     elsif exec_cycle = T4 then
2377                         d_print("rti 5");
2378                         --stack decrement stop.
2379                         back_we(sp_cmd, '1');
2380                         sp_pop_n <= '1';
2381                         front_we(pcl_cmd, '1');
2382
2383                         --pop pch
2384                         back_oe(sp_cmd, '0');
2385                         sp_oe_n <= '0';
2386                         --load hi addr.
2387                         dbuf_int_oe_n <= '0';
2388                         front_we(pch_cmd, '0');
2389
2390                         next_cycle <= T5;
2391                     elsif exec_cycle = T5 then
2392                         d_print("rti 6");
2393                         back_oe(sp_cmd, '1');
2394                         sp_oe_n <= '1';
2395                         --load hi addr.
2396                         dbuf_int_oe_n <= '1';
2397                         front_we(pch_cmd, '1');
2398
2399                         --increment pc.
2400                         next_cycle <= T0;
2401                     end if; --if exec_cycle = T1 then
2402
2403                 ----------------------------------------
2404                 -- A.5.6 jmp
2405                 ----------------------------------------
2406                 elsif instruction = conv_std_logic_vector(16#4c#, dsize) then
2407                     --abs
2408                     if exec_cycle = T1 then
2409                         d_print("jmp 2");
2410                         --fetch next opcode (abs low).
2411                         fetch_next;
2412
2413                         --latch abs low data.
2414                         dbuf_int_oe_n <= '0';
2415                         dl_al_we_n <= '0';
2416                         next_cycle <= T2;
2417                     elsif exec_cycle = T2 then
2418                         d_print("jmp 3");
2419                         dl_al_we_n <= '1';
2420
2421                         --fetch abs hi
2422                         fetch_next;
2423
2424                         --latch  in dlh
2425                         dbuf_int_oe_n <= '0';
2426                         dl_ah_we_n <= '0';
2427                         ---load pch.
2428                         front_we(pch_cmd, '0');
2429
2430                         next_cycle <= T0;
2431                     end if;
2432
2433                 elsif instruction = conv_std_logic_vector(16#6c#, dsize) then
2434                     --jmp (indir)
2435                     if exec_cycle = T1 then
2436                         d_print("jmp 2");
2437                         --fetch next opcode (abs low).
2438                         fetch_next;
2439
2440                         --latch abs low data.
2441                         dbuf_int_oe_n <= '0';
2442                         dl_al_we_n <= '0';
2443                         next_cycle <= T2;
2444                     elsif exec_cycle = T2 then
2445                         d_print("jmp 3");
2446                         dl_al_we_n <= '1';
2447
2448                         --fetch abs hi
2449                         fetch_next;
2450
2451                         --latch  in dlh
2452                         dbuf_int_oe_n <= '0';
2453                         dl_ah_we_n <= '0';
2454                         next_cycle <= T3;
2455
2456                     elsif exec_cycle = T3 then
2457                         fetch_stop;
2458                         dl_ah_we_n <= '1';
2459
2460                         --IAH/IAL > ADL
2461                         dl_ah_oe_n <= '0';
2462                         dl_al_oe_n <= '0';
2463                         front_we(pcl_cmd, '0');
2464                         next_cycle <= T4;
2465
2466                     elsif exec_cycle = T4 then
2467                         dl_ah_oe_n <= '0';
2468                         dl_al_oe_n <= '0';
2469                         front_we(pcl_cmd, '1');
2470
2471                         --IAH/IAL+1 > ADH
2472                         front_we(pch_cmd, '0');
2473                         indir_n <= '0';
2474
2475                         next_cycle <= T0;
2476
2477                     end if;
2478
2479
2480                 ----------------------------------------
2481                 -- A.5.7 return from soubroutine
2482                 ----------------------------------------
2483                 elsif instruction = conv_std_logic_vector(16#60#, dsize) then
2484                     if exec_cycle = T1 then
2485                         d_print("rts 2");
2486                         fetch_stop;
2487
2488                         --pop stack (decrement only)
2489                         back_oe(sp_cmd, '0');
2490                         back_we(sp_cmd, '0');
2491                         sp_pop_n <= '0';
2492                         sp_oe_n <= '0';
2493
2494                         next_cycle <= T2;
2495                     elsif exec_cycle = T2 then
2496                         d_print("rts 3");
2497
2498                         --pop pcl
2499                         back_oe(sp_cmd, '0');
2500                         back_we(sp_cmd, '0');
2501                         sp_pop_n <= '0';
2502                         sp_oe_n <= '0';
2503
2504                         --load lo addr.
2505                         dbuf_int_oe_n <= '0';
2506                         front_we(pcl_cmd, '0');
2507
2508                         next_cycle <= T3;
2509                     elsif exec_cycle = T3 then
2510                         d_print("rts 4");
2511                         --stack decrement stop.
2512                         back_we(sp_cmd, '1');
2513                         sp_pop_n <= '1';
2514                         front_we(pcl_cmd, '1');
2515
2516                         --pop pch
2517                         back_oe(sp_cmd, '0');
2518                         sp_oe_n <= '0';
2519                         --load hi addr.
2520                         dbuf_int_oe_n <= '0';
2521                         front_we(pch_cmd, '0');
2522
2523                         next_cycle <= T4;
2524                     elsif exec_cycle = T4 then
2525                         d_print("rts 5");
2526                         back_oe(sp_cmd, '1');
2527                         sp_oe_n <= '1';
2528                         --load hi addr.
2529                         dbuf_int_oe_n <= '1';
2530                         front_we(pch_cmd, '1');
2531                         --empty cycle.
2532                         --complying h/w manual...
2533                         next_cycle <= T5;
2534                     elsif exec_cycle = T5 then
2535                         d_print("rts 6");
2536
2537                         --increment pc.
2538                         fetch_next;
2539                         next_cycle <= T0;
2540                     end if; --if exec_cycle = T1 then
2541
2542                 ----------------------------------------
2543                 -- A.5.8 branch operations
2544                 ----------------------------------------
2545                 elsif instruction = conv_std_logic_vector(16#90#, dsize) then
2546                     d_print("bcc");
2547                     a58_branch (st_C, '0');
2548
2549                 elsif instruction = conv_std_logic_vector(16#b0#, dsize) then
2550                     d_print("bcs");
2551                     a58_branch (st_C, '1');
2552
2553                 elsif instruction = conv_std_logic_vector(16#f0#, dsize) then
2554                     d_print("beq");
2555                     a58_branch (st_Z, '1');
2556
2557                 elsif instruction = conv_std_logic_vector(16#30#, dsize) then
2558                     d_print("bmi");
2559                     a58_branch (st_N, '1');
2560
2561                 elsif instruction = conv_std_logic_vector(16#d0#, dsize) then
2562                     d_print("bne");
2563                     a58_branch (st_Z, '0');
2564
2565                 elsif instruction = conv_std_logic_vector(16#10#, dsize) then
2566                     d_print("bpl");
2567                     a58_branch (st_N, '0');
2568
2569                 elsif instruction = conv_std_logic_vector(16#50#, dsize) then
2570                     d_print("bvc");
2571                     a58_branch (st_V, '0');
2572
2573                 elsif instruction = conv_std_logic_vector(16#70#, dsize) then
2574                     d_print("bvs");
2575                     a58_branch (st_V, '1');
2576
2577                 else
2578                     ---unknown instruction!!!!
2579                     assert false
2580                         report "======== unknow instruction "
2581                             & conv_hex8(conv_integer(instruction))
2582                         severity failure;
2583                 end if; --if instruction = conv_std_logic_vector(16#0a#, dsize)
2584
2585             elsif exec_cycle = R0 then
2586                 d_print(string'("reset"));
2587
2588                 front_we(pch_cmd, '1');
2589                 back_we(pcl_cmd, '1');
2590
2591                 --initialize port...
2592                 inst_we_n <= '1';
2593                 ad_oe_n <= '1';
2594                 dbuf_int_oe_n <= '1';
2595                 dl_al_we_n <= '1';
2596                 dl_ah_we_n <= '1';
2597                 dl_al_oe_n <= '1';
2598                 dl_ah_oe_n <= '1';
2599                 dl_dh_oe_n <= '1';
2600                 pcl_inc_n <= '1';
2601                 pcl_cmd <= "1111";
2602                 pch_cmd <= "1111";
2603                 sp_cmd <= "1111";
2604                 sp_oe_n <= '1';
2605                 sp_push_n <= '1';
2606                 sp_pop_n <= '1';
2607                 acc_cmd <= "1111";
2608                 x_cmd <= "1111";
2609                 y_cmd <= "1111";
2610
2611                 abs_xy_n <= '1';
2612                 pg_next_n <= '1';
2613                 zp_n <= '1';
2614                 zp_xy_n <= '1';
2615                 rel_calc_n <= '1';
2616                 indir_n <= '1';
2617                 indir_x_n <= '1';
2618                 indir_y_n <= '1';
2619                 arith_en_n <= '1';
2620
2621                 stat_dec_oe_n <= '1';
2622                 stat_bus_oe_n <= '1';
2623                 stat_set_flg_n <= '1';
2624                 stat_flg <= '1';
2625                 stat_bus_all_n <= '1';
2626                 stat_bus_nz_n <= '1';
2627                 stat_alu_we_n <= '1';
2628
2629                 r_vec_oe_n <= '1';
2630                 n_vec_oe_n <= '1';
2631                 i_vec_oe_n <= '1';
2632                 nmi_handled_n := '1';
2633                 r_nw <= '1';
2634
2635                 next_cycle <= R1;
2636             elsif exec_cycle = R1 or exec_cycle = N1 then
2637                 pcl_cmd <= "1111";
2638                 pcl_inc_n <= '1';
2639                 inst_we_n <= '1';
2640                 dl_al_oe_n <= '1';
2641
2642                 --push pch.
2643                 d_print("R1");
2644                 ad_oe_n <= '0';
2645                 sp_push_n <= '0';
2646                 sp_oe_n <= '0';
2647                 pch_cmd <= "0111";
2648                 --front_oe(pch_cmd, '0');
2649                 back_oe(sp_cmd, '0');
2650                 back_we(sp_cmd, '0');
2651                 r_nw <= '0';
2652
2653                 if exec_cycle = R1 then
2654                     next_cycle <= R2;
2655                 elsif exec_cycle = N1 then
2656                     next_cycle <= N2;
2657                 end if;
2658
2659             elsif exec_cycle = R2 or exec_cycle = N2 then
2660                 front_oe(pch_cmd, '1');
2661
2662                --push pcl.
2663                 sp_push_n <= '0';
2664                 sp_oe_n <= '0';
2665                 front_oe(pcl_cmd, '0');
2666                 back_oe(sp_cmd, '0');
2667                 back_we(sp_cmd, '0');
2668                 r_nw <= '0';
2669
2670                 if exec_cycle = R2 then
2671                     next_cycle <= R3;
2672                 elsif exec_cycle = N2 then
2673                     next_cycle <= N3;
2674                 end if;
2675
2676             elsif exec_cycle = R3 or exec_cycle = N3 then
2677                 front_oe(pcl_cmd, '1');
2678
2679                --push status.
2680                 sp_push_n <= '0';
2681                 sp_oe_n <= '0';
2682                 stat_bus_oe_n <= '0';
2683                 back_oe(sp_cmd, '0');
2684                 back_we(sp_cmd, '0');
2685                 r_nw <= '0';
2686
2687                 if exec_cycle = R3 then
2688                     next_cycle <= R4;
2689                 elsif exec_cycle = N3 then
2690                     next_cycle <= N4;
2691                 end if;
2692
2693             elsif exec_cycle = R4 or exec_cycle = N4 then
2694                 stat_bus_oe_n <= '1';
2695                 sp_push_n <= '1';
2696                 sp_oe_n <= '1';
2697                 front_oe(pcl_cmd, '1');
2698                 back_oe(sp_cmd, '1');
2699                 back_we(sp_cmd, '1');
2700
2701                 --fetch reset vector low
2702                 r_nw <= '1';
2703                 dbuf_int_oe_n <= '0';
2704                 front_we(pcl_cmd, '0');
2705
2706                 if exec_cycle = R4 then
2707                     r_vec_oe_n <= '0';
2708                     next_cycle <= R5;
2709                 elsif exec_cycle = N4 then
2710                     n_vec_oe_n <= '0';
2711                     next_cycle <= N5;
2712                 end if;
2713
2714             elsif exec_cycle = R5 or exec_cycle = N5 then
2715                 front_we(pcl_cmd, '1');
2716
2717                 --fetch reset vector hi
2718                 front_we(pch_cmd, '0');
2719                 indir_n <= '0';
2720
2721                 if exec_cycle = N5 then
2722                     nmi_handled_n := '0';
2723                 end if;
2724                 --start execute cycle.
2725                 next_cycle <= T0;
2726
2727             elsif exec_cycle(5) = '1' then
2728                 ---pc increment and next page.
2729                 d_print(string'("pch next page..."));
2730                 --pcl stop increment
2731                 pcl_inc_n <= '1';
2732                 back_we(pcl_cmd, '1');
2733                 --pch increment
2734                 back_we(pch_cmd, '0');
2735                 back_oe(pch_cmd, '0');
2736
2737                 if ('0' & exec_cycle(4 downto 0) = T0) then
2738                     --do the t0 identical routine.
2739                     disable_pins;
2740                     inst_we_n <= '1';
2741                     r_nw <= '1';
2742
2743                 elsif ('0' & exec_cycle(4 downto 0) = T1) then
2744                     --if fetch cycle, preserve instrution register
2745                     inst_we_n <= '1';
2746
2747                     --TODO: must handle for jmp case???
2748                 elsif ('0' & exec_cycle(4 downto 0) = T2) then
2749                     --disable previous we_n gate.
2750                     --t1 cycle is fetch low oprand.
2751                     dl_al_we_n <= '1';
2752                 elsif ('0' & exec_cycle(4 downto 0) = T3) then
2753                     --t2 cycle is fetch high oprand.
2754                     dl_ah_we_n <= '1';
2755                 end if;
2756
2757             end if; --if exec_cycle = T0 then
2758
2759         end if; --if (set_clk'event and set_clk = '1')
2760
2761     end process;
2762
2763 end rtl;
2764