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sdc added. must rework for timing again... all clocks must be aligned on the risigg...
[motonesfpga/motonesfpga.git] / de1_nes / mos6502-timing.sdc
1 create_clock -name base_clock -period 20 [get_ports {base_clk}]\r
2 create_generated_clock -name cpu_clock -source [get_ports {base_clk}] -divide_by 2