2 use IEEE.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
5 entity testbench_motones_sim is
6 end testbench_motones_sim;
8 architecture stimulus of testbench_motones_sim is
12 signal dbg_cpu_clk : out std_logic;
13 signal dbg_ppu_clk : out std_logic;
14 signal dbg_emu_ppu_clk : out std_logic;
15 signal dbg_mem_clk : out std_logic;
16 signal dbg_r_nw : out std_logic;
17 signal dbg_addr : out std_logic_vector( 16 - 1 downto 0);
18 signal dbg_d_io : out std_logic_vector( 8 - 1 downto 0);
19 signal dbg_vram_ad : out std_logic_vector (7 downto 0);
20 signal dbg_vram_a : out std_logic_vector (13 downto 8);
23 signal dbg_instruction : out std_logic_vector(7 downto 0);
24 signal dbg_int_d_bus : out std_logic_vector(7 downto 0);
25 signal dbg_exec_cycle : out std_logic_vector (5 downto 0);
26 signal dbg_ea_carry : out std_logic;
27 -- signal dbg_index_bus : out std_logic_vector(7 downto 0);
28 -- signal dbg_acc_bus : out std_logic_vector(7 downto 0);
29 signal dbg_status : out std_logic_vector(7 downto 0);
30 -- signal dbg_pcl, dbg_pch : out std_logic_vector(7 downto 0);
31 signal dbg_sp, dbg_x, dbg_y, dbg_acc : out std_logic_vector(7 downto 0);
32 signal dbg_dec_oe_n : out std_logic;
33 signal dbg_dec_val : out std_logic_vector (7 downto 0);
34 signal dbg_int_dbus : out std_logic_vector (7 downto 0);
35 -- signal dbg_status_val : out std_logic_vector (7 downto 0);
36 -- signal dbg_stat_we_n : out std_logic;
37 -- signal dbg_idl_h, dbg_idl_l, dbg_dbb_r, dbg_dbb_w : out std_logic_vector (7 downto 0);
40 signal dbg_ppu_ce_n : out std_logic;
41 signal dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status : out std_logic_vector (7 downto 0);
42 signal dbg_ppu_addr : out std_logic_vector (13 downto 0);
43 signal dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y : out std_logic_vector (7 downto 0);
44 signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0);
45 signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0);
46 signal dbg_nmi : out std_logic;
47 signal dummy_nmi : in std_logic;
51 base_clk : in std_logic;
53 joypad1 : in std_logic_vector(7 downto 0);
54 joypad2 : in std_logic_vector(7 downto 0);
55 h_sync_n : out std_logic;
56 v_sync_n : out std_logic;
57 r : out std_logic_vector(3 downto 0);
58 g : out std_logic_vector(3 downto 0);
59 b : out std_logic_vector(3 downto 0);
60 nt_v_mirror : in std_logic
64 signal base_clk : std_logic;
65 signal reset_input : std_logic;
66 signal nmi_input : std_logic;
67 signal dbg_nmi : std_logic;
68 signal dummy_nmi : std_logic;
70 signal h_sync_n : std_logic;
71 signal v_sync_n : std_logic;
72 signal r : std_logic_vector(3 downto 0);
73 signal g : std_logic_vector(3 downto 0);
74 signal b : std_logic_vector(3 downto 0);
75 signal joypad1 : std_logic_vector(7 downto 0);
76 signal joypad2 : std_logic_vector(7 downto 0);
77 signal nt_v_mirror : std_logic;
79 constant powerup_time : time := 2 us;
80 constant reset_time : time := 890 ns;
82 ---clock frequency = 21,477,270 (21 MHz)
83 --constant base_clock_time : time := 46 ns;
85 --DE1 base clock = 50 MHz
86 constant base_clock_time : time := 20 ns;
88 signal dbg_cpu_clk : std_logic;
89 signal dbg_ppu_clk : std_logic;
90 signal dbg_emu_ppu_clk : std_logic;
91 signal dbg_mem_clk : std_logic;
92 signal dbg_r_nw : std_logic;
93 signal dbg_addr : std_logic_vector( 16 - 1 downto 0);
94 signal dbg_d_io : std_logic_vector( 8 - 1 downto 0);
95 signal dbg_vram_ad : std_logic_vector (7 downto 0);
96 signal dbg_vram_a : std_logic_vector (13 downto 8);
97 signal dbg_instruction : std_logic_vector(7 downto 0);
98 signal dbg_int_d_bus : std_logic_vector(7 downto 0);
99 signal dbg_exec_cycle : std_logic_vector (5 downto 0);
100 signal dbg_ea_carry : std_logic;
101 -- signal dbg_index_bus : std_logic_vector(7 downto 0);
102 -- signal dbg_acc_bus : std_logic_vector(7 downto 0);
103 signal dbg_status : std_logic_vector(7 downto 0);
104 signal dbg_pcl, dbg_pch, dbg_sp, dbg_x, dbg_y, dbg_acc : std_logic_vector(7 downto 0);
105 signal dbg_dec_oe_n : std_logic;
106 signal dbg_dec_val : std_logic_vector (7 downto 0);
107 signal dbg_int_dbus : std_logic_vector (7 downto 0);
108 -- signal dbg_status_val : std_logic_vector (7 downto 0);
109 signal dbg_stat_we_n : std_logic;
110 signal dbg_idl_h, dbg_idl_l, dbg_dbb_r, dbg_dbb_w : std_logic_vector (7 downto 0);
111 signal dbg_ppu_ce_n : std_logic;
112 signal dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status : std_logic_vector (7 downto 0);
113 signal dbg_ppu_addr : std_logic_vector (13 downto 0);
114 signal dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y : std_logic_vector (7 downto 0);
115 signal dbg_disp_nt, dbg_disp_attr : std_logic_vector (7 downto 0);
116 signal dbg_disp_ptn_h, dbg_disp_ptn_l : std_logic_vector (15 downto 0);
117 signal dbg_ppu_addr_we_n : std_logic;
118 signal dbg_ppu_clk_cnt : std_logic_vector(1 downto 0);
122 sim_board : de1_nes port map (
140 dbg_sp, dbg_x, dbg_y, dbg_acc ,
146 --dbg_idl_h, dbg_idl_l, dbg_dbb_r, dbg_dbb_w,
149 dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status ,
151 dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y,
152 dbg_disp_nt, dbg_disp_attr ,
153 dbg_disp_ptn_h, dbg_disp_ptn_l ,
159 base_clk, reset_input, joypad1, joypad2,
160 h_sync_n, v_sync_n, r, g, b, nt_v_mirror);
166 wait for powerup_time;
175 --- generate base clock.
179 wait for base_clock_time / 2;
181 wait for base_clock_time / 2;
186 constant nmi_wait : time := 100657965 ps;
187 --constant nmi_wait : time := 10 ms;
188 constant vblank_time : time := 60 us;
189 variable wait_cnt : integer := 0;
192 if (wait_cnt = 0) then
194 wait for powerup_time + reset_time + nmi_wait;
195 wait_cnt := wait_cnt + 1;
198 wait for vblank_time ;
200 wait for vblank_time / 4;
204 dummy_nmi <= nmi_input;
207 --set chr rom mirror setting.