signal x_res_n : std_logic;\r
signal y_res_n : std_logic;\r
signal y_en_n : std_logic;\r
-signal vga_clk_n : std_logic;\r
\r
signal emu_ppu_clk_n : std_logic;\r
signal nes_x : std_logic_vector (8 downto 0);\r
begin\r
dbg_vga_x <= vga_x;\r
dbg_vga_y <= vga_y;\r
+ dbg_nes_x <= nes_x;\r
+ dbg_nes_y <= nes_y;\r
+ dbg_disp_nt <= disp_nt;\r
+ dbg_disp_attr <= disp_attr;\r
+ dbg_disp_ptn_h <= disp_ptn_h;\r
+ dbg_disp_ptn_l <= disp_ptn_l;\r
+ dbg_plt_addr <= plt_addr;\r
+ dbg_plt_data <= plt_data;\r
+ dbg_plt_ce_rn_wn <= plt_ram_ce_n & plt_r_n & plt_w_n;\r
+ dbg_p_oam_ce_rn_wn <= p_oam_ram_ce_n & p_oam_r_n & p_oam_w_n;\r
+ dbg_p_oam_addr <= p_oam_addr;\r
+ dbg_p_oam_data <= p_oam_data;\r
+ dbg_s_oam_ce_rn_wn <= s_oam_ram_ce_n & s_oam_r_n & s_oam_w_n;\r
+ dbg_s_oam_addr <= s_oam_addr;\r
+ dbg_s_oam_data <= s_oam_data;\r
+\r
\r
- vga_clk_n <= not vga_clk;\r
\r
+ -----------------------------------------\r
--vga position counter\r
+ -----------------------------------------\r
vga_x_inst : counter_register generic map (10, 1)\r
port map (vga_clk, x_res_n, '0', '1', (others => '0'), vga_x);\r
vga_y_inst : counter_register generic map (10, 1)\r
end if;\r
end process;\r
\r
+\r
+ -----------------------------------------\r
+ ---emurated ppu clock and nes positions...\r
+ -----------------------------------------\r
emu_ppu_clk_n <= not emu_ppu_clk;\r
nes_x <= vga_x(9 downto 1);\r
--debug purpose, accelarate the clock...\r
nes_y <= vga_y(9 downto 1);\r
--nes_y <= vga_y(8 downto 0);\r
\r
-------------------------------------------------------------------------\r
-------------------------------------------------------------------------\r
-------------------------------------------------------------------------\r
-------------------------------------------------------------------------\r
------------------------- ppu render instance... ------------------------\r
-------------------------------------------------------------------------\r
-------------------------------------------------------------------------\r
-------------------------------------------------------------------------\r
-------------------------------------------------------------------------\r
-\r
- dbg_nes_x <= nes_x;\r
- dbg_nes_y <= nes_y;\r
- dbg_disp_nt <= disp_nt;\r
- dbg_disp_attr <= disp_attr;\r
- dbg_disp_ptn_h <= disp_ptn_h;\r
- dbg_disp_ptn_l <= disp_ptn_l;\r
- dbg_plt_addr <= plt_addr;\r
- dbg_plt_data <= plt_data;\r
- dbg_plt_ce_rn_wn <= plt_ram_ce_n & plt_r_n & plt_w_n;\r
- dbg_p_oam_ce_rn_wn <= p_oam_ram_ce_n & p_oam_r_n & p_oam_w_n;\r
- dbg_p_oam_addr <= p_oam_addr;\r
- dbg_p_oam_data <= p_oam_data;\r
- dbg_s_oam_ce_rn_wn <= s_oam_ram_ce_n & s_oam_r_n & s_oam_w_n;\r
- dbg_s_oam_addr <= s_oam_addr;\r
- dbg_s_oam_data <= s_oam_data;\r
\r
-----------------------------------------\r
---vram access signals\r
'1';\r
v_bus_busy_n <= ah_oe_n;\r
\r
+\r
-----------------------------------------\r
--vram i/o\r
-----------------------------------------\r
vram_a_buf : tri_state_buffer generic map (6)\r
port map (ah_oe_n, vram_addr(asize - 1 downto dsize), vram_a);\r
\r
+\r
+ -----------------------------------------\r
+ ---palette ram\r
+ -----------------------------------------\r
+ r_n <= not r_nw;\r
+\r
+ plt_ram_ce_n_in <= '0' when plt_bus_ce_n = '0' and r_nw = '0' else \r
+ '0' when plt_bus_ce_n = '0' and r_nw = '1' else\r
+ '0' when ppu_mask(PPUSBG) = '1' and \r
+ (nes_x < conv_std_logic_vector(HSCAN, X_SIZE)) and \r
+ (nes_y < conv_std_logic_vector(VSCAN, X_SIZE)) else\r
+ '1';\r
+\r
+ plt_addr <= oam_plt_addr(4 downto 0) when plt_bus_ce_n = '0' else\r
+ "1" & spr_attr(0)(1 downto 0) & spr_ptn_h(0)(0) & spr_ptn_l(0)(0)\r
+ when ppu_mask(PPUSSP) = '1' and\r
+ (nes_x < conv_std_logic_vector(HSCAN, X_SIZE)) and\r
+ (nes_y < conv_std_logic_vector(VSCAN, X_SIZE)) and\r
+ spr_x_cnt(0) = "00000000" and \r
+ (spr_ptn_h(0)(0) or spr_ptn_l(0)(0)) = '1' else\r
+ "1" & spr_attr(1)(1 downto 0) & spr_ptn_h(1)(0) & spr_ptn_l(1)(0)\r
+ when ppu_mask(PPUSSP) = '1' and\r
+ (nes_x < conv_std_logic_vector(HSCAN, X_SIZE)) and\r
+ (nes_y < conv_std_logic_vector(VSCAN, X_SIZE)) and\r
+ spr_x_cnt(1) = "00000000" and \r
+ (spr_ptn_h(1)(0) or spr_ptn_l(1)(0)) = '1' else\r
+ "1" & spr_attr(2)(1 downto 0) & spr_ptn_h(2)(0) & spr_ptn_l(2)(0)\r
+ when ppu_mask(PPUSSP) = '1' and \r
+ (nes_x < conv_std_logic_vector(HSCAN, X_SIZE)) and\r
+ (nes_y < conv_std_logic_vector(VSCAN, X_SIZE)) and\r
+ spr_x_cnt(2) = "00000000" and\r
+ (spr_ptn_h(2)(0) or spr_ptn_l(2)(0)) = '1' else\r
+ "1" & spr_attr(3)(1 downto 0) & spr_ptn_h(3)(0) & spr_ptn_l(3)(0)\r
+ when ppu_mask(PPUSSP) = '1' and\r
+ (nes_x < conv_std_logic_vector(HSCAN, X_SIZE)) and\r
+ (nes_y < conv_std_logic_vector(VSCAN, X_SIZE)) and\r
+ spr_x_cnt(3) = "00000000" and\r
+ (spr_ptn_h(3)(0) or spr_ptn_l(3)(0)) = '1' else\r
+ "1" & spr_attr(4)(1 downto 0) & spr_ptn_h(4)(0) & spr_ptn_l(4)(0)\r
+ when ppu_mask(PPUSSP) = '1' and\r
+ (nes_x < conv_std_logic_vector(HSCAN, X_SIZE)) and\r
+ (nes_y < conv_std_logic_vector(VSCAN, X_SIZE)) and\r
+ spr_x_cnt(4) = "00000000" and\r
+ (spr_ptn_h(4)(0) or spr_ptn_l(4)(0)) = '1' else\r
+ "1" & spr_attr(5)(1 downto 0) & spr_ptn_h(5)(0) & spr_ptn_l(5)(0)\r
+ when ppu_mask(PPUSSP) = '1' and\r
+ (nes_x < conv_std_logic_vector(HSCAN, X_SIZE)) and\r
+ (nes_y < conv_std_logic_vector(VSCAN, X_SIZE)) and\r
+ spr_x_cnt(5) = "00000000" and\r
+ (spr_ptn_h(5)(0) or spr_ptn_l(5)(0)) = '1' else\r
+ "1" & spr_attr(6)(1 downto 0) & spr_ptn_h(6)(0) & spr_ptn_l(6)(0)\r
+ when ppu_mask(PPUSSP) = '1' and\r
+ (nes_x < conv_std_logic_vector(HSCAN, X_SIZE)) and\r
+ (nes_y < conv_std_logic_vector(VSCAN, X_SIZE)) and\r
+ spr_x_cnt(6) = "00000000" and\r
+ (spr_ptn_h(6)(0) or spr_ptn_l(6)(0)) = '1' else\r
+ "1" & spr_attr(7)(1 downto 0) & spr_ptn_h(7)(0) & spr_ptn_l(7)(0)\r
+ when ppu_mask(PPUSSP) = '1' and\r
+ (nes_x < conv_std_logic_vector(HSCAN, X_SIZE)) and\r
+ (nes_y < conv_std_logic_vector(VSCAN, X_SIZE)) and\r
+ spr_x_cnt(7) = "00000000" and\r
+ (spr_ptn_h(7)(0) or spr_ptn_l(7)(0)) = '1' else\r
+ "0" & disp_attr(1 downto 0) & disp_ptn_h(0) & disp_ptn_l(0) \r
+ when ppu_mask(PPUSBG) = '1' and nes_y(4) = '0' and\r
+ ((disp_ptn_h(0) or disp_ptn_l(0)) = '1') and\r
+ (nes_x < conv_std_logic_vector(HSCAN, X_SIZE)) and\r
+ (nes_y < conv_std_logic_vector(VSCAN, X_SIZE)) else\r
+ "0" & disp_attr(5 downto 4) & disp_ptn_h(0) & disp_ptn_l(0)\r
+ when ppu_mask(PPUSBG) = '1' and nes_y(4) = '1' and\r
+ ((disp_ptn_h(0) or disp_ptn_l(0)) = '1') and\r
+ (nes_x < conv_std_logic_vector(HSCAN, X_SIZE)) and\r
+ (nes_y < conv_std_logic_vector(VSCAN, X_SIZE)) else\r
+ ---else: no output color >> universal bg color output.\r
+ --0x3f00 is the universal bg palette.\r
+ (others => '0'); \r
+\r
+ plt_r_n <= not r_nw when plt_bus_ce_n = '0' else\r
+ '0' when ppu_mask(PPUSBG) = '1' else\r
+ '1';\r
+ plt_w_n <= r_nw when plt_bus_ce_n = '0' else\r
+ '1';\r
+ plt_d_buf_w : tri_state_buffer generic map (dsize)\r
+ port map (plt_w_n, oam_plt_data, plt_data);\r
+ plt_d_buf_r : tri_state_buffer generic map (dsize)\r
+ port map (plt_r_n, plt_data, oam_plt_data);\r
+ plt_ram_ctl : ram_ctrl generic map (1)\r
+ port map (mem_clk, plt_ram_ce_n_in, plt_r_n, plt_w_n, plt_ram_ce_n);\r
+ palette_inst : palette_ram generic map (5, dsize)\r
+ port map (mem_clk, plt_ram_ce_n, plt_r_n, plt_w_n, plt_addr, plt_data);\r
+\r
+\r
-----------------------------------------\r
---primary oam implementation...\r
-----------------------------------------\r
port map (emu_ppu_clk_n, rst_n, spr_ptn_ce_n(i), spr_ptn_h_we_n(i), spr_ptn_in, spr_ptn_h(i));\r
end generate;\r
\r
- -----------------------------------------\r
- ---palette ram\r
- -----------------------------------------\r
- r_n <= not r_nw;\r
-\r
- plt_ram_ce_n_in <= '0' when plt_bus_ce_n = '0' and r_nw = '0' else \r
- '0' when plt_bus_ce_n = '0' and r_nw = '1' else\r
- '0' when ppu_mask(PPUSBG) = '1' and \r
- (nes_x < conv_std_logic_vector(HSCAN, X_SIZE)) and \r
- (nes_y < conv_std_logic_vector(VSCAN, X_SIZE)) else\r
- '1';\r
-\r
- plt_addr <= oam_plt_addr(4 downto 0) when plt_bus_ce_n = '0' else\r
- "1" & spr_attr(0)(1 downto 0) & spr_ptn_h(0)(0) & spr_ptn_l(0)(0)\r
- when ppu_mask(PPUSSP) = '1' and\r
- (nes_x < conv_std_logic_vector(HSCAN, X_SIZE)) and\r
- (nes_y < conv_std_logic_vector(VSCAN, X_SIZE)) and\r
- spr_x_cnt(0) = "00000000" and \r
- (spr_ptn_h(0)(0) or spr_ptn_l(0)(0)) = '1' else\r
- "1" & spr_attr(1)(1 downto 0) & spr_ptn_h(1)(0) & spr_ptn_l(1)(0)\r
- when ppu_mask(PPUSSP) = '1' and\r
- (nes_x < conv_std_logic_vector(HSCAN, X_SIZE)) and\r
- (nes_y < conv_std_logic_vector(VSCAN, X_SIZE)) and\r
- spr_x_cnt(1) = "00000000" and \r
- (spr_ptn_h(1)(0) or spr_ptn_l(1)(0)) = '1' else\r
- "1" & spr_attr(2)(1 downto 0) & spr_ptn_h(2)(0) & spr_ptn_l(2)(0)\r
- when ppu_mask(PPUSSP) = '1' and \r
- (nes_x < conv_std_logic_vector(HSCAN, X_SIZE)) and\r
- (nes_y < conv_std_logic_vector(VSCAN, X_SIZE)) and\r
- spr_x_cnt(2) = "00000000" and\r
- (spr_ptn_h(2)(0) or spr_ptn_l(2)(0)) = '1' else\r
- "1" & spr_attr(3)(1 downto 0) & spr_ptn_h(3)(0) & spr_ptn_l(3)(0)\r
- when ppu_mask(PPUSSP) = '1' and\r
- (nes_x < conv_std_logic_vector(HSCAN, X_SIZE)) and\r
- (nes_y < conv_std_logic_vector(VSCAN, X_SIZE)) and\r
- spr_x_cnt(3) = "00000000" and\r
- (spr_ptn_h(3)(0) or spr_ptn_l(3)(0)) = '1' else\r
- "1" & spr_attr(4)(1 downto 0) & spr_ptn_h(4)(0) & spr_ptn_l(4)(0)\r
- when ppu_mask(PPUSSP) = '1' and\r
- (nes_x < conv_std_logic_vector(HSCAN, X_SIZE)) and\r
- (nes_y < conv_std_logic_vector(VSCAN, X_SIZE)) and\r
- spr_x_cnt(4) = "00000000" and\r
- (spr_ptn_h(4)(0) or spr_ptn_l(4)(0)) = '1' else\r
- "1" & spr_attr(5)(1 downto 0) & spr_ptn_h(5)(0) & spr_ptn_l(5)(0)\r
- when ppu_mask(PPUSSP) = '1' and\r
- (nes_x < conv_std_logic_vector(HSCAN, X_SIZE)) and\r
- (nes_y < conv_std_logic_vector(VSCAN, X_SIZE)) and\r
- spr_x_cnt(5) = "00000000" and\r
- (spr_ptn_h(5)(0) or spr_ptn_l(5)(0)) = '1' else\r
- "1" & spr_attr(6)(1 downto 0) & spr_ptn_h(6)(0) & spr_ptn_l(6)(0)\r
- when ppu_mask(PPUSSP) = '1' and\r
- (nes_x < conv_std_logic_vector(HSCAN, X_SIZE)) and\r
- (nes_y < conv_std_logic_vector(VSCAN, X_SIZE)) and\r
- spr_x_cnt(6) = "00000000" and\r
- (spr_ptn_h(6)(0) or spr_ptn_l(6)(0)) = '1' else\r
- "1" & spr_attr(7)(1 downto 0) & spr_ptn_h(7)(0) & spr_ptn_l(7)(0)\r
- when ppu_mask(PPUSSP) = '1' and\r
- (nes_x < conv_std_logic_vector(HSCAN, X_SIZE)) and\r
- (nes_y < conv_std_logic_vector(VSCAN, X_SIZE)) and\r
- spr_x_cnt(7) = "00000000" and\r
- (spr_ptn_h(7)(0) or spr_ptn_l(7)(0)) = '1' else\r
- "0" & disp_attr(1 downto 0) & disp_ptn_h(0) & disp_ptn_l(0) \r
- when ppu_mask(PPUSBG) = '1' and nes_y(4) = '0' and\r
- ((disp_ptn_h(0) or disp_ptn_l(0)) = '1') and\r
- (nes_x < conv_std_logic_vector(HSCAN, X_SIZE)) and\r
- (nes_y < conv_std_logic_vector(VSCAN, X_SIZE)) else\r
- "0" & disp_attr(5 downto 4) & disp_ptn_h(0) & disp_ptn_l(0)\r
- when ppu_mask(PPUSBG) = '1' and nes_y(4) = '1' and\r
- ((disp_ptn_h(0) or disp_ptn_l(0)) = '1') and\r
- (nes_x < conv_std_logic_vector(HSCAN, X_SIZE)) and\r
- (nes_y < conv_std_logic_vector(VSCAN, X_SIZE)) else\r
- ---else: no output color >> universal bg color output.\r
- --0x3f00 is the universal bg palette.\r
- (others => '0'); \r
-\r
- plt_r_n <= not r_nw when plt_bus_ce_n = '0' else\r
- '0' when ppu_mask(PPUSBG) = '1' else\r
- '1';\r
- plt_w_n <= r_nw when plt_bus_ce_n = '0' else\r
- '1';\r
- plt_d_buf_w : tri_state_buffer generic map (dsize)\r
- port map (plt_w_n, oam_plt_data, plt_data);\r
- plt_d_buf_r : tri_state_buffer generic map (dsize)\r
- port map (plt_r_n, plt_data, oam_plt_data);\r
- plt_ram_ctl : ram_ctrl generic map (1)\r
- port map (mem_clk, plt_ram_ce_n_in, plt_r_n, plt_w_n, plt_ram_ce_n);\r
- palette_inst : palette_ram generic map (5, dsize)\r
- port map (mem_clk, plt_ram_ce_n, plt_r_n, plt_w_n, plt_addr, plt_data);\r
\r
-----------------------------------------\r
---sprite main process\r
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