2 * Driver for (BCM4706)? GBit MAC core on BCMA bus.
4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
6 * Licensed under the GNU/GPL. See COPYING for details.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/phy.h>
17 #include <linux/phy_fixed.h>
18 #include <linux/interrupt.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/bcm47xx_nvram.h>
22 static const struct bcma_device_id bgmac_bcma_tbl[] = {
23 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
24 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
27 MODULE_DEVICE_TABLE(bcma, bgmac_bcma_tbl);
29 static bool bgmac_wait_value(struct bcma_device *core, u16 reg, u32 mask,
30 u32 value, int timeout)
35 for (i = 0; i < timeout / 10; i++) {
36 val = bcma_read32(core, reg);
37 if ((val & mask) == value)
41 pr_err("Timeout waiting for reg 0x%X\n", reg);
45 /**************************************************
47 **************************************************/
49 static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
57 /* Suspend DMA TX ring first.
58 * bgmac_wait_value doesn't support waiting for any of few values, so
59 * implement whole loop here.
61 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL,
62 BGMAC_DMA_TX_SUSPEND);
63 for (i = 0; i < 10000 / 10; i++) {
64 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
65 val &= BGMAC_DMA_TX_STAT;
66 if (val == BGMAC_DMA_TX_STAT_DISABLED ||
67 val == BGMAC_DMA_TX_STAT_IDLEWAIT ||
68 val == BGMAC_DMA_TX_STAT_STOPPED) {
75 bgmac_err(bgmac, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
76 ring->mmio_base, val);
78 /* Remove SUSPEND bit */
79 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0);
80 if (!bgmac_wait_value(bgmac->core,
81 ring->mmio_base + BGMAC_DMA_TX_STATUS,
82 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED,
84 bgmac_warn(bgmac, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
87 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
88 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED)
89 bgmac_err(bgmac, "Reset of DMA TX ring 0x%X failed\n",
94 static void bgmac_dma_tx_enable(struct bgmac *bgmac,
95 struct bgmac_dma_ring *ring)
99 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
100 if (bgmac->core->id.rev >= 4) {
101 ctl &= ~BGMAC_DMA_TX_BL_MASK;
102 ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
104 ctl &= ~BGMAC_DMA_TX_MR_MASK;
105 ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
107 ctl &= ~BGMAC_DMA_TX_PC_MASK;
108 ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
110 ctl &= ~BGMAC_DMA_TX_PT_MASK;
111 ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
113 ctl |= BGMAC_DMA_TX_ENABLE;
114 ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
115 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
119 bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
120 int i, int len, u32 ctl0)
122 struct bgmac_slot_info *slot;
123 struct bgmac_dma_desc *dma_desc;
126 if (i == BGMAC_TX_RING_SLOTS - 1)
127 ctl0 |= BGMAC_DESC_CTL0_EOT;
129 ctl1 = len & BGMAC_DESC_CTL1_LEN;
131 slot = &ring->slots[i];
132 dma_desc = &ring->cpu_base[i];
133 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr));
134 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr));
135 dma_desc->ctl0 = cpu_to_le32(ctl0);
136 dma_desc->ctl1 = cpu_to_le32(ctl1);
139 static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac,
140 struct bgmac_dma_ring *ring,
143 struct device *dma_dev = bgmac->core->dma_dev;
144 struct net_device *net_dev = bgmac->net_dev;
145 int index = ring->end % BGMAC_TX_RING_SLOTS;
146 struct bgmac_slot_info *slot = &ring->slots[index];
151 if (skb->len > BGMAC_DESC_CTL1_LEN) {
152 bgmac_err(bgmac, "Too long skb (%d)\n", skb->len);
156 if (skb->ip_summed == CHECKSUM_PARTIAL)
157 skb_checksum_help(skb);
159 nr_frags = skb_shinfo(skb)->nr_frags;
161 /* ring->end - ring->start will return the number of valid slots,
162 * even when ring->end overflows
164 if (ring->end - ring->start + nr_frags + 1 >= BGMAC_TX_RING_SLOTS) {
165 bgmac_err(bgmac, "TX ring is full, queue should be stopped!\n");
166 netif_stop_queue(net_dev);
167 return NETDEV_TX_BUSY;
170 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb),
172 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
175 flags = BGMAC_DESC_CTL0_SOF;
177 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
179 bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags);
182 for (i = 0; i < nr_frags; i++) {
183 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
184 int len = skb_frag_size(frag);
186 index = (index + 1) % BGMAC_TX_RING_SLOTS;
187 slot = &ring->slots[index];
188 slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0,
190 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
193 if (i == nr_frags - 1)
194 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
196 bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags);
200 ring->end += nr_frags + 1;
201 netdev_sent_queue(net_dev, skb->len);
205 /* Increase ring->end to point empty slot. We tell hardware the first
206 * slot it should *not* read.
208 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,
210 (ring->end % BGMAC_TX_RING_SLOTS) *
211 sizeof(struct bgmac_dma_desc));
213 if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8)
214 netif_stop_queue(net_dev);
219 dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb),
223 int index = (ring->end + i) % BGMAC_TX_RING_SLOTS;
224 struct bgmac_slot_info *slot = &ring->slots[index];
225 u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1);
226 int len = ctl1 & BGMAC_DESC_CTL1_LEN;
228 dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE);
232 bgmac_err(bgmac, "Mapping error of skb on ring 0x%X\n",
240 /* Free transmitted packets */
241 static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
243 struct device *dma_dev = bgmac->core->dma_dev;
246 unsigned bytes_compl = 0, pkts_compl = 0;
248 /* The last slot that hardware didn't consume yet */
249 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
250 empty_slot &= BGMAC_DMA_TX_STATDPTR;
251 empty_slot -= ring->index_base;
252 empty_slot &= BGMAC_DMA_TX_STATDPTR;
253 empty_slot /= sizeof(struct bgmac_dma_desc);
255 while (ring->start != ring->end) {
256 int slot_idx = ring->start % BGMAC_TX_RING_SLOTS;
257 struct bgmac_slot_info *slot = &ring->slots[slot_idx];
261 if (slot_idx == empty_slot)
264 ctl0 = le32_to_cpu(ring->cpu_base[slot_idx].ctl0);
265 ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1);
266 len = ctl1 & BGMAC_DESC_CTL1_LEN;
267 if (ctl0 & BGMAC_DESC_CTL0_SOF)
268 /* Unmap no longer used buffer */
269 dma_unmap_single(dma_dev, slot->dma_addr, len,
272 dma_unmap_page(dma_dev, slot->dma_addr, len,
276 bytes_compl += slot->skb->len;
279 /* Free memory! :) */
280 dev_kfree_skb(slot->skb);
292 netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl);
294 if (netif_queue_stopped(bgmac->net_dev))
295 netif_wake_queue(bgmac->net_dev);
298 static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
300 if (!ring->mmio_base)
303 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0);
304 if (!bgmac_wait_value(bgmac->core,
305 ring->mmio_base + BGMAC_DMA_RX_STATUS,
306 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED,
308 bgmac_err(bgmac, "Reset of ring 0x%X RX failed\n",
312 static void bgmac_dma_rx_enable(struct bgmac *bgmac,
313 struct bgmac_dma_ring *ring)
317 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
319 /* preserve ONLY bits 16-17 from current hardware value */
320 ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
322 if (bgmac->core->id.rev >= 4) {
323 ctl &= ~BGMAC_DMA_RX_BL_MASK;
324 ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
326 ctl &= ~BGMAC_DMA_RX_PC_MASK;
327 ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
329 ctl &= ~BGMAC_DMA_RX_PT_MASK;
330 ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
332 ctl |= BGMAC_DMA_RX_ENABLE;
333 ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
334 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
335 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
336 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
339 static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac,
340 struct bgmac_slot_info *slot)
342 struct device *dma_dev = bgmac->core->dma_dev;
344 struct bgmac_rx_header *rx;
348 buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE);
352 /* Poison - if everything goes fine, hardware will overwrite it */
353 rx = buf + BGMAC_RX_BUF_OFFSET;
354 rx->len = cpu_to_le16(0xdead);
355 rx->flags = cpu_to_le16(0xbeef);
357 /* Map skb for the DMA */
358 dma_addr = dma_map_single(dma_dev, buf + BGMAC_RX_BUF_OFFSET,
359 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
360 if (dma_mapping_error(dma_dev, dma_addr)) {
361 bgmac_err(bgmac, "DMA mapping error\n");
362 put_page(virt_to_head_page(buf));
366 /* Update the slot */
368 slot->dma_addr = dma_addr;
373 static void bgmac_dma_rx_update_index(struct bgmac *bgmac,
374 struct bgmac_dma_ring *ring)
378 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
380 ring->end * sizeof(struct bgmac_dma_desc));
383 static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac,
384 struct bgmac_dma_ring *ring, int desc_idx)
386 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx;
387 u32 ctl0 = 0, ctl1 = 0;
389 if (desc_idx == BGMAC_RX_RING_SLOTS - 1)
390 ctl0 |= BGMAC_DESC_CTL0_EOT;
391 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN;
392 /* Is there any BGMAC device that requires extension? */
393 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) &
394 * B43_DMA64_DCTL1_ADDREXT_MASK;
397 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr));
398 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr));
399 dma_desc->ctl0 = cpu_to_le32(ctl0);
400 dma_desc->ctl1 = cpu_to_le32(ctl1);
402 ring->end = desc_idx;
405 static void bgmac_dma_rx_poison_buf(struct device *dma_dev,
406 struct bgmac_slot_info *slot)
408 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
410 dma_sync_single_for_cpu(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
412 rx->len = cpu_to_le16(0xdead);
413 rx->flags = cpu_to_le16(0xbeef);
414 dma_sync_single_for_device(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
418 static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
424 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
425 end_slot &= BGMAC_DMA_RX_STATDPTR;
426 end_slot -= ring->index_base;
427 end_slot &= BGMAC_DMA_RX_STATDPTR;
428 end_slot /= sizeof(struct bgmac_dma_desc);
430 while (ring->start != end_slot) {
431 struct device *dma_dev = bgmac->core->dma_dev;
432 struct bgmac_slot_info *slot = &ring->slots[ring->start];
433 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
435 void *buf = slot->buf;
436 dma_addr_t dma_addr = slot->dma_addr;
440 /* Prepare new skb as replacement */
441 if (bgmac_dma_rx_skb_for_slot(bgmac, slot)) {
442 bgmac_dma_rx_poison_buf(dma_dev, slot);
446 /* Unmap buffer to make it accessible to the CPU */
447 dma_unmap_single(dma_dev, dma_addr,
448 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
450 /* Get info from the header */
451 len = le16_to_cpu(rx->len);
452 flags = le16_to_cpu(rx->flags);
454 /* Check for poison and drop or pass the packet */
455 if (len == 0xdead && flags == 0xbeef) {
456 bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n",
458 put_page(virt_to_head_page(buf));
462 if (len > BGMAC_RX_ALLOC_SIZE) {
463 bgmac_err(bgmac, "Found oversized packet at slot %d, DMA issue!\n",
465 put_page(virt_to_head_page(buf));
472 skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE);
473 if (unlikely(!skb)) {
474 bgmac_err(bgmac, "build_skb failed\n");
475 put_page(virt_to_head_page(buf));
478 skb_put(skb, BGMAC_RX_FRAME_OFFSET +
479 BGMAC_RX_BUF_OFFSET + len);
480 skb_pull(skb, BGMAC_RX_FRAME_OFFSET +
481 BGMAC_RX_BUF_OFFSET);
483 skb_checksum_none_assert(skb);
484 skb->protocol = eth_type_trans(skb, bgmac->net_dev);
485 napi_gro_receive(&bgmac->napi, skb);
489 bgmac_dma_rx_setup_desc(bgmac, ring, ring->start);
491 if (++ring->start >= BGMAC_RX_RING_SLOTS)
494 if (handled >= weight) /* Should never be greater */
498 bgmac_dma_rx_update_index(bgmac, ring);
503 /* Does ring support unaligned addressing? */
504 static bool bgmac_dma_unaligned(struct bgmac *bgmac,
505 struct bgmac_dma_ring *ring,
506 enum bgmac_dma_ring_type ring_type)
509 case BGMAC_DMA_RING_TX:
510 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
512 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO))
515 case BGMAC_DMA_RING_RX:
516 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
518 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO))
525 static void bgmac_dma_tx_ring_free(struct bgmac *bgmac,
526 struct bgmac_dma_ring *ring)
528 struct device *dma_dev = bgmac->core->dma_dev;
529 struct bgmac_dma_desc *dma_desc = ring->cpu_base;
530 struct bgmac_slot_info *slot;
533 for (i = 0; i < BGMAC_TX_RING_SLOTS; i++) {
534 int len = dma_desc[i].ctl1 & BGMAC_DESC_CTL1_LEN;
536 slot = &ring->slots[i];
537 dev_kfree_skb(slot->skb);
543 dma_unmap_single(dma_dev, slot->dma_addr,
546 dma_unmap_page(dma_dev, slot->dma_addr,
551 static void bgmac_dma_rx_ring_free(struct bgmac *bgmac,
552 struct bgmac_dma_ring *ring)
554 struct device *dma_dev = bgmac->core->dma_dev;
555 struct bgmac_slot_info *slot;
558 for (i = 0; i < BGMAC_RX_RING_SLOTS; i++) {
559 slot = &ring->slots[i];
563 dma_unmap_single(dma_dev, slot->dma_addr,
566 put_page(virt_to_head_page(slot->buf));
571 static void bgmac_dma_ring_desc_free(struct bgmac *bgmac,
572 struct bgmac_dma_ring *ring,
575 struct device *dma_dev = bgmac->core->dma_dev;
581 /* Free ring of descriptors */
582 size = num_slots * sizeof(struct bgmac_dma_desc);
583 dma_free_coherent(dma_dev, size, ring->cpu_base,
587 static void bgmac_dma_cleanup(struct bgmac *bgmac)
591 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
592 bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]);
594 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
595 bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]);
598 static void bgmac_dma_free(struct bgmac *bgmac)
602 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
603 bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i],
604 BGMAC_TX_RING_SLOTS);
606 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
607 bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i],
608 BGMAC_RX_RING_SLOTS);
611 static int bgmac_dma_alloc(struct bgmac *bgmac)
613 struct device *dma_dev = bgmac->core->dma_dev;
614 struct bgmac_dma_ring *ring;
615 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1,
616 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, };
617 int size; /* ring size: different for Tx and Rx */
621 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base));
622 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base));
624 if (!(bcma_aread32(bgmac->core, BCMA_IOST) & BCMA_IOST_DMA64)) {
625 bgmac_err(bgmac, "Core does not report 64-bit DMA\n");
629 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
630 ring = &bgmac->tx_ring[i];
631 ring->mmio_base = ring_base[i];
633 /* Alloc ring of descriptors */
634 size = BGMAC_TX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
635 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
638 if (!ring->cpu_base) {
639 bgmac_err(bgmac, "Allocation of TX ring 0x%X failed\n",
644 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
647 ring->index_base = lower_32_bits(ring->dma_base);
649 ring->index_base = 0;
651 /* No need to alloc TX slots yet */
654 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
655 ring = &bgmac->rx_ring[i];
656 ring->mmio_base = ring_base[i];
658 /* Alloc ring of descriptors */
659 size = BGMAC_RX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
660 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
663 if (!ring->cpu_base) {
664 bgmac_err(bgmac, "Allocation of RX ring 0x%X failed\n",
670 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
673 ring->index_base = lower_32_bits(ring->dma_base);
675 ring->index_base = 0;
681 bgmac_dma_free(bgmac);
685 static int bgmac_dma_init(struct bgmac *bgmac)
687 struct bgmac_dma_ring *ring;
690 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
691 ring = &bgmac->tx_ring[i];
693 if (!ring->unaligned)
694 bgmac_dma_tx_enable(bgmac, ring);
695 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
696 lower_32_bits(ring->dma_base));
697 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,
698 upper_32_bits(ring->dma_base));
700 bgmac_dma_tx_enable(bgmac, ring);
703 ring->end = 0; /* Points the slot that should *not* be read */
706 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
709 ring = &bgmac->rx_ring[i];
711 if (!ring->unaligned)
712 bgmac_dma_rx_enable(bgmac, ring);
713 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
714 lower_32_bits(ring->dma_base));
715 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,
716 upper_32_bits(ring->dma_base));
718 bgmac_dma_rx_enable(bgmac, ring);
722 for (j = 0; j < BGMAC_RX_RING_SLOTS; j++) {
723 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]);
727 bgmac_dma_rx_setup_desc(bgmac, ring, j);
730 bgmac_dma_rx_update_index(bgmac, ring);
736 bgmac_dma_cleanup(bgmac);
740 /**************************************************
742 **************************************************/
744 static u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg)
746 struct bcma_device *core;
751 BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK);
752 BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK);
753 BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT);
754 BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK);
755 BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT);
756 BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE);
757 BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START);
758 BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK);
759 BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK);
760 BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT);
761 BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE);
763 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
764 core = bgmac->core->bus->drv_gmac_cmn.core;
765 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
766 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
769 phy_access_addr = BGMAC_PHY_ACCESS;
770 phy_ctl_addr = BGMAC_PHY_CNTL;
773 tmp = bcma_read32(core, phy_ctl_addr);
774 tmp &= ~BGMAC_PC_EPA_MASK;
776 bcma_write32(core, phy_ctl_addr, tmp);
778 tmp = BGMAC_PA_START;
779 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
780 tmp |= reg << BGMAC_PA_REG_SHIFT;
781 bcma_write32(core, phy_access_addr, tmp);
783 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
784 bgmac_err(bgmac, "Reading PHY %d register 0x%X failed\n",
789 return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK;
792 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */
793 static int bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value)
795 struct bcma_device *core;
800 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
801 core = bgmac->core->bus->drv_gmac_cmn.core;
802 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
803 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
806 phy_access_addr = BGMAC_PHY_ACCESS;
807 phy_ctl_addr = BGMAC_PHY_CNTL;
810 tmp = bcma_read32(core, phy_ctl_addr);
811 tmp &= ~BGMAC_PC_EPA_MASK;
813 bcma_write32(core, phy_ctl_addr, tmp);
815 bgmac_write(bgmac, BGMAC_INT_STATUS, BGMAC_IS_MDIO);
816 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & BGMAC_IS_MDIO)
817 bgmac_warn(bgmac, "Error setting MDIO int\n");
819 tmp = BGMAC_PA_START;
820 tmp |= BGMAC_PA_WRITE;
821 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
822 tmp |= reg << BGMAC_PA_REG_SHIFT;
824 bcma_write32(core, phy_access_addr, tmp);
826 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
827 bgmac_err(bgmac, "Writing to PHY %d register 0x%X failed\n",
835 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */
836 static void bgmac_phy_init(struct bgmac *bgmac)
838 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
839 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
842 if (ci->id == BCMA_CHIP_ID_BCM5356) {
843 for (i = 0; i < 5; i++) {
844 bgmac_phy_write(bgmac, i, 0x1f, 0x008b);
845 bgmac_phy_write(bgmac, i, 0x15, 0x0100);
846 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
847 bgmac_phy_write(bgmac, i, 0x12, 0x2aaa);
848 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
851 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) ||
852 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) ||
853 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) {
854 bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0);
855 bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0);
856 for (i = 0; i < 5; i++) {
857 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
858 bgmac_phy_write(bgmac, i, 0x16, 0x5284);
859 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
860 bgmac_phy_write(bgmac, i, 0x17, 0x0010);
861 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
862 bgmac_phy_write(bgmac, i, 0x16, 0x5296);
863 bgmac_phy_write(bgmac, i, 0x17, 0x1073);
864 bgmac_phy_write(bgmac, i, 0x17, 0x9073);
865 bgmac_phy_write(bgmac, i, 0x16, 0x52b6);
866 bgmac_phy_write(bgmac, i, 0x17, 0x9273);
867 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
872 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */
873 static void bgmac_phy_reset(struct bgmac *bgmac)
875 if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
878 bgmac_phy_write(bgmac, bgmac->phyaddr, MII_BMCR, BMCR_RESET);
880 if (bgmac_phy_read(bgmac, bgmac->phyaddr, MII_BMCR) & BMCR_RESET)
881 bgmac_err(bgmac, "PHY reset failed\n");
882 bgmac_phy_init(bgmac);
885 /**************************************************
887 **************************************************/
889 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is
890 * nothing to change? Try if after stabilizng driver.
892 static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set,
895 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
896 u32 new_val = (cmdcfg & mask) | set;
898 bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev));
901 if (new_val != cmdcfg || force)
902 bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
904 bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev));
908 static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr)
912 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
913 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp);
914 tmp = (addr[4] << 8) | addr[5];
915 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp);
918 static void bgmac_set_rx_mode(struct net_device *net_dev)
920 struct bgmac *bgmac = netdev_priv(net_dev);
922 if (net_dev->flags & IFF_PROMISC)
923 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true);
925 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true);
928 #if 0 /* We don't use that regs yet */
929 static void bgmac_chip_stats_update(struct bgmac *bgmac)
933 if (bgmac->core->id.id != BCMA_CORE_4706_MAC_GBIT) {
934 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
935 bgmac->mib_tx_regs[i] =
937 BGMAC_TX_GOOD_OCTETS + (i * 4));
938 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
939 bgmac->mib_rx_regs[i] =
941 BGMAC_RX_GOOD_OCTETS + (i * 4));
944 /* TODO: what else? how to handle BCM4706? Specs are needed */
948 static void bgmac_clear_mib(struct bgmac *bgmac)
952 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT)
955 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR);
956 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
957 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4));
958 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
959 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4));
962 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
963 static void bgmac_mac_speed(struct bgmac *bgmac)
965 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD);
968 switch (bgmac->mac_speed) {
970 set |= BGMAC_CMDCFG_ES_10;
973 set |= BGMAC_CMDCFG_ES_100;
976 set |= BGMAC_CMDCFG_ES_1000;
979 set |= BGMAC_CMDCFG_ES_2500;
982 bgmac_err(bgmac, "Unsupported speed: %d\n", bgmac->mac_speed);
985 if (bgmac->mac_duplex == DUPLEX_HALF)
986 set |= BGMAC_CMDCFG_HD;
988 bgmac_cmdcfg_maskset(bgmac, mask, set, true);
991 static void bgmac_miiconfig(struct bgmac *bgmac)
993 struct bcma_device *core = bgmac->core;
994 struct bcma_chipinfo *ci = &core->bus->chipinfo;
997 if (ci->id == BCMA_CHIP_ID_BCM4707 ||
998 ci->id == BCMA_CHIP_ID_BCM53018) {
999 bcma_awrite32(core, BCMA_IOCTL,
1000 bcma_aread32(core, BCMA_IOCTL) | 0x40 |
1001 BGMAC_BCMA_IOCTL_SW_CLKEN);
1002 bgmac->mac_speed = SPEED_2500;
1003 bgmac->mac_duplex = DUPLEX_FULL;
1004 bgmac_mac_speed(bgmac);
1006 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
1007 BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
1008 if (imode == 0 || imode == 1) {
1009 bgmac->mac_speed = SPEED_100;
1010 bgmac->mac_duplex = DUPLEX_FULL;
1011 bgmac_mac_speed(bgmac);
1016 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */
1017 static void bgmac_chip_reset(struct bgmac *bgmac)
1019 struct bcma_device *core = bgmac->core;
1020 struct bcma_bus *bus = core->bus;
1021 struct bcma_chipinfo *ci = &bus->chipinfo;
1026 if (bcma_core_is_enabled(core)) {
1027 if (!bgmac->stats_grabbed) {
1028 /* bgmac_chip_stats_update(bgmac); */
1029 bgmac->stats_grabbed = true;
1032 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
1033 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]);
1035 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
1038 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
1039 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]);
1041 /* TODO: Clear software multicast filter list */
1044 iost = bcma_aread32(core, BCMA_IOST);
1045 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) ||
1046 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
1047 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188))
1048 iost &= ~BGMAC_BCMA_IOST_ATTACHED;
1050 /* 3GMAC: for BCM4707, only do core reset at bgmac_probe() */
1051 if (ci->id != BCMA_CHIP_ID_BCM4707) {
1053 if (iost & BGMAC_BCMA_IOST_ATTACHED) {
1054 flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
1055 if (!bgmac->has_robosw)
1056 flags |= BGMAC_BCMA_IOCTL_SW_RESET;
1058 bcma_core_enable(core, flags);
1061 /* Request Misc PLL for corerev > 2 */
1062 if (core->id.rev > 2 &&
1063 ci->id != BCMA_CHIP_ID_BCM4707 &&
1064 ci->id != BCMA_CHIP_ID_BCM53018) {
1065 bgmac_set(bgmac, BCMA_CLKCTLST,
1066 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
1067 bgmac_wait_value(bgmac->core, BCMA_CLKCTLST,
1068 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
1069 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
1073 if (ci->id == BCMA_CHIP_ID_BCM5357 ||
1074 ci->id == BCMA_CHIP_ID_BCM4749 ||
1075 ci->id == BCMA_CHIP_ID_BCM53572) {
1076 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
1078 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
1079 BGMAC_CHIPCTL_1_IF_TYPE_MII;
1082 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
1083 if (kstrtou8(buf, 0, &et_swtype))
1084 bgmac_err(bgmac, "Failed to parse et_swtype (%s)\n",
1088 sw_type = et_swtype;
1089 } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM5358) {
1090 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
1091 } else if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) ||
1092 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
1093 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) {
1094 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
1095 BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
1097 bcma_chipco_chipctl_maskset(cc, 1,
1098 ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK |
1099 BGMAC_CHIPCTL_1_SW_TYPE_MASK),
1103 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw)
1104 bcma_awrite32(core, BCMA_IOCTL,
1105 bcma_aread32(core, BCMA_IOCTL) &
1106 ~BGMAC_BCMA_IOCTL_SW_RESET);
1108 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset
1109 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine
1110 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to
1111 * be keps until taking MAC out of the reset.
1113 bgmac_cmdcfg_maskset(bgmac,
1125 BGMAC_CMDCFG_PAD_EN |
1130 BGMAC_CMDCFG_SR(core->id.rev),
1132 bgmac->mac_speed = SPEED_UNKNOWN;
1133 bgmac->mac_duplex = DUPLEX_UNKNOWN;
1135 bgmac_clear_mib(bgmac);
1136 if (core->id.id == BCMA_CORE_4706_MAC_GBIT)
1137 bcma_maskset32(bgmac->cmn, BCMA_GMAC_CMN_PHY_CTL, ~0,
1138 BCMA_GMAC_CMN_PC_MTE);
1140 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE);
1141 bgmac_miiconfig(bgmac);
1142 bgmac_phy_init(bgmac);
1144 netdev_reset_queue(bgmac->net_dev);
1147 static void bgmac_chip_intrs_on(struct bgmac *bgmac)
1149 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask);
1152 static void bgmac_chip_intrs_off(struct bgmac *bgmac)
1154 bgmac_write(bgmac, BGMAC_INT_MASK, 0);
1155 bgmac_read(bgmac, BGMAC_INT_MASK);
1158 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
1159 static void bgmac_enable(struct bgmac *bgmac)
1161 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
1169 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
1170 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
1171 BGMAC_CMDCFG_SR(bgmac->core->id.rev), true);
1173 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
1174 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
1176 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
1178 if (ci->id != BCMA_CHIP_ID_BCM47162 || mode != 0)
1179 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
1180 if (ci->id == BCMA_CHIP_ID_BCM47162 && mode == 2)
1181 bcma_chipco_chipctl_maskset(&bgmac->core->bus->drv_cc, 1, ~0,
1182 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS);
1185 case BCMA_CHIP_ID_BCM5357:
1186 case BCMA_CHIP_ID_BCM4749:
1187 case BCMA_CHIP_ID_BCM53572:
1188 case BCMA_CHIP_ID_BCM4716:
1189 case BCMA_CHIP_ID_BCM47162:
1190 fl_ctl = 0x03cb04cb;
1191 if (ci->id == BCMA_CHIP_ID_BCM5357 ||
1192 ci->id == BCMA_CHIP_ID_BCM4749 ||
1193 ci->id == BCMA_CHIP_ID_BCM53572)
1195 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);
1196 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff);
1200 if (ci->id != BCMA_CHIP_ID_BCM4707 &&
1201 ci->id != BCMA_CHIP_ID_BCM53018) {
1202 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
1203 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
1204 bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) /
1206 mdp = (bp_clk * 128 / 1000) - 3;
1207 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
1208 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
1212 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
1213 static void bgmac_chip_init(struct bgmac *bgmac)
1215 /* 1 interrupt per received frame */
1216 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
1218 /* Enable 802.3x tx flow control (honor received PAUSE frames) */
1219 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true);
1221 bgmac_set_rx_mode(bgmac->net_dev);
1223 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr);
1225 if (bgmac->loopback)
1226 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
1228 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false);
1230 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
1232 bgmac_chip_intrs_on(bgmac);
1234 bgmac_enable(bgmac);
1237 static irqreturn_t bgmac_interrupt(int irq, void *dev_id)
1239 struct bgmac *bgmac = netdev_priv(dev_id);
1241 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS);
1242 int_status &= bgmac->int_mask;
1247 int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX);
1249 bgmac_err(bgmac, "Unknown IRQs: 0x%08X\n", int_status);
1251 /* Disable new interrupts until handling existing ones */
1252 bgmac_chip_intrs_off(bgmac);
1254 napi_schedule(&bgmac->napi);
1259 static int bgmac_poll(struct napi_struct *napi, int weight)
1261 struct bgmac *bgmac = container_of(napi, struct bgmac, napi);
1265 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
1267 bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]);
1268 handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight);
1270 /* Poll again if more events arrived in the meantime */
1271 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX))
1274 if (handled < weight) {
1275 napi_complete(napi);
1276 bgmac_chip_intrs_on(bgmac);
1282 /**************************************************
1284 **************************************************/
1286 static int bgmac_open(struct net_device *net_dev)
1288 struct bgmac *bgmac = netdev_priv(net_dev);
1291 bgmac_chip_reset(bgmac);
1293 err = bgmac_dma_init(bgmac);
1297 /* Specs say about reclaiming rings here, but we do that in DMA init */
1298 bgmac_chip_init(bgmac);
1300 err = request_irq(bgmac->core->irq, bgmac_interrupt, IRQF_SHARED,
1301 KBUILD_MODNAME, net_dev);
1303 bgmac_err(bgmac, "IRQ request error: %d!\n", err);
1304 bgmac_dma_cleanup(bgmac);
1307 napi_enable(&bgmac->napi);
1309 phy_start(bgmac->phy_dev);
1311 netif_start_queue(net_dev);
1316 static int bgmac_stop(struct net_device *net_dev)
1318 struct bgmac *bgmac = netdev_priv(net_dev);
1320 netif_carrier_off(net_dev);
1322 phy_stop(bgmac->phy_dev);
1324 napi_disable(&bgmac->napi);
1325 bgmac_chip_intrs_off(bgmac);
1326 free_irq(bgmac->core->irq, net_dev);
1328 bgmac_chip_reset(bgmac);
1329 bgmac_dma_cleanup(bgmac);
1334 static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb,
1335 struct net_device *net_dev)
1337 struct bgmac *bgmac = netdev_priv(net_dev);
1338 struct bgmac_dma_ring *ring;
1340 /* No QOS support yet */
1341 ring = &bgmac->tx_ring[0];
1342 return bgmac_dma_tx_add(bgmac, ring, skb);
1345 static int bgmac_set_mac_address(struct net_device *net_dev, void *addr)
1347 struct bgmac *bgmac = netdev_priv(net_dev);
1350 ret = eth_prepare_mac_addr_change(net_dev, addr);
1353 bgmac_write_mac_address(bgmac, (u8 *)addr);
1354 eth_commit_mac_addr_change(net_dev, addr);
1358 static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1360 struct bgmac *bgmac = netdev_priv(net_dev);
1362 if (!netif_running(net_dev))
1365 return phy_mii_ioctl(bgmac->phy_dev, ifr, cmd);
1368 static const struct net_device_ops bgmac_netdev_ops = {
1369 .ndo_open = bgmac_open,
1370 .ndo_stop = bgmac_stop,
1371 .ndo_start_xmit = bgmac_start_xmit,
1372 .ndo_set_rx_mode = bgmac_set_rx_mode,
1373 .ndo_set_mac_address = bgmac_set_mac_address,
1374 .ndo_validate_addr = eth_validate_addr,
1375 .ndo_do_ioctl = bgmac_ioctl,
1378 /**************************************************
1380 **************************************************/
1382 static int bgmac_get_settings(struct net_device *net_dev,
1383 struct ethtool_cmd *cmd)
1385 struct bgmac *bgmac = netdev_priv(net_dev);
1387 return phy_ethtool_gset(bgmac->phy_dev, cmd);
1390 static int bgmac_set_settings(struct net_device *net_dev,
1391 struct ethtool_cmd *cmd)
1393 struct bgmac *bgmac = netdev_priv(net_dev);
1395 return phy_ethtool_sset(bgmac->phy_dev, cmd);
1398 static void bgmac_get_drvinfo(struct net_device *net_dev,
1399 struct ethtool_drvinfo *info)
1401 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1402 strlcpy(info->bus_info, "BCMA", sizeof(info->bus_info));
1405 static const struct ethtool_ops bgmac_ethtool_ops = {
1406 .get_settings = bgmac_get_settings,
1407 .set_settings = bgmac_set_settings,
1408 .get_drvinfo = bgmac_get_drvinfo,
1411 /**************************************************
1413 **************************************************/
1415 static int bgmac_mii_read(struct mii_bus *bus, int mii_id, int regnum)
1417 return bgmac_phy_read(bus->priv, mii_id, regnum);
1420 static int bgmac_mii_write(struct mii_bus *bus, int mii_id, int regnum,
1423 return bgmac_phy_write(bus->priv, mii_id, regnum, value);
1426 static void bgmac_adjust_link(struct net_device *net_dev)
1428 struct bgmac *bgmac = netdev_priv(net_dev);
1429 struct phy_device *phy_dev = bgmac->phy_dev;
1430 bool update = false;
1432 if (phy_dev->link) {
1433 if (phy_dev->speed != bgmac->mac_speed) {
1434 bgmac->mac_speed = phy_dev->speed;
1438 if (phy_dev->duplex != bgmac->mac_duplex) {
1439 bgmac->mac_duplex = phy_dev->duplex;
1445 bgmac_mac_speed(bgmac);
1446 phy_print_status(phy_dev);
1450 static int bgmac_fixed_phy_register(struct bgmac *bgmac)
1452 struct fixed_phy_status fphy_status = {
1454 .speed = SPEED_1000,
1455 .duplex = DUPLEX_FULL,
1457 struct phy_device *phy_dev;
1460 phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
1461 if (!phy_dev || IS_ERR(phy_dev)) {
1462 bgmac_err(bgmac, "Failed to register fixed PHY device\n");
1466 err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link,
1467 PHY_INTERFACE_MODE_MII);
1469 bgmac_err(bgmac, "Connecting PHY failed\n");
1473 bgmac->phy_dev = phy_dev;
1478 static int bgmac_mii_register(struct bgmac *bgmac)
1480 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
1481 struct mii_bus *mii_bus;
1482 struct phy_device *phy_dev;
1483 char bus_id[MII_BUS_ID_SIZE + 3];
1486 if (ci->id == BCMA_CHIP_ID_BCM4707 ||
1487 ci->id == BCMA_CHIP_ID_BCM53018)
1488 return bgmac_fixed_phy_register(bgmac);
1490 mii_bus = mdiobus_alloc();
1494 mii_bus->name = "bgmac mii bus";
1495 sprintf(mii_bus->id, "%s-%d-%d", "bgmac", bgmac->core->bus->num,
1496 bgmac->core->core_unit);
1497 mii_bus->priv = bgmac;
1498 mii_bus->read = bgmac_mii_read;
1499 mii_bus->write = bgmac_mii_write;
1500 mii_bus->parent = &bgmac->core->dev;
1501 mii_bus->phy_mask = ~(1 << bgmac->phyaddr);
1503 mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
1504 if (!mii_bus->irq) {
1508 for (i = 0; i < PHY_MAX_ADDR; i++)
1509 mii_bus->irq[i] = PHY_POLL;
1511 err = mdiobus_register(mii_bus);
1513 bgmac_err(bgmac, "Registration of mii bus failed\n");
1517 bgmac->mii_bus = mii_bus;
1519 /* Connect to the PHY */
1520 snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, mii_bus->id,
1522 phy_dev = phy_connect(bgmac->net_dev, bus_id, &bgmac_adjust_link,
1523 PHY_INTERFACE_MODE_MII);
1524 if (IS_ERR(phy_dev)) {
1525 bgmac_err(bgmac, "PHY connecton failed\n");
1526 err = PTR_ERR(phy_dev);
1527 goto err_unregister_bus;
1529 bgmac->phy_dev = phy_dev;
1534 mdiobus_unregister(mii_bus);
1536 kfree(mii_bus->irq);
1538 mdiobus_free(mii_bus);
1542 static void bgmac_mii_unregister(struct bgmac *bgmac)
1544 struct mii_bus *mii_bus = bgmac->mii_bus;
1546 mdiobus_unregister(mii_bus);
1547 kfree(mii_bus->irq);
1548 mdiobus_free(mii_bus);
1551 /**************************************************
1553 **************************************************/
1555 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */
1556 static int bgmac_probe(struct bcma_device *core)
1558 struct bcma_chipinfo *ci = &core->bus->chipinfo;
1559 struct net_device *net_dev;
1560 struct bgmac *bgmac;
1561 struct ssb_sprom *sprom = &core->bus->sprom;
1565 switch (core->core_unit) {
1567 mac = sprom->et0mac;
1570 mac = sprom->et1mac;
1573 mac = sprom->et2mac;
1576 pr_err("Unsupported core_unit %d\n", core->core_unit);
1580 if (!is_valid_ether_addr(mac)) {
1581 dev_err(&core->dev, "Invalid MAC addr: %pM\n", mac);
1582 eth_random_addr(mac);
1583 dev_warn(&core->dev, "Using random MAC: %pM\n", mac);
1586 /* Allocation and references */
1587 net_dev = alloc_etherdev(sizeof(*bgmac));
1590 net_dev->netdev_ops = &bgmac_netdev_ops;
1591 net_dev->irq = core->irq;
1592 net_dev->ethtool_ops = &bgmac_ethtool_ops;
1593 bgmac = netdev_priv(net_dev);
1594 bgmac->net_dev = net_dev;
1596 bcma_set_drvdata(core, bgmac);
1599 memcpy(bgmac->net_dev->dev_addr, mac, ETH_ALEN);
1601 /* On BCM4706 we need common core to access PHY */
1602 if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
1603 !core->bus->drv_gmac_cmn.core) {
1604 bgmac_err(bgmac, "GMAC CMN core not found (required for BCM4706)\n");
1606 goto err_netdev_free;
1608 bgmac->cmn = core->bus->drv_gmac_cmn.core;
1610 switch (core->core_unit) {
1612 bgmac->phyaddr = sprom->et0phyaddr;
1615 bgmac->phyaddr = sprom->et1phyaddr;
1618 bgmac->phyaddr = sprom->et2phyaddr;
1621 bgmac->phyaddr &= BGMAC_PHY_MASK;
1622 if (bgmac->phyaddr == BGMAC_PHY_MASK) {
1623 bgmac_err(bgmac, "No PHY found\n");
1625 goto err_netdev_free;
1627 bgmac_info(bgmac, "Found PHY addr: %d%s\n", bgmac->phyaddr,
1628 bgmac->phyaddr == BGMAC_PHY_NOREGS ? " (NOREGS)" : "");
1630 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
1631 bgmac_err(bgmac, "PCI setup not implemented\n");
1633 goto err_netdev_free;
1636 bgmac_chip_reset(bgmac);
1638 /* For Northstar, we have to take all GMAC core out of reset */
1639 if (ci->id == BCMA_CHIP_ID_BCM4707 ||
1640 ci->id == BCMA_CHIP_ID_BCM53018) {
1641 struct bcma_device *ns_core;
1644 /* Northstar has 4 GMAC cores */
1645 for (ns_gmac = 0; ns_gmac < 4; ns_gmac++) {
1646 /* As Northstar requirement, we have to reset all GMACs
1647 * before accessing one. bgmac_chip_reset() call
1648 * bcma_core_enable() for this core. Then the other
1649 * three GMACs didn't reset. We do it here.
1651 ns_core = bcma_find_core_unit(core->bus,
1654 if (ns_core && !bcma_core_is_enabled(ns_core))
1655 bcma_core_enable(ns_core, 0);
1659 err = bgmac_dma_alloc(bgmac);
1661 bgmac_err(bgmac, "Unable to alloc memory for DMA\n");
1662 goto err_netdev_free;
1665 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK;
1666 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0)
1667 bgmac->int_mask &= ~BGMAC_IS_TX_MASK;
1669 /* TODO: reset the external phy. Specs are needed */
1670 bgmac_phy_reset(bgmac);
1672 bgmac->has_robosw = !!(core->bus->sprom.boardflags_lo &
1673 BGMAC_BFL_ENETROBO);
1674 if (bgmac->has_robosw)
1675 bgmac_warn(bgmac, "Support for Roboswitch not implemented\n");
1677 if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM)
1678 bgmac_warn(bgmac, "Support for ADMtek ethernet switch not implemented\n");
1680 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
1682 err = bgmac_mii_register(bgmac);
1684 bgmac_err(bgmac, "Cannot register MDIO\n");
1688 net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1689 net_dev->hw_features = net_dev->features;
1690 net_dev->vlan_features = net_dev->features;
1692 err = register_netdev(bgmac->net_dev);
1694 bgmac_err(bgmac, "Cannot register net device\n");
1695 goto err_mii_unregister;
1698 netif_carrier_off(net_dev);
1703 bgmac_mii_unregister(bgmac);
1705 bgmac_dma_free(bgmac);
1708 bcma_set_drvdata(core, NULL);
1709 free_netdev(net_dev);
1714 static void bgmac_remove(struct bcma_device *core)
1716 struct bgmac *bgmac = bcma_get_drvdata(core);
1718 unregister_netdev(bgmac->net_dev);
1719 bgmac_mii_unregister(bgmac);
1720 netif_napi_del(&bgmac->napi);
1721 bgmac_dma_free(bgmac);
1722 bcma_set_drvdata(core, NULL);
1723 free_netdev(bgmac->net_dev);
1726 static struct bcma_driver bgmac_bcma_driver = {
1727 .name = KBUILD_MODNAME,
1728 .id_table = bgmac_bcma_tbl,
1729 .probe = bgmac_probe,
1730 .remove = bgmac_remove,
1733 static int __init bgmac_init(void)
1737 err = bcma_driver_register(&bgmac_bcma_driver);
1740 pr_info("Broadcom 47xx GBit MAC driver loaded\n");
1745 static void __exit bgmac_exit(void)
1747 bcma_driver_unregister(&bgmac_bcma_driver);
1750 module_init(bgmac_init)
1751 module_exit(bgmac_exit)
1753 MODULE_AUTHOR("Rafał Miłecki");
1754 MODULE_LICENSE("GPL");