drivers/net/gianfar.c

   1 /*
   2  * drivers/net/gianfar.c
   3  *
   4  * Gianfar Ethernet Driver
   5  * This driver is designed for the non-CPM ethernet controllers
   6  * on the 85xx and 83xx family of integrated processors
   7  * Based on 8260_io/fcc_enet.c
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala
  11  *
  12  * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
  13  * Copyright (c) 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #include <linux/kernel.h>
  65 #include <linux/string.h>
  66 #include <linux/errno.h>
  67 #include <linux/unistd.h>
  68 #include <linux/slab.h>
  69 #include <linux/interrupt.h>
  70 #include <linux/init.h>
  71 #include <linux/delay.h>
  72 #include <linux/netdevice.h>
  73 #include <linux/etherdevice.h>
  74 #include <linux/skbuff.h>
  75 #include <linux/if_vlan.h>
  76 #include <linux/spinlock.h>
  77 #include <linux/mm.h>
  78 #include <linux/of_platform.h>
  79 #include <linux/ip.h>
  80 #include <linux/tcp.h>
  81 #include <linux/udp.h>
  82 #include <linux/in.h>
  83
  84 #include <asm/io.h>
  85 #include <asm/irq.h>
  86 #include <asm/uaccess.h>
  87 #include <linux/module.h>
  88 #include <linux/dma-mapping.h>
  89 #include <linux/crc32.h>
  90 #include <linux/mii.h>
  91 #include <linux/phy.h>
  92 #include <linux/phy_fixed.h>
  93 #include <linux/of.h>
  94
  95 #include "gianfar.h"
  96 #include "gianfar_mii.h"
  97
  98 #define TX_TIMEOUT      (1*HZ)
  99 #undef BRIEF_GFAR_ERRORS
 100 #undef VERBOSE_GFAR_ERRORS
 101
 102 const char gfar_driver_name[] = "Gianfar Ethernet";
 103 const char gfar_driver_version[] = "1.3";
 104
 105 static int gfar_enet_open(struct net_device *dev);
 106 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 107 static void gfar_reset_task(struct work_struct *work);
 108 static void gfar_timeout(struct net_device *dev);
 109 static int gfar_close(struct net_device *dev);
 110 struct sk_buff *gfar_new_skb(struct net_device *dev);
 111 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
 112                 struct sk_buff *skb);
 113 static int gfar_set_mac_address(struct net_device *dev);
 114 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 115 static irqreturn_t gfar_error(int irq, void *dev_id);
 116 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 117 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 118 static void adjust_link(struct net_device *dev);
 119 static void init_registers(struct net_device *dev);
 120 static int init_phy(struct net_device *dev);
 121 static int gfar_probe(struct of_device *ofdev,
 122                 const struct of_device_id *match);
 123 static int gfar_remove(struct of_device *ofdev);
 124 static void free_skb_resources(struct gfar_private *priv);
 125 static void gfar_set_multi(struct net_device *dev);
 126 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 127 static void gfar_configure_serdes(struct net_device *dev);
 128 static int gfar_poll(struct napi_struct *napi, int budget);
 129 #ifdef CONFIG_NET_POLL_CONTROLLER
 130 static void gfar_netpoll(struct net_device *dev);
 131 #endif
 132 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
 133 static int gfar_clean_tx_ring(struct net_device *dev);
 134 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 135                               int amount_pull);
 136 static void gfar_vlan_rx_register(struct net_device *netdev,
 137                                 struct vlan_group *grp);
 138 void gfar_halt(struct net_device *dev);
 139 static void gfar_halt_nodisable(struct net_device *dev);
 140 void gfar_start(struct net_device *dev);
 141 static void gfar_clear_exact_match(struct net_device *dev);
 142 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
 143
 144 extern const struct ethtool_ops gfar_ethtool_ops;
 145
 146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 148 MODULE_LICENSE("GPL");
 149
 150 /* Returns 1 if incoming frames use an FCB */
 151 static inline int gfar_uses_fcb(struct gfar_private *priv)
 152 {
 153         return priv->vlgrp || priv->rx_csum_enable;
 154 }
 155
 156 static int gfar_of_init(struct net_device *dev)
 157 {
 158         struct device_node *phy, *mdio;
 159         const unsigned int *id;
 160         const char *model;
 161         const char *ctype;
 162         const void *mac_addr;
 163         const phandle *ph;
 164         u64 addr, size;
 165         int err = 0;
 166         struct gfar_private *priv = netdev_priv(dev);
 167         struct device_node *np = priv->node;
 168         char bus_name[MII_BUS_ID_SIZE];
 169
 170         if (!np || !of_device_is_available(np))
 171                 return -ENODEV;
 172
 173         /* get a pointer to the register memory */
 174         addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
 175         priv->regs = ioremap(addr, size);
 176
 177         if (priv->regs == NULL)
 178                 return -ENOMEM;
 179
 180         priv->interruptTransmit = irq_of_parse_and_map(np, 0);
 181
 182         model = of_get_property(np, "model", NULL);
 183
 184         /* If we aren't the FEC we have multiple interrupts */
 185         if (model && strcasecmp(model, "FEC")) {
 186                 priv->interruptReceive = irq_of_parse_and_map(np, 1);
 187
 188                 priv->interruptError = irq_of_parse_and_map(np, 2);
 189
 190                 if (priv->interruptTransmit < 0 ||
 191                                 priv->interruptReceive < 0 ||
 192                                 priv->interruptError < 0) {
 193                         err = -EINVAL;
 194                         goto err_out;
 195                 }
 196         }
 197
 198         mac_addr = of_get_mac_address(np);
 199         if (mac_addr)
 200                 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
 201
 202         if (model && !strcasecmp(model, "TSEC"))
 203                 priv->device_flags =
 204                         FSL_GIANFAR_DEV_HAS_GIGABIT |
 205                         FSL_GIANFAR_DEV_HAS_COALESCE |
 206                         FSL_GIANFAR_DEV_HAS_RMON |
 207                         FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 208         if (model && !strcasecmp(model, "eTSEC"))
 209                 priv->device_flags =
 210                         FSL_GIANFAR_DEV_HAS_GIGABIT |
 211                         FSL_GIANFAR_DEV_HAS_COALESCE |
 212                         FSL_GIANFAR_DEV_HAS_RMON |
 213                         FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 214                         FSL_GIANFAR_DEV_HAS_PADDING |
 215                         FSL_GIANFAR_DEV_HAS_CSUM |
 216                         FSL_GIANFAR_DEV_HAS_VLAN |
 217                         FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 218                         FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
 219
 220         ctype = of_get_property(np, "phy-connection-type", NULL);
 221
 222         /* We only care about rgmii-id.  The rest are autodetected */
 223         if (ctype && !strcmp(ctype, "rgmii-id"))
 224                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 225         else
 226                 priv->interface = PHY_INTERFACE_MODE_MII;
 227
 228         if (of_get_property(np, "fsl,magic-packet", NULL))
 229                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 230
 231         ph = of_get_property(np, "phy-handle", NULL);
 232         if (ph == NULL) {
 233                 u32 *fixed_link;
 234
 235                 fixed_link = (u32 *)of_get_property(np, "fixed-link", NULL);
 236                 if (!fixed_link) {
 237                         err = -ENODEV;
 238                         goto err_out;
 239                 }
 240
 241                 snprintf(priv->phy_bus_id, BUS_ID_SIZE, PHY_ID_FMT, "0",
 242                                 fixed_link[0]);
 243         } else {
 244                 phy = of_find_node_by_phandle(*ph);
 245
 246                 if (phy == NULL) {
 247                         err = -ENODEV;
 248                         goto err_out;
 249                 }
 250
 251                 mdio = of_get_parent(phy);
 252
 253                 id = of_get_property(phy, "reg", NULL);
 254
 255                 of_node_put(phy);
 256                 of_node_put(mdio);
 257
 258                 gfar_mdio_bus_name(bus_name, mdio);
 259                 snprintf(priv->phy_bus_id, BUS_ID_SIZE, "%s:%02x",
 260                                 bus_name, *id);
 261         }
 262
 263         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 264         ph = of_get_property(np, "tbi-handle", NULL);
 265         if (ph) {
 266                 struct device_node *tbi = of_find_node_by_phandle(*ph);
 267                 struct of_device *ofdev;
 268                 struct mii_bus *bus;
 269
 270                 if (!tbi)
 271                         return 0;
 272
 273                 mdio = of_get_parent(tbi);
 274                 if (!mdio)
 275                         return 0;
 276
 277                 ofdev = of_find_device_by_node(mdio);
 278
 279                 of_node_put(mdio);
 280
 281                 id = of_get_property(tbi, "reg", NULL);
 282                 if (!id)
 283                         return 0;
 284
 285                 of_node_put(tbi);
 286
 287                 bus = dev_get_drvdata(&ofdev->dev);
 288
 289                 priv->tbiphy = bus->phy_map[*id];
 290         }
 291
 292         return 0;
 293
 294 err_out:
 295         iounmap(priv->regs);
 296         return err;
 297 }
 298
 299 /* Set up the ethernet device structure, private data,
 300  * and anything else we need before we start */
 301 static int gfar_probe(struct of_device *ofdev,
 302                 const struct of_device_id *match)
 303 {
 304         u32 tempval;
 305         struct net_device *dev = NULL;
 306         struct gfar_private *priv = NULL;
 307         int err = 0;
 308         DECLARE_MAC_BUF(mac);
 309
 310         /* Create an ethernet device instance */
 311         dev = alloc_etherdev(sizeof (*priv));
 312
 313         if (NULL == dev)
 314                 return -ENOMEM;
 315
 316         priv = netdev_priv(dev);
 317         priv->dev = dev;
 318         priv->node = ofdev->node;
 319
 320         err = gfar_of_init(dev);
 321
 322         if (err)
 323                 goto regs_fail;
 324
 325         spin_lock_init(&priv->txlock);
 326         spin_lock_init(&priv->rxlock);
 327         spin_lock_init(&priv->bflock);
 328         INIT_WORK(&priv->reset_task, gfar_reset_task);
 329
 330         dev_set_drvdata(&ofdev->dev, priv);
 331
 332         /* Stop the DMA engine now, in case it was running before */
 333         /* (The firmware could have used it, and left it running). */
 334         gfar_halt(dev);
 335
 336         /* Reset MAC layer */
 337         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
 338
 339         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
 340         gfar_write(&priv->regs->maccfg1, tempval);
 341
 342         /* Initialize MACCFG2. */
 343         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
 344
 345         /* Initialize ECNTRL */
 346         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
 347
 348         /* Set the dev->base_addr to the gfar reg region */
 349         dev->base_addr = (unsigned long) (priv->regs);
 350
 351         SET_NETDEV_DEV(dev, &ofdev->dev);
 352
 353         /* Fill in the dev structure */
 354         dev->open = gfar_enet_open;
 355         dev->hard_start_xmit = gfar_start_xmit;
 356         dev->tx_timeout = gfar_timeout;
 357         dev->watchdog_timeo = TX_TIMEOUT;
 358         netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
 359 #ifdef CONFIG_NET_POLL_CONTROLLER
 360         dev->poll_controller = gfar_netpoll;
 361 #endif
 362         dev->stop = gfar_close;
 363         dev->change_mtu = gfar_change_mtu;
 364         dev->mtu = 1500;
 365         dev->set_multicast_list = gfar_set_multi;
 366
 367         dev->ethtool_ops = &gfar_ethtool_ops;
 368
 369         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
 370                 priv->rx_csum_enable = 1;
 371                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
 372         } else
 373                 priv->rx_csum_enable = 0;
 374
 375         priv->vlgrp = NULL;
 376
 377         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
 378                 dev->vlan_rx_register = gfar_vlan_rx_register;
 379
 380                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
 381         }
 382
 383         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
 384                 priv->extended_hash = 1;
 385                 priv->hash_width = 9;
 386
 387                 priv->hash_regs[0] = &priv->regs->igaddr0;
 388                 priv->hash_regs[1] = &priv->regs->igaddr1;
 389                 priv->hash_regs[2] = &priv->regs->igaddr2;
 390                 priv->hash_regs[3] = &priv->regs->igaddr3;
 391                 priv->hash_regs[4] = &priv->regs->igaddr4;
 392                 priv->hash_regs[5] = &priv->regs->igaddr5;
 393                 priv->hash_regs[6] = &priv->regs->igaddr6;
 394                 priv->hash_regs[7] = &priv->regs->igaddr7;
 395                 priv->hash_regs[8] = &priv->regs->gaddr0;
 396                 priv->hash_regs[9] = &priv->regs->gaddr1;
 397                 priv->hash_regs[10] = &priv->regs->gaddr2;
 398                 priv->hash_regs[11] = &priv->regs->gaddr3;
 399                 priv->hash_regs[12] = &priv->regs->gaddr4;
 400                 priv->hash_regs[13] = &priv->regs->gaddr5;
 401                 priv->hash_regs[14] = &priv->regs->gaddr6;
 402                 priv->hash_regs[15] = &priv->regs->gaddr7;
 403
 404         } else {
 405                 priv->extended_hash = 0;
 406                 priv->hash_width = 8;
 407
 408                 priv->hash_regs[0] = &priv->regs->gaddr0;
 409                 priv->hash_regs[1] = &priv->regs->gaddr1;
 410                 priv->hash_regs[2] = &priv->regs->gaddr2;
 411                 priv->hash_regs[3] = &priv->regs->gaddr3;
 412                 priv->hash_regs[4] = &priv->regs->gaddr4;
 413                 priv->hash_regs[5] = &priv->regs->gaddr5;
 414                 priv->hash_regs[6] = &priv->regs->gaddr6;
 415                 priv->hash_regs[7] = &priv->regs->gaddr7;
 416         }
 417
 418         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
 419                 priv->padding = DEFAULT_PADDING;
 420         else
 421                 priv->padding = 0;
 422
 423         if (dev->features & NETIF_F_IP_CSUM)
 424                 dev->hard_header_len += GMAC_FCB_LEN;
 425
 426         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
 427         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
 428         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
 429         priv->num_txbdfree = DEFAULT_TX_RING_SIZE;
 430
 431         priv->txcoalescing = DEFAULT_TX_COALESCE;
 432         priv->txic = DEFAULT_TXIC;
 433         priv->rxcoalescing = DEFAULT_RX_COALESCE;
 434         priv->rxic = DEFAULT_RXIC;
 435
 436         /* Enable most messages by default */
 437         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
 438
 439         /* Carrier starts down, phylib will bring it up */
 440         netif_carrier_off(dev);
 441
 442         err = register_netdev(dev);
 443
 444         if (err) {
 445                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
 446                                 dev->name);
 447                 goto register_fail;
 448         }
 449
 450         /* Create all the sysfs files */
 451         gfar_init_sysfs(dev);
 452
 453         /* Print out the device info */
 454         printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
 455
 456         /* Even more device info helps when determining which kernel */
 457         /* provided which set of benchmarks. */
 458         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
 459         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
 460                dev->name, priv->rx_ring_size, priv->tx_ring_size);
 461
 462         return 0;
 463
 464 register_fail:
 465         iounmap(priv->regs);
 466 regs_fail:
 467         free_netdev(dev);
 468         return err;
 469 }
 470
 471 static int gfar_remove(struct of_device *ofdev)
 472 {
 473         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
 474
 475         dev_set_drvdata(&ofdev->dev, NULL);
 476
 477         iounmap(priv->regs);
 478         free_netdev(priv->dev);
 479
 480         return 0;
 481 }
 482
 483 #ifdef CONFIG_PM
 484 static int gfar_suspend(struct of_device *ofdev, pm_message_t state)
 485 {
 486         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
 487         struct net_device *dev = priv->dev;
 488         unsigned long flags;
 489         u32 tempval;
 490
 491         int magic_packet = priv->wol_en &&
 492                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
 493
 494         netif_device_detach(dev);
 495
 496         if (netif_running(dev)) {
 497                 spin_lock_irqsave(&priv->txlock, flags);
 498                 spin_lock(&priv->rxlock);
 499
 500                 gfar_halt_nodisable(dev);
 501
 502                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
 503                 tempval = gfar_read(&priv->regs->maccfg1);
 504
 505                 tempval &= ~MACCFG1_TX_EN;
 506
 507                 if (!magic_packet)
 508                         tempval &= ~MACCFG1_RX_EN;
 509
 510                 gfar_write(&priv->regs->maccfg1, tempval);
 511
 512                 spin_unlock(&priv->rxlock);
 513                 spin_unlock_irqrestore(&priv->txlock, flags);
 514
 515                 napi_disable(&priv->napi);
 516
 517                 if (magic_packet) {
 518                         /* Enable interrupt on Magic Packet */
 519                         gfar_write(&priv->regs->imask, IMASK_MAG);
 520
 521                         /* Enable Magic Packet mode */
 522                         tempval = gfar_read(&priv->regs->maccfg2);
 523                         tempval |= MACCFG2_MPEN;
 524                         gfar_write(&priv->regs->maccfg2, tempval);
 525                 } else {
 526                         phy_stop(priv->phydev);
 527                 }
 528         }
 529
 530         return 0;
 531 }
 532
 533 static int gfar_resume(struct of_device *ofdev)
 534 {
 535         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
 536         struct net_device *dev = priv->dev;
 537         unsigned long flags;
 538         u32 tempval;
 539         int magic_packet = priv->wol_en &&
 540                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
 541
 542         if (!netif_running(dev)) {
 543                 netif_device_attach(dev);
 544                 return 0;
 545         }
 546
 547         if (!magic_packet && priv->phydev)
 548                 phy_start(priv->phydev);
 549
 550         /* Disable Magic Packet mode, in case something
 551          * else woke us up.
 552          */
 553
 554         spin_lock_irqsave(&priv->txlock, flags);
 555         spin_lock(&priv->rxlock);
 556
 557         tempval = gfar_read(&priv->regs->maccfg2);
 558         tempval &= ~MACCFG2_MPEN;
 559         gfar_write(&priv->regs->maccfg2, tempval);
 560
 561         gfar_start(dev);
 562
 563         spin_unlock(&priv->rxlock);
 564         spin_unlock_irqrestore(&priv->txlock, flags);
 565
 566         netif_device_attach(dev);
 567
 568         napi_enable(&priv->napi);
 569
 570         return 0;
 571 }
 572 #else
 573 #define gfar_suspend NULL
 574 #define gfar_resume NULL
 575 #endif
 576
 577 /* Reads the controller's registers to determine what interface
 578  * connects it to the PHY.
 579  */
 580 static phy_interface_t gfar_get_interface(struct net_device *dev)
 581 {
 582         struct gfar_private *priv = netdev_priv(dev);
 583         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
 584
 585         if (ecntrl & ECNTRL_SGMII_MODE)
 586                 return PHY_INTERFACE_MODE_SGMII;
 587
 588         if (ecntrl & ECNTRL_TBI_MODE) {
 589                 if (ecntrl & ECNTRL_REDUCED_MODE)
 590                         return PHY_INTERFACE_MODE_RTBI;
 591                 else
 592                         return PHY_INTERFACE_MODE_TBI;
 593         }
 594
 595         if (ecntrl & ECNTRL_REDUCED_MODE) {
 596                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
 597                         return PHY_INTERFACE_MODE_RMII;
 598                 else {
 599                         phy_interface_t interface = priv->interface;
 600
 601                         /*
 602                          * This isn't autodetected right now, so it must
 603                          * be set by the device tree or platform code.
 604                          */
 605                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
 606                                 return PHY_INTERFACE_MODE_RGMII_ID;
 607
 608                         return PHY_INTERFACE_MODE_RGMII;
 609                 }
 610         }
 611
 612         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
 613                 return PHY_INTERFACE_MODE_GMII;
 614
 615         return PHY_INTERFACE_MODE_MII;
 616 }
 617
 618
 619 /* Initializes driver's PHY state, and attaches to the PHY.
 620  * Returns 0 on success.
 621  */
 622 static int init_phy(struct net_device *dev)
 623 {
 624         struct gfar_private *priv = netdev_priv(dev);
 625         uint gigabit_support =
 626                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
 627                 SUPPORTED_1000baseT_Full : 0;
 628         struct phy_device *phydev;
 629         phy_interface_t interface;
 630
 631         priv->oldlink = 0;
 632         priv->oldspeed = 0;
 633         priv->oldduplex = -1;
 634
 635         interface = gfar_get_interface(dev);
 636
 637         phydev = phy_connect(dev, priv->phy_bus_id, &adjust_link, 0, interface);
 638
 639         if (interface == PHY_INTERFACE_MODE_SGMII)
 640                 gfar_configure_serdes(dev);
 641
 642         if (IS_ERR(phydev)) {
 643                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
 644                 return PTR_ERR(phydev);
 645         }
 646
 647         /* Remove any features not supported by the controller */
 648         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
 649         phydev->advertising = phydev->supported;
 650
 651         priv->phydev = phydev;
 652
 653         return 0;
 654 }
 655
 656 /*
 657  * Initialize TBI PHY interface for communicating with the
 658  * SERDES lynx PHY on the chip.  We communicate with this PHY
 659  * through the MDIO bus on each controller, treating it as a
 660  * "normal" PHY at the address found in the TBIPA register.  We assume
 661  * that the TBIPA register is valid.  Either the MDIO bus code will set
 662  * it to a value that doesn't conflict with other PHYs on the bus, or the
 663  * value doesn't matter, as there are no other PHYs on the bus.
 664  */
 665 static void gfar_configure_serdes(struct net_device *dev)
 666 {
 667         struct gfar_private *priv = netdev_priv(dev);
 668
 669         if (!priv->tbiphy) {
 670                 printk(KERN_WARNING "SGMII mode requires that the device "
 671                                 "tree specify a tbi-handle\n");
 672                 return;
 673         }
 674
 675         /*
 676          * If the link is already up, we must already be ok, and don't need to
 677          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
 678          * everything for us?  Resetting it takes the link down and requires
 679          * several seconds for it to come back.
 680          */
 681         if (phy_read(priv->tbiphy, MII_BMSR) & BMSR_LSTATUS)
 682                 return;
 683
 684         /* Single clk mode, mii mode off(for serdes communication) */
 685         phy_write(priv->tbiphy, MII_TBICON, TBICON_CLK_SELECT);
 686
 687         phy_write(priv->tbiphy, MII_ADVERTISE,
 688                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
 689                         ADVERTISE_1000XPSE_ASYM);
 690
 691         phy_write(priv->tbiphy, MII_BMCR, BMCR_ANENABLE |
 692                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
 693 }
 694
 695 static void init_registers(struct net_device *dev)
 696 {
 697         struct gfar_private *priv = netdev_priv(dev);
 698
 699         /* Clear IEVENT */
 700         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
 701
 702         /* Initialize IMASK */
 703         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
 704
 705         /* Init hash registers to zero */
 706         gfar_write(&priv->regs->igaddr0, 0);
 707         gfar_write(&priv->regs->igaddr1, 0);
 708         gfar_write(&priv->regs->igaddr2, 0);
 709         gfar_write(&priv->regs->igaddr3, 0);
 710         gfar_write(&priv->regs->igaddr4, 0);
 711         gfar_write(&priv->regs->igaddr5, 0);
 712         gfar_write(&priv->regs->igaddr6, 0);
 713         gfar_write(&priv->regs->igaddr7, 0);
 714
 715         gfar_write(&priv->regs->gaddr0, 0);
 716         gfar_write(&priv->regs->gaddr1, 0);
 717         gfar_write(&priv->regs->gaddr2, 0);
 718         gfar_write(&priv->regs->gaddr3, 0);
 719         gfar_write(&priv->regs->gaddr4, 0);
 720         gfar_write(&priv->regs->gaddr5, 0);
 721         gfar_write(&priv->regs->gaddr6, 0);
 722         gfar_write(&priv->regs->gaddr7, 0);
 723
 724         /* Zero out the rmon mib registers if it has them */
 725         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
 726                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
 727
 728                 /* Mask off the CAM interrupts */
 729                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
 730                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
 731         }
 732
 733         /* Initialize the max receive buffer length */
 734         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
 735
 736         /* Initialize the Minimum Frame Length Register */
 737         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
 738 }
 739
 740
 741 /* Halt the receive and transmit queues */
 742 static void gfar_halt_nodisable(struct net_device *dev)
 743 {
 744         struct gfar_private *priv = netdev_priv(dev);
 745         struct gfar __iomem *regs = priv->regs;
 746         u32 tempval;
 747
 748         /* Mask all interrupts */
 749         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 750
 751         /* Clear all interrupts */
 752         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 753
 754         /* Stop the DMA, and wait for it to stop */
 755         tempval = gfar_read(&priv->regs->dmactrl);
 756         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
 757             != (DMACTRL_GRS | DMACTRL_GTS)) {
 758                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
 759                 gfar_write(&priv->regs->dmactrl, tempval);
 760
 761                 while (!(gfar_read(&priv->regs->ievent) &
 762                          (IEVENT_GRSC | IEVENT_GTSC)))
 763                         cpu_relax();
 764         }
 765 }
 766
 767 /* Halt the receive and transmit queues */
 768 void gfar_halt(struct net_device *dev)
 769 {
 770         struct gfar_private *priv = netdev_priv(dev);
 771         struct gfar __iomem *regs = priv->regs;
 772         u32 tempval;
 773
 774         gfar_halt_nodisable(dev);
 775
 776         /* Disable Rx and Tx */
 777         tempval = gfar_read(&regs->maccfg1);
 778         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
 779         gfar_write(&regs->maccfg1, tempval);
 780 }
 781
 782 void stop_gfar(struct net_device *dev)
 783 {
 784         struct gfar_private *priv = netdev_priv(dev);
 785         struct gfar __iomem *regs = priv->regs;
 786         unsigned long flags;
 787
 788         phy_stop(priv->phydev);
 789
 790         /* Lock it down */
 791         spin_lock_irqsave(&priv->txlock, flags);
 792         spin_lock(&priv->rxlock);
 793
 794         gfar_halt(dev);
 795
 796         spin_unlock(&priv->rxlock);
 797         spin_unlock_irqrestore(&priv->txlock, flags);
 798
 799         /* Free the IRQs */
 800         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 801                 free_irq(priv->interruptError, dev);
 802                 free_irq(priv->interruptTransmit, dev);
 803                 free_irq(priv->interruptReceive, dev);
 804         } else {
 805                 free_irq(priv->interruptTransmit, dev);
 806         }
 807
 808         free_skb_resources(priv);
 809
 810         dma_free_coherent(&dev->dev,
 811                         sizeof(struct txbd8)*priv->tx_ring_size
 812                         + sizeof(struct rxbd8)*priv->rx_ring_size,
 813                         priv->tx_bd_base,
 814                         gfar_read(&regs->tbase0));
 815 }
 816
 817 /* If there are any tx skbs or rx skbs still around, free them.
 818  * Then free tx_skbuff and rx_skbuff */
 819 static void free_skb_resources(struct gfar_private *priv)
 820 {
 821         struct rxbd8 *rxbdp;
 822         struct txbd8 *txbdp;
 823         int i, j;
 824
 825         /* Go through all the buffer descriptors and free their data buffers */
 826         txbdp = priv->tx_bd_base;
 827
 828         for (i = 0; i < priv->tx_ring_size; i++) {
 829                 if (!priv->tx_skbuff[i])
 830                         continue;
 831
 832                 dma_unmap_single(&priv->dev->dev, txbdp->bufPtr,
 833                                 txbdp->length, DMA_TO_DEVICE);
 834                 txbdp->lstatus = 0;
 835                 for (j = 0; j < skb_shinfo(priv->tx_skbuff[i])->nr_frags; j++) {
 836                         txbdp++;
 837                         dma_unmap_page(&priv->dev->dev, txbdp->bufPtr,
 838                                         txbdp->length, DMA_TO_DEVICE);
 839                 }
 840                 txbdp++;
 841                 dev_kfree_skb_any(priv->tx_skbuff[i]);
 842                 priv->tx_skbuff[i] = NULL;
 843         }
 844
 845         kfree(priv->tx_skbuff);
 846
 847         rxbdp = priv->rx_bd_base;
 848
 849         /* rx_skbuff is not guaranteed to be allocated, so only
 850          * free it and its contents if it is allocated */
 851         if(priv->rx_skbuff != NULL) {
 852                 for (i = 0; i < priv->rx_ring_size; i++) {
 853                         if (priv->rx_skbuff[i]) {
 854                                 dma_unmap_single(&priv->dev->dev, rxbdp->bufPtr,
 855                                                 priv->rx_buffer_size,
 856                                                 DMA_FROM_DEVICE);
 857
 858                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
 859                                 priv->rx_skbuff[i] = NULL;
 860                         }
 861
 862                         rxbdp->lstatus = 0;
 863                         rxbdp->bufPtr = 0;
 864
 865                         rxbdp++;
 866                 }
 867
 868                 kfree(priv->rx_skbuff);
 869         }
 870 }
 871
 872 void gfar_start(struct net_device *dev)
 873 {
 874         struct gfar_private *priv = netdev_priv(dev);
 875         struct gfar __iomem *regs = priv->regs;
 876         u32 tempval;
 877
 878         /* Enable Rx and Tx in MACCFG1 */
 879         tempval = gfar_read(&regs->maccfg1);
 880         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
 881         gfar_write(&regs->maccfg1, tempval);
 882
 883         /* Initialize DMACTRL to have WWR and WOP */
 884         tempval = gfar_read(&priv->regs->dmactrl);
 885         tempval |= DMACTRL_INIT_SETTINGS;
 886         gfar_write(&priv->regs->dmactrl, tempval);
 887
 888         /* Make sure we aren't stopped */
 889         tempval = gfar_read(&priv->regs->dmactrl);
 890         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
 891         gfar_write(&priv->regs->dmactrl, tempval);
 892
 893         /* Clear THLT/RHLT, so that the DMA starts polling now */
 894         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
 895         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
 896
 897         /* Unmask the interrupts we look for */
 898         gfar_write(&regs->imask, IMASK_DEFAULT);
 899
 900         dev->trans_start = jiffies;
 901 }
 902
 903 /* Bring the controller up and running */
 904 int startup_gfar(struct net_device *dev)
 905 {
 906         struct txbd8 *txbdp;
 907         struct rxbd8 *rxbdp;
 908         dma_addr_t addr = 0;
 909         unsigned long vaddr;
 910         int i;
 911         struct gfar_private *priv = netdev_priv(dev);
 912         struct gfar __iomem *regs = priv->regs;
 913         int err = 0;
 914         u32 rctrl = 0;
 915         u32 attrs = 0;
 916
 917         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 918
 919         /* Allocate memory for the buffer descriptors */
 920         vaddr = (unsigned long) dma_alloc_coherent(&dev->dev,
 921                         sizeof (struct txbd8) * priv->tx_ring_size +
 922                         sizeof (struct rxbd8) * priv->rx_ring_size,
 923                         &addr, GFP_KERNEL);
 924
 925         if (vaddr == 0) {
 926                 if (netif_msg_ifup(priv))
 927                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
 928                                         dev->name);
 929                 return -ENOMEM;
 930         }
 931
 932         priv->tx_bd_base = (struct txbd8 *) vaddr;
 933
 934         /* enet DMA only understands physical addresses */
 935         gfar_write(&regs->tbase0, addr);
 936
 937         /* Start the rx descriptor ring where the tx ring leaves off */
 938         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
 939         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
 940         priv->rx_bd_base = (struct rxbd8 *) vaddr;
 941         gfar_write(&regs->rbase0, addr);
 942
 943         /* Setup the skbuff rings */
 944         priv->tx_skbuff =
 945             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
 946                                         priv->tx_ring_size, GFP_KERNEL);
 947
 948         if (NULL == priv->tx_skbuff) {
 949                 if (netif_msg_ifup(priv))
 950                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
 951                                         dev->name);
 952                 err = -ENOMEM;
 953                 goto tx_skb_fail;
 954         }
 955
 956         for (i = 0; i < priv->tx_ring_size; i++)
 957                 priv->tx_skbuff[i] = NULL;
 958
 959         priv->rx_skbuff =
 960             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
 961                                         priv->rx_ring_size, GFP_KERNEL);
 962
 963         if (NULL == priv->rx_skbuff) {
 964                 if (netif_msg_ifup(priv))
 965                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
 966                                         dev->name);
 967                 err = -ENOMEM;
 968                 goto rx_skb_fail;
 969         }
 970
 971         for (i = 0; i < priv->rx_ring_size; i++)
 972                 priv->rx_skbuff[i] = NULL;
 973
 974         /* Initialize some variables in our dev structure */
 975         priv->num_txbdfree = priv->tx_ring_size;
 976         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
 977         priv->cur_rx = priv->rx_bd_base;
 978         priv->skb_curtx = priv->skb_dirtytx = 0;
 979         priv->skb_currx = 0;
 980
 981         /* Initialize Transmit Descriptor Ring */
 982         txbdp = priv->tx_bd_base;
 983         for (i = 0; i < priv->tx_ring_size; i++) {
 984                 txbdp->lstatus = 0;
 985                 txbdp->bufPtr = 0;
 986                 txbdp++;
 987         }
 988
 989         /* Set the last descriptor in the ring to indicate wrap */
 990         txbdp--;
 991         txbdp->status |= TXBD_WRAP;
 992
 993         rxbdp = priv->rx_bd_base;
 994         for (i = 0; i < priv->rx_ring_size; i++) {
 995                 struct sk_buff *skb;
 996
 997                 skb = gfar_new_skb(dev);
 998
 999                 if (!skb) {
1000                         printk(KERN_ERR "%s: Can't allocate RX buffers\n",
1001                                         dev->name);
1002
1003                         goto err_rxalloc_fail;
1004                 }
1005
1006                 priv->rx_skbuff[i] = skb;
1007
1008                 gfar_new_rxbdp(dev, rxbdp, skb);
1009
1010                 rxbdp++;
1011         }
1012
1013         /* Set the last descriptor in the ring to wrap */
1014         rxbdp--;
1015         rxbdp->status |= RXBD_WRAP;
1016
1017         /* If the device has multiple interrupts, register for
1018          * them.  Otherwise, only register for the one */
1019         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1020                 /* Install our interrupt handlers for Error,
1021                  * Transmit, and Receive */
1022                 if (request_irq(priv->interruptError, gfar_error,
1023                                 0, "enet_error", dev) < 0) {
1024                         if (netif_msg_intr(priv))
1025                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1026                                         dev->name, priv->interruptError);
1027
1028                         err = -1;
1029                         goto err_irq_fail;
1030                 }
1031
1032                 if (request_irq(priv->interruptTransmit, gfar_transmit,
1033                                 0, "enet_tx", dev) < 0) {
1034                         if (netif_msg_intr(priv))
1035                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1036                                         dev->name, priv->interruptTransmit);
1037
1038                         err = -1;
1039
1040                         goto tx_irq_fail;
1041                 }
1042
1043                 if (request_irq(priv->interruptReceive, gfar_receive,
1044                                 0, "enet_rx", dev) < 0) {
1045                         if (netif_msg_intr(priv))
1046                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
1047                                                 dev->name, priv->interruptReceive);
1048
1049                         err = -1;
1050                         goto rx_irq_fail;
1051                 }
1052         } else {
1053                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
1054                                 0, "gfar_interrupt", dev) < 0) {
1055                         if (netif_msg_intr(priv))
1056                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1057                                         dev->name, priv->interruptError);
1058
1059                         err = -1;
1060                         goto err_irq_fail;
1061                 }
1062         }
1063
1064         phy_start(priv->phydev);
1065
1066         /* Configure the coalescing support */
1067         gfar_write(&regs->txic, 0);
1068         if (priv->txcoalescing)
1069                 gfar_write(&regs->txic, priv->txic);
1070
1071         gfar_write(&regs->rxic, 0);
1072         if (priv->rxcoalescing)
1073                 gfar_write(&regs->rxic, priv->rxic);
1074
1075         if (priv->rx_csum_enable)
1076                 rctrl |= RCTRL_CHECKSUMMING;
1077
1078         if (priv->extended_hash) {
1079                 rctrl |= RCTRL_EXTHASH;
1080
1081                 gfar_clear_exact_match(dev);
1082                 rctrl |= RCTRL_EMEN;
1083         }
1084
1085         if (priv->padding) {
1086                 rctrl &= ~RCTRL_PAL_MASK;
1087                 rctrl |= RCTRL_PADDING(priv->padding);
1088         }
1089
1090         /* Init rctrl based on our settings */
1091         gfar_write(&priv->regs->rctrl, rctrl);
1092
1093         if (dev->features & NETIF_F_IP_CSUM)
1094                 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
1095
1096         /* Set the extraction length and index */
1097         attrs = ATTRELI_EL(priv->rx_stash_size) |
1098                 ATTRELI_EI(priv->rx_stash_index);
1099
1100         gfar_write(&priv->regs->attreli, attrs);
1101
1102         /* Start with defaults, and add stashing or locking
1103          * depending on the approprate variables */
1104         attrs = ATTR_INIT_SETTINGS;
1105
1106         if (priv->bd_stash_en)
1107                 attrs |= ATTR_BDSTASH;
1108
1109         if (priv->rx_stash_size != 0)
1110                 attrs |= ATTR_BUFSTASH;
1111
1112         gfar_write(&priv->regs->attr, attrs);
1113
1114         gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1115         gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1116         gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1117
1118         /* Start the controller */
1119         gfar_start(dev);
1120
1121         return 0;
1122
1123 rx_irq_fail:
1124         free_irq(priv->interruptTransmit, dev);
1125 tx_irq_fail:
1126         free_irq(priv->interruptError, dev);
1127 err_irq_fail:
1128 err_rxalloc_fail:
1129 rx_skb_fail:
1130         free_skb_resources(priv);
1131 tx_skb_fail:
1132         dma_free_coherent(&dev->dev,
1133                         sizeof(struct txbd8)*priv->tx_ring_size
1134                         + sizeof(struct rxbd8)*priv->rx_ring_size,
1135                         priv->tx_bd_base,
1136                         gfar_read(&regs->tbase0));
1137
1138         return err;
1139 }
1140
1141 /* Called when something needs to use the ethernet device */
1142 /* Returns 0 for success. */
1143 static int gfar_enet_open(struct net_device *dev)
1144 {
1145         struct gfar_private *priv = netdev_priv(dev);
1146         int err;
1147
1148         napi_enable(&priv->napi);
1149
1150         /* Initialize a bunch of registers */
1151         init_registers(dev);
1152
1153         gfar_set_mac_address(dev);
1154
1155         err = init_phy(dev);
1156
1157         if(err) {
1158                 napi_disable(&priv->napi);
1159                 return err;
1160         }
1161
1162         err = startup_gfar(dev);
1163         if (err) {
1164                 napi_disable(&priv->napi);
1165                 return err;
1166         }
1167
1168         netif_start_queue(dev);
1169
1170         return err;
1171 }
1172
1173 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1174 {
1175         struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
1176
1177         cacheable_memzero(fcb, GMAC_FCB_LEN);
1178
1179         return fcb;
1180 }
1181
1182 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1183 {
1184         u8 flags = 0;
1185
1186         /* If we're here, it's a IP packet with a TCP or UDP
1187          * payload.  We set it to checksum, using a pseudo-header
1188          * we provide
1189          */
1190         flags = TXFCB_DEFAULT;
1191
1192         /* Tell the controller what the protocol is */
1193         /* And provide the already calculated phcs */
1194         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1195                 flags |= TXFCB_UDP;
1196                 fcb->phcs = udp_hdr(skb)->check;
1197         } else
1198                 fcb->phcs = tcp_hdr(skb)->check;
1199
1200         /* l3os is the distance between the start of the
1201          * frame (skb->data) and the start of the IP hdr.
1202          * l4os is the distance between the start of the
1203          * l3 hdr and the l4 hdr */
1204         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1205         fcb->l4os = skb_network_header_len(skb);
1206
1207         fcb->flags = flags;
1208 }
1209
1210 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1211 {
1212         fcb->flags |= TXFCB_VLN;
1213         fcb->vlctl = vlan_tx_tag_get(skb);
1214 }
1215
1216 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1217                                struct txbd8 *base, int ring_size)
1218 {
1219         struct txbd8 *new_bd = bdp + stride;
1220
1221         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1222 }
1223
1224 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1225                 int ring_size)
1226 {
1227         return skip_txbd(bdp, 1, base, ring_size);
1228 }
1229
1230 /* This is called by the kernel when a frame is ready for transmission. */
1231 /* It is pointed to by the dev->hard_start_xmit function pointer */
1232 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1233 {
1234         struct gfar_private *priv = netdev_priv(dev);
1235         struct txfcb *fcb = NULL;
1236         struct txbd8 *txbdp, *txbdp_start, *base;
1237         u32 lstatus;
1238         int i;
1239         u32 bufaddr;
1240         unsigned long flags;
1241         unsigned int nr_frags, length;
1242
1243         base = priv->tx_bd_base;
1244
1245         /* total number of fragments in the SKB */
1246         nr_frags = skb_shinfo(skb)->nr_frags;
1247
1248         spin_lock_irqsave(&priv->txlock, flags);
1249
1250         /* check if there is space to queue this packet */
1251         if (nr_frags > priv->num_txbdfree) {
1252                 /* no space, stop the queue */
1253                 netif_stop_queue(dev);
1254                 dev->stats.tx_fifo_errors++;
1255                 spin_unlock_irqrestore(&priv->txlock, flags);
1256                 return NETDEV_TX_BUSY;
1257         }
1258
1259         /* Update transmit stats */
1260         dev->stats.tx_bytes += skb->len;
1261
1262         txbdp = txbdp_start = priv->cur_tx;
1263
1264         if (nr_frags == 0) {
1265                 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1266         } else {
1267                 /* Place the fragment addresses and lengths into the TxBDs */
1268                 for (i = 0; i < nr_frags; i++) {
1269                         /* Point at the next BD, wrapping as needed */
1270                         txbdp = next_txbd(txbdp, base, priv->tx_ring_size);
1271
1272                         length = skb_shinfo(skb)->frags[i].size;
1273
1274                         lstatus = txbdp->lstatus | length |
1275                                 BD_LFLAG(TXBD_READY);
1276
1277                         /* Handle the last BD specially */
1278                         if (i == nr_frags - 1)
1279                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1280
1281                         bufaddr = dma_map_page(&dev->dev,
1282                                         skb_shinfo(skb)->frags[i].page,
1283                                         skb_shinfo(skb)->frags[i].page_offset,
1284                                         length,
1285                                         DMA_TO_DEVICE);
1286
1287                         /* set the TxBD length and buffer pointer */
1288                         txbdp->bufPtr = bufaddr;
1289                         txbdp->lstatus = lstatus;
1290                 }
1291
1292                 lstatus = txbdp_start->lstatus;
1293         }
1294
1295         /* Set up checksumming */
1296         if (CHECKSUM_PARTIAL == skb->ip_summed) {
1297                 fcb = gfar_add_fcb(skb);
1298                 lstatus |= BD_LFLAG(TXBD_TOE);
1299                 gfar_tx_checksum(skb, fcb);
1300         }
1301
1302         if (priv->vlgrp && vlan_tx_tag_present(skb)) {
1303                 if (unlikely(NULL == fcb)) {
1304                         fcb = gfar_add_fcb(skb);
1305                         lstatus |= BD_LFLAG(TXBD_TOE);
1306                 }
1307
1308                 gfar_tx_vlan(skb, fcb);
1309         }
1310
1311         /* setup the TxBD length and buffer pointer for the first BD */
1312         priv->tx_skbuff[priv->skb_curtx] = skb;
1313         txbdp_start->bufPtr = dma_map_single(&dev->dev, skb->data,
1314                         skb_headlen(skb), DMA_TO_DEVICE);
1315
1316         lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1317
1318         /*
1319          * The powerpc-specific eieio() is used, as wmb() has too strong
1320          * semantics (it requires synchronization between cacheable and
1321          * uncacheable mappings, which eieio doesn't provide and which we
1322          * don't need), thus requiring a more expensive sync instruction.  At
1323          * some point, the set of architecture-independent barrier functions
1324          * should be expanded to include weaker barriers.
1325          */
1326         eieio();
1327
1328         txbdp_start->lstatus = lstatus;
1329
1330         /* Update the current skb pointer to the next entry we will use
1331          * (wrapping if necessary) */
1332         priv->skb_curtx = (priv->skb_curtx + 1) &
1333                 TX_RING_MOD_MASK(priv->tx_ring_size);
1334
1335         priv->cur_tx = next_txbd(txbdp, base, priv->tx_ring_size);
1336
1337         /* reduce TxBD free count */
1338         priv->num_txbdfree -= (nr_frags + 1);
1339
1340         dev->trans_start = jiffies;
1341
1342         /* If the next BD still needs to be cleaned up, then the bds
1343            are full.  We need to tell the kernel to stop sending us stuff. */
1344         if (!priv->num_txbdfree) {
1345                 netif_stop_queue(dev);
1346
1347                 dev->stats.tx_fifo_errors++;
1348         }
1349
1350         /* Tell the DMA to go go go */
1351         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1352
1353         /* Unlock priv */
1354         spin_unlock_irqrestore(&priv->txlock, flags);
1355
1356         return 0;
1357 }
1358
1359 /* Stops the kernel queue, and halts the controller */
1360 static int gfar_close(struct net_device *dev)
1361 {
1362         struct gfar_private *priv = netdev_priv(dev);
1363
1364         napi_disable(&priv->napi);
1365
1366         cancel_work_sync(&priv->reset_task);
1367         stop_gfar(dev);
1368
1369         /* Disconnect from the PHY */
1370         phy_disconnect(priv->phydev);
1371         priv->phydev = NULL;
1372
1373         netif_stop_queue(dev);
1374
1375         return 0;
1376 }
1377
1378 /* Changes the mac address if the controller is not running. */
1379 static int gfar_set_mac_address(struct net_device *dev)
1380 {
1381         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1382
1383         return 0;
1384 }
1385
1386
1387 /* Enables and disables VLAN insertion/extraction */
1388 static void gfar_vlan_rx_register(struct net_device *dev,
1389                 struct vlan_group *grp)
1390 {
1391         struct gfar_private *priv = netdev_priv(dev);
1392         unsigned long flags;
1393         struct vlan_group *old_grp;
1394         u32 tempval;
1395
1396         spin_lock_irqsave(&priv->rxlock, flags);
1397
1398         old_grp = priv->vlgrp;
1399
1400         if (old_grp == grp)
1401                 return;
1402
1403         if (grp) {
1404                 /* Enable VLAN tag insertion */
1405                 tempval = gfar_read(&priv->regs->tctrl);
1406                 tempval |= TCTRL_VLINS;
1407
1408                 gfar_write(&priv->regs->tctrl, tempval);
1409
1410                 /* Enable VLAN tag extraction */
1411                 tempval = gfar_read(&priv->regs->rctrl);
1412                 tempval |= RCTRL_VLEX;
1413                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
1414                 gfar_write(&priv->regs->rctrl, tempval);
1415         } else {
1416                 /* Disable VLAN tag insertion */
1417                 tempval = gfar_read(&priv->regs->tctrl);
1418                 tempval &= ~TCTRL_VLINS;
1419                 gfar_write(&priv->regs->tctrl, tempval);
1420
1421                 /* Disable VLAN tag extraction */
1422                 tempval = gfar_read(&priv->regs->rctrl);
1423                 tempval &= ~RCTRL_VLEX;
1424                 /* If parse is no longer required, then disable parser */
1425                 if (tempval & RCTRL_REQ_PARSER)
1426                         tempval |= RCTRL_PRSDEP_INIT;
1427                 else
1428                         tempval &= ~RCTRL_PRSDEP_INIT;
1429                 gfar_write(&priv->regs->rctrl, tempval);
1430         }
1431
1432         gfar_change_mtu(dev, dev->mtu);
1433
1434         spin_unlock_irqrestore(&priv->rxlock, flags);
1435 }
1436
1437 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1438 {
1439         int tempsize, tempval;
1440         struct gfar_private *priv = netdev_priv(dev);
1441         int oldsize = priv->rx_buffer_size;
1442         int frame_size = new_mtu + ETH_HLEN;
1443
1444         if (priv->vlgrp)
1445                 frame_size += VLAN_HLEN;
1446
1447         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1448                 if (netif_msg_drv(priv))
1449                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1450                                         dev->name);
1451                 return -EINVAL;
1452         }
1453
1454         if (gfar_uses_fcb(priv))
1455                 frame_size += GMAC_FCB_LEN;
1456
1457         frame_size += priv->padding;
1458
1459         tempsize =
1460             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1461             INCREMENTAL_BUFFER_SIZE;
1462
1463         /* Only stop and start the controller if it isn't already
1464          * stopped, and we changed something */
1465         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1466                 stop_gfar(dev);
1467
1468         priv->rx_buffer_size = tempsize;
1469
1470         dev->mtu = new_mtu;
1471
1472         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1473         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1474
1475         /* If the mtu is larger than the max size for standard
1476          * ethernet frames (ie, a jumbo frame), then set maccfg2
1477          * to allow huge frames, and to check the length */
1478         tempval = gfar_read(&priv->regs->maccfg2);
1479
1480         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1481                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1482         else
1483                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1484
1485         gfar_write(&priv->regs->maccfg2, tempval);
1486
1487         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1488                 startup_gfar(dev);
1489
1490         return 0;
1491 }
1492
1493 /* gfar_reset_task gets scheduled when a packet has not been
1494  * transmitted after a set amount of time.
1495  * For now, assume that clearing out all the structures, and
1496  * starting over will fix the problem.
1497  */
1498 static void gfar_reset_task(struct work_struct *work)
1499 {
1500         struct gfar_private *priv = container_of(work, struct gfar_private,
1501                         reset_task);
1502         struct net_device *dev = priv->dev;
1503
1504         if (dev->flags & IFF_UP) {
1505                 stop_gfar(dev);
1506                 startup_gfar(dev);
1507         }
1508
1509         netif_tx_schedule_all(dev);
1510 }
1511
1512 static void gfar_timeout(struct net_device *dev)
1513 {
1514         struct gfar_private *priv = netdev_priv(dev);
1515
1516         dev->stats.tx_errors++;
1517         schedule_work(&priv->reset_task);
1518 }
1519
1520 /* Interrupt Handler for Transmit complete */
1521 static int gfar_clean_tx_ring(struct net_device *dev)
1522 {
1523         struct gfar_private *priv = netdev_priv(dev);
1524         struct txbd8 *bdp;
1525         struct txbd8 *lbdp = NULL;
1526         struct txbd8 *base = priv->tx_bd_base;
1527         struct sk_buff *skb;
1528         int skb_dirtytx;
1529         int tx_ring_size = priv->tx_ring_size;
1530         int frags = 0;
1531         int i;
1532         int howmany = 0;
1533         u32 lstatus;
1534
1535         bdp = priv->dirty_tx;
1536         skb_dirtytx = priv->skb_dirtytx;
1537
1538         while ((skb = priv->tx_skbuff[skb_dirtytx])) {
1539                 frags = skb_shinfo(skb)->nr_frags;
1540                 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
1541
1542                 lstatus = lbdp->lstatus;
1543
1544                 /* Only clean completed frames */
1545                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
1546                                 (lstatus & BD_LENGTH_MASK))
1547                         break;
1548
1549                 dma_unmap_single(&dev->dev,
1550                                 bdp->bufPtr,
1551                                 bdp->length,
1552                                 DMA_TO_DEVICE);
1553
1554                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1555                 bdp = next_txbd(bdp, base, tx_ring_size);
1556
1557                 for (i = 0; i < frags; i++) {
1558                         dma_unmap_page(&dev->dev,
1559                                         bdp->bufPtr,
1560                                         bdp->length,
1561                                         DMA_TO_DEVICE);
1562                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1563                         bdp = next_txbd(bdp, base, tx_ring_size);
1564                 }
1565
1566                 dev_kfree_skb_any(skb);
1567                 priv->tx_skbuff[skb_dirtytx] = NULL;
1568
1569                 skb_dirtytx = (skb_dirtytx + 1) &
1570                         TX_RING_MOD_MASK(tx_ring_size);
1571
1572                 howmany++;
1573                 priv->num_txbdfree += frags + 1;
1574         }
1575
1576         /* If we freed a buffer, we can restart transmission, if necessary */
1577         if (netif_queue_stopped(dev) && priv->num_txbdfree)
1578                 netif_wake_queue(dev);
1579
1580         /* Update dirty indicators */
1581         priv->skb_dirtytx = skb_dirtytx;
1582         priv->dirty_tx = bdp;
1583
1584         dev->stats.tx_packets += howmany;
1585
1586         return howmany;
1587 }
1588
1589 /* Interrupt Handler for Transmit complete */
1590 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1591 {
1592         struct net_device *dev = (struct net_device *) dev_id;
1593         struct gfar_private *priv = netdev_priv(dev);
1594
1595         /* Clear IEVENT */
1596         gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1597
1598         /* Lock priv */
1599         spin_lock(&priv->txlock);
1600
1601         gfar_clean_tx_ring(dev);
1602
1603         /* If we are coalescing the interrupts, reset the timer */
1604         /* Otherwise, clear it */
1605         if (likely(priv->txcoalescing)) {
1606                 gfar_write(&priv->regs->txic, 0);
1607                 gfar_write(&priv->regs->txic, priv->txic);
1608         }
1609
1610         spin_unlock(&priv->txlock);
1611
1612         return IRQ_HANDLED;
1613 }
1614
1615 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1616                 struct sk_buff *skb)
1617 {
1618         struct gfar_private *priv = netdev_priv(dev);
1619         u32 lstatus;
1620
1621         bdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1622                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1623
1624         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
1625
1626         if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1627                 lstatus |= BD_LFLAG(RXBD_WRAP);
1628
1629         eieio();
1630
1631         bdp->lstatus = lstatus;
1632 }
1633
1634
1635 struct sk_buff * gfar_new_skb(struct net_device *dev)
1636 {
1637         unsigned int alignamount;
1638         struct gfar_private *priv = netdev_priv(dev);
1639         struct sk_buff *skb = NULL;
1640
1641         /* We have to allocate the skb, so keep trying till we succeed */
1642         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
1643
1644         if (!skb)
1645                 return NULL;
1646
1647         alignamount = RXBUF_ALIGNMENT -
1648                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1649
1650         /* We need the data buffer to be aligned properly.  We will reserve
1651          * as many bytes as needed to align the data properly
1652          */
1653         skb_reserve(skb, alignamount);
1654
1655         return skb;
1656 }
1657
1658 static inline void count_errors(unsigned short status, struct net_device *dev)
1659 {
1660         struct gfar_private *priv = netdev_priv(dev);
1661         struct net_device_stats *stats = &dev->stats;
1662         struct gfar_extra_stats *estats = &priv->extra_stats;
1663
1664         /* If the packet was truncated, none of the other errors
1665          * matter */
1666         if (status & RXBD_TRUNCATED) {
1667                 stats->rx_length_errors++;
1668
1669                 estats->rx_trunc++;
1670
1671                 return;
1672         }
1673         /* Count the errors, if there were any */
1674         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1675                 stats->rx_length_errors++;
1676
1677                 if (status & RXBD_LARGE)
1678                         estats->rx_large++;
1679                 else
1680                         estats->rx_short++;
1681         }
1682         if (status & RXBD_NONOCTET) {
1683                 stats->rx_frame_errors++;
1684                 estats->rx_nonoctet++;
1685         }
1686         if (status & RXBD_CRCERR) {
1687                 estats->rx_crcerr++;
1688                 stats->rx_crc_errors++;
1689         }
1690         if (status & RXBD_OVERRUN) {
1691                 estats->rx_overrun++;
1692                 stats->rx_crc_errors++;
1693         }
1694 }
1695
1696 irqreturn_t gfar_receive(int irq, void *dev_id)
1697 {
1698         struct net_device *dev = (struct net_device *) dev_id;
1699         struct gfar_private *priv = netdev_priv(dev);
1700         u32 tempval;
1701
1702         /* support NAPI */
1703         /* Clear IEVENT, so interrupts aren't called again
1704          * because of the packets that have already arrived */
1705         gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1706
1707         if (netif_rx_schedule_prep(dev, &priv->napi)) {
1708                 tempval = gfar_read(&priv->regs->imask);
1709                 tempval &= IMASK_RTX_DISABLED;
1710                 gfar_write(&priv->regs->imask, tempval);
1711
1712                 __netif_rx_schedule(dev, &priv->napi);
1713         } else {
1714                 if (netif_msg_rx_err(priv))
1715                         printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1716                                 dev->name, gfar_read(&priv->regs->ievent),
1717                                 gfar_read(&priv->regs->imask));
1718         }
1719
1720         return IRQ_HANDLED;
1721 }
1722
1723 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1724 {
1725         /* If valid headers were found, and valid sums
1726          * were verified, then we tell the kernel that no
1727          * checksumming is necessary.  Otherwise, it is */
1728         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1729                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1730         else
1731                 skb->ip_summed = CHECKSUM_NONE;
1732 }
1733
1734
1735 /* gfar_process_frame() -- handle one incoming packet if skb
1736  * isn't NULL.  */
1737 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1738                               int amount_pull)
1739 {
1740         struct gfar_private *priv = netdev_priv(dev);
1741         struct rxfcb *fcb = NULL;
1742
1743         int ret;
1744
1745         /* fcb is at the beginning if exists */
1746         fcb = (struct rxfcb *)skb->data;
1747
1748         /* Remove the FCB from the skb */
1749         /* Remove the padded bytes, if there are any */
1750         if (amount_pull)
1751                 skb_pull(skb, amount_pull);
1752
1753         if (priv->rx_csum_enable)
1754                 gfar_rx_checksum(skb, fcb);
1755
1756         /* Tell the skb what kind of packet this is */
1757         skb->protocol = eth_type_trans(skb, dev);
1758
1759         /* Send the packet up the stack */
1760         if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1761                 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
1762         else
1763                 ret = netif_receive_skb(skb);
1764
1765         if (NET_RX_DROP == ret)
1766                 priv->extra_stats.kernel_dropped++;
1767
1768         return 0;
1769 }
1770
1771 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1772  *   until the budget/quota has been reached. Returns the number
1773  *   of frames handled
1774  */
1775 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1776 {
1777         struct rxbd8 *bdp, *base;
1778         struct sk_buff *skb;
1779         int pkt_len;
1780         int amount_pull;
1781         int howmany = 0;
1782         struct gfar_private *priv = netdev_priv(dev);
1783
1784         /* Get the first full descriptor */
1785         bdp = priv->cur_rx;
1786         base = priv->rx_bd_base;
1787
1788         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
1789                 priv->padding;
1790
1791         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1792                 struct sk_buff *newskb;
1793                 rmb();
1794
1795                 /* Add another skb for the future */
1796                 newskb = gfar_new_skb(dev);
1797
1798                 skb = priv->rx_skbuff[priv->skb_currx];
1799
1800                 dma_unmap_single(&priv->dev->dev, bdp->bufPtr,
1801                                 priv->rx_buffer_size, DMA_FROM_DEVICE);
1802
1803                 /* We drop the frame if we failed to allocate a new buffer */
1804                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1805                                  bdp->status & RXBD_ERR)) {
1806                         count_errors(bdp->status, dev);
1807
1808                         if (unlikely(!newskb))
1809                                 newskb = skb;
1810                         else if (skb)
1811                                 dev_kfree_skb_any(skb);
1812                 } else {
1813                         /* Increment the number of packets */
1814                         dev->stats.rx_packets++;
1815                         howmany++;
1816
1817                         if (likely(skb)) {
1818                                 pkt_len = bdp->length - ETH_FCS_LEN;
1819                                 /* Remove the FCS from the packet length */
1820                                 skb_put(skb, pkt_len);
1821                                 dev->stats.rx_bytes += pkt_len;
1822
1823                                 gfar_process_frame(dev, skb, amount_pull);
1824
1825                         } else {
1826                                 if (netif_msg_rx_err(priv))
1827                                         printk(KERN_WARNING
1828                                                "%s: Missing skb!\n", dev->name);
1829                                 dev->stats.rx_dropped++;
1830                                 priv->extra_stats.rx_skbmissing++;
1831                         }
1832
1833                 }
1834
1835                 priv->rx_skbuff[priv->skb_currx] = newskb;
1836
1837                 /* Setup the new bdp */
1838                 gfar_new_rxbdp(dev, bdp, newskb);
1839
1840                 /* Update to the next pointer */
1841                 bdp = next_bd(bdp, base, priv->rx_ring_size);
1842
1843                 /* update to point at the next skb */
1844                 priv->skb_currx =
1845                     (priv->skb_currx + 1) &
1846                     RX_RING_MOD_MASK(priv->rx_ring_size);
1847         }
1848
1849         /* Update the current rxbd pointer to be the next one */
1850         priv->cur_rx = bdp;
1851
1852         return howmany;
1853 }
1854
1855 static int gfar_poll(struct napi_struct *napi, int budget)
1856 {
1857         struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1858         struct net_device *dev = priv->dev;
1859         int howmany;
1860         unsigned long flags;
1861
1862         /* If we fail to get the lock, don't bother with the TX BDs */
1863         if (spin_trylock_irqsave(&priv->txlock, flags)) {
1864                 gfar_clean_tx_ring(dev);
1865                 spin_unlock_irqrestore(&priv->txlock, flags);
1866         }
1867
1868         howmany = gfar_clean_rx_ring(dev, budget);
1869
1870         if (howmany < budget) {
1871                 netif_rx_complete(dev, napi);
1872
1873                 /* Clear the halt bit in RSTAT */
1874                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1875
1876                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1877
1878                 /* If we are coalescing interrupts, update the timer */
1879                 /* Otherwise, clear it */
1880                 if (likely(priv->rxcoalescing)) {
1881                         gfar_write(&priv->regs->rxic, 0);
1882                         gfar_write(&priv->regs->rxic, priv->rxic);
1883                 }
1884         }
1885
1886         return howmany;
1887 }
1888
1889 #ifdef CONFIG_NET_POLL_CONTROLLER
1890 /*
1891  * Polling 'interrupt' - used by things like netconsole to send skbs
1892  * without having to re-enable interrupts. It's not called while
1893  * the interrupt routine is executing.
1894  */
1895 static void gfar_netpoll(struct net_device *dev)
1896 {
1897         struct gfar_private *priv = netdev_priv(dev);
1898
1899         /* If the device has multiple interrupts, run tx/rx */
1900         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1901                 disable_irq(priv->interruptTransmit);
1902                 disable_irq(priv->interruptReceive);
1903                 disable_irq(priv->interruptError);
1904                 gfar_interrupt(priv->interruptTransmit, dev);
1905                 enable_irq(priv->interruptError);
1906                 enable_irq(priv->interruptReceive);
1907                 enable_irq(priv->interruptTransmit);
1908         } else {
1909                 disable_irq(priv->interruptTransmit);
1910                 gfar_interrupt(priv->interruptTransmit, dev);
1911                 enable_irq(priv->interruptTransmit);
1912         }
1913 }
1914 #endif
1915
1916 /* The interrupt handler for devices with one interrupt */
1917 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1918 {
1919         struct net_device *dev = dev_id;
1920         struct gfar_private *priv = netdev_priv(dev);
1921
1922         /* Save ievent for future reference */
1923         u32 events = gfar_read(&priv->regs->ievent);
1924
1925         /* Check for reception */
1926         if (events & IEVENT_RX_MASK)
1927                 gfar_receive(irq, dev_id);
1928
1929         /* Check for transmit completion */
1930         if (events & IEVENT_TX_MASK)
1931                 gfar_transmit(irq, dev_id);
1932
1933         /* Check for errors */
1934         if (events & IEVENT_ERR_MASK)
1935                 gfar_error(irq, dev_id);
1936
1937         return IRQ_HANDLED;
1938 }
1939
1940 /* Called every time the controller might need to be made
1941  * aware of new link state.  The PHY code conveys this
1942  * information through variables in the phydev structure, and this
1943  * function converts those variables into the appropriate
1944  * register values, and can bring down the device if needed.
1945  */
1946 static void adjust_link(struct net_device *dev)
1947 {
1948         struct gfar_private *priv = netdev_priv(dev);
1949         struct gfar __iomem *regs = priv->regs;
1950         unsigned long flags;
1951         struct phy_device *phydev = priv->phydev;
1952         int new_state = 0;
1953
1954         spin_lock_irqsave(&priv->txlock, flags);
1955         if (phydev->link) {
1956                 u32 tempval = gfar_read(&regs->maccfg2);
1957                 u32 ecntrl = gfar_read(&regs->ecntrl);
1958
1959                 /* Now we make sure that we can be in full duplex mode.
1960                  * If not, we operate in half-duplex mode. */
1961                 if (phydev->duplex != priv->oldduplex) {
1962                         new_state = 1;
1963                         if (!(phydev->duplex))
1964                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
1965                         else
1966                                 tempval |= MACCFG2_FULL_DUPLEX;
1967
1968                         priv->oldduplex = phydev->duplex;
1969                 }
1970
1971                 if (phydev->speed != priv->oldspeed) {
1972                         new_state = 1;
1973                         switch (phydev->speed) {
1974                         case 1000:
1975                                 tempval =
1976                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1977                                 break;
1978                         case 100:
1979                         case 10:
1980                                 tempval =
1981                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1982
1983                                 /* Reduced mode distinguishes
1984                                  * between 10 and 100 */
1985                                 if (phydev->speed == SPEED_100)
1986                                         ecntrl |= ECNTRL_R100;
1987                                 else
1988                                         ecntrl &= ~(ECNTRL_R100);
1989                                 break;
1990                         default:
1991                                 if (netif_msg_link(priv))
1992                                         printk(KERN_WARNING
1993                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
1994                                                 dev->name, phydev->speed);
1995                                 break;
1996                         }
1997
1998                         priv->oldspeed = phydev->speed;
1999                 }
2000
2001                 gfar_write(&regs->maccfg2, tempval);
2002                 gfar_write(&regs->ecntrl, ecntrl);
2003
2004                 if (!priv->oldlink) {
2005                         new_state = 1;
2006                         priv->oldlink = 1;
2007                 }
2008         } else if (priv->oldlink) {
2009                 new_state = 1;
2010                 priv->oldlink = 0;
2011                 priv->oldspeed = 0;
2012                 priv->oldduplex = -1;
2013         }
2014
2015         if (new_state && netif_msg_link(priv))
2016                 phy_print_status(phydev);
2017
2018         spin_unlock_irqrestore(&priv->txlock, flags);
2019 }
2020
2021 /* Update the hash table based on the current list of multicast
2022  * addresses we subscribe to.  Also, change the promiscuity of
2023  * the device based on the flags (this function is called
2024  * whenever dev->flags is changed */
2025 static void gfar_set_multi(struct net_device *dev)
2026 {
2027         struct dev_mc_list *mc_ptr;
2028         struct gfar_private *priv = netdev_priv(dev);
2029         struct gfar __iomem *regs = priv->regs;
2030         u32 tempval;
2031
2032         if(dev->flags & IFF_PROMISC) {
2033                 /* Set RCTRL to PROM */
2034                 tempval = gfar_read(&regs->rctrl);
2035                 tempval |= RCTRL_PROM;
2036                 gfar_write(&regs->rctrl, tempval);
2037         } else {
2038                 /* Set RCTRL to not PROM */
2039                 tempval = gfar_read(&regs->rctrl);
2040                 tempval &= ~(RCTRL_PROM);
2041                 gfar_write(&regs->rctrl, tempval);
2042         }
2043
2044         if(dev->flags & IFF_ALLMULTI) {
2045                 /* Set the hash to rx all multicast frames */
2046                 gfar_write(&regs->igaddr0, 0xffffffff);
2047                 gfar_write(&regs->igaddr1, 0xffffffff);
2048                 gfar_write(&regs->igaddr2, 0xffffffff);
2049                 gfar_write(&regs->igaddr3, 0xffffffff);
2050                 gfar_write(&regs->igaddr4, 0xffffffff);
2051                 gfar_write(&regs->igaddr5, 0xffffffff);
2052                 gfar_write(&regs->igaddr6, 0xffffffff);
2053                 gfar_write(&regs->igaddr7, 0xffffffff);
2054                 gfar_write(&regs->gaddr0, 0xffffffff);
2055                 gfar_write(&regs->gaddr1, 0xffffffff);
2056                 gfar_write(&regs->gaddr2, 0xffffffff);
2057                 gfar_write(&regs->gaddr3, 0xffffffff);
2058                 gfar_write(&regs->gaddr4, 0xffffffff);
2059                 gfar_write(&regs->gaddr5, 0xffffffff);
2060                 gfar_write(&regs->gaddr6, 0xffffffff);
2061                 gfar_write(&regs->gaddr7, 0xffffffff);
2062         } else {
2063                 int em_num;
2064                 int idx;
2065
2066                 /* zero out the hash */
2067                 gfar_write(&regs->igaddr0, 0x0);
2068                 gfar_write(&regs->igaddr1, 0x0);
2069                 gfar_write(&regs->igaddr2, 0x0);
2070                 gfar_write(&regs->igaddr3, 0x0);
2071                 gfar_write(&regs->igaddr4, 0x0);
2072                 gfar_write(&regs->igaddr5, 0x0);
2073                 gfar_write(&regs->igaddr6, 0x0);
2074                 gfar_write(&regs->igaddr7, 0x0);
2075                 gfar_write(&regs->gaddr0, 0x0);
2076                 gfar_write(&regs->gaddr1, 0x0);
2077                 gfar_write(&regs->gaddr2, 0x0);
2078                 gfar_write(&regs->gaddr3, 0x0);
2079                 gfar_write(&regs->gaddr4, 0x0);
2080                 gfar_write(&regs->gaddr5, 0x0);
2081                 gfar_write(&regs->gaddr6, 0x0);
2082                 gfar_write(&regs->gaddr7, 0x0);
2083
2084                 /* If we have extended hash tables, we need to
2085                  * clear the exact match registers to prepare for
2086                  * setting them */
2087                 if (priv->extended_hash) {
2088                         em_num = GFAR_EM_NUM + 1;
2089                         gfar_clear_exact_match(dev);
2090                         idx = 1;
2091                 } else {
2092                         idx = 0;
2093                         em_num = 0;
2094                 }
2095
2096                 if(dev->mc_count == 0)
2097                         return;
2098
2099                 /* Parse the list, and set the appropriate bits */
2100                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2101                         if (idx < em_num) {
2102                                 gfar_set_mac_for_addr(dev, idx,
2103                                                 mc_ptr->dmi_addr);
2104                                 idx++;
2105                         } else
2106                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2107                 }
2108         }
2109
2110         return;
2111 }
2112
2113
2114 /* Clears each of the exact match registers to zero, so they
2115  * don't interfere with normal reception */
2116 static void gfar_clear_exact_match(struct net_device *dev)
2117 {
2118         int idx;
2119         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2120
2121         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2122                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2123 }
2124
2125 /* Set the appropriate hash bit for the given addr */
2126 /* The algorithm works like so:
2127  * 1) Take the Destination Address (ie the multicast address), and
2128  * do a CRC on it (little endian), and reverse the bits of the
2129  * result.
2130  * 2) Use the 8 most significant bits as a hash into a 256-entry
2131  * table.  The table is controlled through 8 32-bit registers:
2132  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
2133  * gaddr7.  This means that the 3 most significant bits in the
2134  * hash index which gaddr register to use, and the 5 other bits
2135  * indicate which bit (assuming an IBM numbering scheme, which
2136  * for PowerPC (tm) is usually the case) in the register holds
2137  * the entry. */
2138 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2139 {
2140         u32 tempval;
2141         struct gfar_private *priv = netdev_priv(dev);
2142         u32 result = ether_crc(MAC_ADDR_LEN, addr);
2143         int width = priv->hash_width;
2144         u8 whichbit = (result >> (32 - width)) & 0x1f;
2145         u8 whichreg = result >> (32 - width + 5);
2146         u32 value = (1 << (31-whichbit));
2147
2148         tempval = gfar_read(priv->hash_regs[whichreg]);
2149         tempval |= value;
2150         gfar_write(priv->hash_regs[whichreg], tempval);
2151
2152         return;
2153 }
2154
2155
2156 /* There are multiple MAC Address register pairs on some controllers
2157  * This function sets the numth pair to a given address
2158  */
2159 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2160 {
2161         struct gfar_private *priv = netdev_priv(dev);
2162         int idx;
2163         char tmpbuf[MAC_ADDR_LEN];
2164         u32 tempval;
2165         u32 __iomem *macptr = &priv->regs->macstnaddr1;
2166
2167         macptr += num*2;
2168
2169         /* Now copy it into the mac registers backwards, cuz */
2170         /* little endian is silly */
2171         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2172                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2173
2174         gfar_write(macptr, *((u32 *) (tmpbuf)));
2175
2176         tempval = *((u32 *) (tmpbuf + 4));
2177
2178         gfar_write(macptr+1, tempval);
2179 }
2180
2181 /* GFAR error interrupt handler */
2182 static irqreturn_t gfar_error(int irq, void *dev_id)
2183 {
2184         struct net_device *dev = dev_id;
2185         struct gfar_private *priv = netdev_priv(dev);
2186
2187         /* Save ievent for future reference */
2188         u32 events = gfar_read(&priv->regs->ievent);
2189
2190         /* Clear IEVENT */
2191         gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2192
2193         /* Magic Packet is not an error. */
2194         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2195             (events & IEVENT_MAG))
2196                 events &= ~IEVENT_MAG;
2197
2198         /* Hmm... */
2199         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2200                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2201                        dev->name, events, gfar_read(&priv->regs->imask));
2202
2203         /* Update the error counters */
2204         if (events & IEVENT_TXE) {
2205                 dev->stats.tx_errors++;
2206
2207                 if (events & IEVENT_LC)
2208                         dev->stats.tx_window_errors++;
2209                 if (events & IEVENT_CRL)
2210                         dev->stats.tx_aborted_errors++;
2211                 if (events & IEVENT_XFUN) {
2212                         if (netif_msg_tx_err(priv))
2213                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2214                                        "packet dropped.\n", dev->name);
2215                         dev->stats.tx_dropped++;
2216                         priv->extra_stats.tx_underrun++;
2217
2218                         /* Reactivate the Tx Queues */
2219                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2220                 }
2221                 if (netif_msg_tx_err(priv))
2222                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2223         }
2224         if (events & IEVENT_BSY) {
2225                 dev->stats.rx_errors++;
2226                 priv->extra_stats.rx_bsy++;
2227
2228                 gfar_receive(irq, dev_id);
2229
2230                 if (netif_msg_rx_err(priv))
2231                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2232                                dev->name, gfar_read(&priv->regs->rstat));
2233         }
2234         if (events & IEVENT_BABR) {
2235                 dev->stats.rx_errors++;
2236                 priv->extra_stats.rx_babr++;
2237
2238                 if (netif_msg_rx_err(priv))
2239                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2240         }
2241         if (events & IEVENT_EBERR) {
2242                 priv->extra_stats.eberr++;
2243                 if (netif_msg_rx_err(priv))
2244                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
2245         }
2246         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2247                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2248
2249         if (events & IEVENT_BABT) {
2250                 priv->extra_stats.tx_babt++;
2251                 if (netif_msg_tx_err(priv))
2252                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2253         }
2254         return IRQ_HANDLED;
2255 }
2256
2257 /* work with hotplug and coldplug */
2258 MODULE_ALIAS("platform:fsl-gianfar");
2259
2260 static struct of_device_id gfar_match[] =
2261 {
2262         {
2263                 .type = "network",
2264                 .compatible = "gianfar",
2265         },
2266         {},
2267 };
2268
2269 /* Structure for a device driver */
2270 static struct of_platform_driver gfar_driver = {
2271         .name = "fsl-gianfar",
2272         .match_table = gfar_match,
2273
2274         .probe = gfar_probe,
2275         .remove = gfar_remove,
2276         .suspend = gfar_suspend,
2277         .resume = gfar_resume,
2278 };
2279
2280 static int __init gfar_init(void)
2281 {
2282         int err = gfar_mdio_init();
2283
2284         if (err)
2285                 return err;
2286
2287         err = of_register_platform_driver(&gfar_driver);
2288
2289         if (err)
2290                 gfar_mdio_exit();
2291
2292         return err;
2293 }
2294
2295 static void __exit gfar_exit(void)
2296 {
2297         of_unregister_platform_driver(&gfar_driver);
2298         gfar_mdio_exit();
2299 }
2300
2301 module_init(gfar_init);
2302 module_exit(gfar_exit);
2303