hal/usb_halinit.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #define _HCI_HAL_INIT_C_
  21
  22 #include <drv_conf.h>
  23 #include <osdep_service.h>
  24 #include <drv_types.h>
  25 #include <rtw_efuse.h>
  26
  27
  28 #include <HalPwrSeqCmd.h>
  29 #include <Hal8723PwrSeq.h>
  30 #include <rtl8723a_hal.h>
  31 #include <rtl8723a_led.h>
  32 #include <linux/ieee80211.h>
  33
  34 #ifdef CONFIG_IOL
  35 #include <rtw_iol.h>
  36 #endif
  37
  38 #ifdef CONFIG_EFUSE_CONFIG_FILE
  39 #include <linux/fs.h>
  40 #include <asm/uaccess.h>
  41 #endif //CONFIG_EFUSE_CONFIG_FILE
  42
  43 #include <usb_ops.h>
  44 #include <usb_hal.h>
  45 #include <usb_osintf.h>
  46
  47 #if DISABLE_BB_RF
  48         #define         HAL_MAC_ENABLE  0
  49         #define         HAL_BB_ENABLE           0
  50         #define         HAL_RF_ENABLE           0
  51 #else
  52         #define         HAL_MAC_ENABLE  1
  53         #define         HAL_BB_ENABLE           1
  54         #define         HAL_RF_ENABLE           1
  55 #endif
  56
  57
  58 static void
  59 _ConfigChipOutEP(
  60         PADAPTER        pAdapter,
  61         u8              NumOutPipe
  62         )
  63 {
  64         u8                      value8;
  65         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(pAdapter);
  66
  67         pHalData->OutEpQueueSel = 0;
  68         pHalData->OutEpNumber   = 0;
  69
  70         // Normal and High queue
  71         value8 = rtw_read8(pAdapter, (REG_NORMAL_SIE_EP + 1));
  72
  73         if(value8 & USB_NORMAL_SIE_EP_MASK){
  74                 pHalData->OutEpQueueSel |= TX_SELE_HQ;
  75                 pHalData->OutEpNumber++;
  76         }
  77
  78         if((value8 >> USB_NORMAL_SIE_EP_SHIFT) & USB_NORMAL_SIE_EP_MASK){
  79                 pHalData->OutEpQueueSel |= TX_SELE_NQ;
  80                 pHalData->OutEpNumber++;
  81         }
  82
  83         // Low queue
  84         value8 = rtw_read8(pAdapter, (REG_NORMAL_SIE_EP + 2));
  85         if(value8 & USB_NORMAL_SIE_EP_MASK){
  86                 pHalData->OutEpQueueSel |= TX_SELE_LQ;
  87                 pHalData->OutEpNumber++;
  88         }
  89
  90         // TODO: Error recovery for this case
  91         //RT_ASSERT((NumOutPipe == pHalData->OutEpNumber), ("Out EP number isn't match! %d(Descriptor) != %d (SIE reg)\n", (u32)NumOutPipe, (u32)pHalData->OutEpNumber));
  92
  93 }
  94
  95 static bool HalUsbSetQueuePipeMapping8192CUsb(
  96         PADAPTER        pAdapter,
  97         u8              NumInPipe,
  98         u8              NumOutPipe
  99         )
 100 {
 101         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(pAdapter);
 102         bool                    result          = _FALSE;
 103
 104         _ConfigChipOutEP(pAdapter, NumOutPipe);
 105
 106         // Normal chip with one IN and one OUT doesn't have interrupt IN EP.
 107         if(1 == pHalData->OutEpNumber){
 108                 if(1 != NumInPipe){
 109                         return result;
 110                 }
 111         }
 112
 113         result = Hal_MappingOutPipe(pAdapter, NumOutPipe);
 114
 115         return result;
 116
 117 }
 118
 119 void rtl8192cu_interface_configure(_adapter *padapter)
 120 {
 121         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(padapter);
 122         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
 123
 124         if (pdvobjpriv->ishighspeed == _TRUE)
 125         {
 126                 pHalData->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;//512 bytes
 127         }
 128         else
 129         {
 130                 pHalData->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;//64 bytes
 131         }
 132
 133         pHalData->interfaceIndex = pdvobjpriv->InterfaceNumber;
 134
 135 #ifdef CONFIG_USB_TX_AGGREGATION
 136         pHalData->UsbTxAggMode          = 1;
 137         pHalData->UsbTxAggDescNum       = 0x6;  // only 4 bits
 138 #endif
 139
 140 #ifdef CONFIG_USB_RX_AGGREGATION
 141         pHalData->UsbRxAggMode          = USB_RX_AGG_DMA;// USB_RX_AGG_DMA;
 142         pHalData->UsbRxAggBlockCount    = 8; //unit : 512b
 143         pHalData->UsbRxAggBlockTimeout  = 0x6;
 144         pHalData->UsbRxAggPageCount     = 48; //uint :128 b //0x0A;     // 10 = MAX_RX_DMA_BUFFER_SIZE/2/pHalData->UsbBulkOutSize
 145         pHalData->UsbRxAggPageTimeout   = 0x4; //6, absolute time = 34ms/(2^6)
 146 #endif
 147
 148         HalUsbSetQueuePipeMapping8192CUsb(padapter,
 149                                 pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes);
 150
 151 }
 152
 153 static u8 _InitPowerOn(PADAPTER padapter)
 154 {
 155         u8              status = _SUCCESS;
 156         u16                     value16=0;
 157         u8                      value8 = 0;
 158
 159         // RSV_CTRL 0x1C[7:0] = 0x00                    // unlock ISO/CLK/Power control register
 160         rtw_write8(padapter, REG_RSV_CTRL, 0x0);
 161
 162         // HW Power on sequence
 163         if(!HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, rtl8723A_card_enable_flow ))
 164                                 return _FAIL;
 165
 166         // 0x04[19] = 1, suggest by Jackie 2011.05.09, reset 8051
 167                         value8 = rtw_read8(padapter, REG_APS_FSMCO+2);
 168                         rtw_write8(padapter,REG_APS_FSMCO+2,(value8|BIT3));
 169
 170                         // Enable MAC DMA/WMAC/SCHEDULE/SEC block
 171                         // Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31.
 172                         value16 = rtw_read16(padapter, REG_CR);
 173                         value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
 174                                                 | PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC | CALTMR_EN);
 175                         rtw_write16(padapter, REG_CR, value16);
 176
 177         //for Efuse PG, suggest by Jackie 2011.11.23
 178         PHY_SetBBReg(padapter, REG_EFUSE_CTRL, BIT28|BIT29|BIT30, 0x06);
 179
 180         return status;
 181 }
 182
 183
 184 static void _dbg_dump_macreg(_adapter *padapter)
 185 {
 186         u32 offset = 0;
 187         u32 val32 = 0;
 188         u32 index =0 ;
 189         for(index=0;index<64;index++)
 190         {
 191                 offset = index*4;
 192                 val32 = rtw_read32(padapter,offset);
 193                 DBG_8723A("offset : 0x%02x ,val:0x%08x\n",offset,val32);
 194         }
 195 }
 196
 197 //-------------------------------------------------------------------------
 198 //
 199 // LLT R/W/Init function
 200 //
 201 //-------------------------------------------------------------------------
 202 static u8 _LLTWrite(
 203   PADAPTER      Adapter,
 204         u32             address,
 205         u32             data
 206         )
 207 {
 208         u8      status = _SUCCESS;
 209         int             count = 0;
 210         u32             value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
 211
 212         rtw_write32(Adapter, REG_LLT_INIT, value);
 213
 214         //polling
 215         do{
 216
 217                 value = rtw_read32(Adapter, REG_LLT_INIT);
 218                 if(_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)){
 219                         break;
 220                 }
 221
 222                 if(count > POLLING_LLT_THRESHOLD){
 223                         //RT_TRACE(COMP_INIT,DBG_SERIOUS,("Failed to polling write LLT done at address %d!\n", address));
 224                         status = _FAIL;
 225                         break;
 226                 }
 227         }while(count++);
 228
 229         return status;
 230
 231 }
 232
 233
 234 static u8 _LLTRead(
 235   PADAPTER      Adapter,
 236         u32             address
 237         )
 238 {
 239         int             count = 0;
 240         u32             value = _LLT_INIT_ADDR(address) | _LLT_OP(_LLT_READ_ACCESS);
 241
 242         rtw_write32(Adapter, REG_LLT_INIT, value);
 243
 244         //polling and get value
 245         do{
 246
 247                 value = rtw_read32(Adapter, REG_LLT_INIT);
 248                 if(_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)){
 249                         return (u8)value;
 250                 }
 251
 252                 if(count > POLLING_LLT_THRESHOLD){
 253                         //RT_TRACE(COMP_INIT,DBG_SERIOUS,("Failed to polling read LLT done at address %d!\n", address));
 254                         break;
 255                 }
 256         }while(count++);
 257
 258         return 0xFF;
 259
 260 }
 261
 262
 263 //---------------------------------------------------------------
 264 //
 265 //      MAC init functions
 266 //
 267 //---------------------------------------------------------------
 268 static void
 269 _SetMacID(
 270   PADAPTER Adapter, u8* MacID
 271         )
 272 {
 273         u32 i;
 274         for(i=0 ; i< MAC_ADDR_LEN ; i++){
 275 #ifdef  CONFIG_CONCURRENT_MODE
 276                 if(Adapter->iface_type == IFACE_PORT1)
 277                         rtw_write32(Adapter, REG_MACID1+i, MacID[i]);
 278                 else
 279 #endif
 280                 rtw_write32(Adapter, REG_MACID+i, MacID[i]);
 281         }
 282 }
 283
 284 static void
 285 _SetBSSID(
 286   PADAPTER Adapter, u8* BSSID
 287         )
 288 {
 289         u32 i;
 290         for(i=0 ; i< MAC_ADDR_LEN ; i++){
 291 #ifdef  CONFIG_CONCURRENT_MODE
 292                 if(Adapter->iface_type == IFACE_PORT1)
 293                         rtw_write32(Adapter, REG_BSSID1+i, BSSID[i]);
 294                 else
 295 #endif
 296                 rtw_write32(Adapter, REG_BSSID+i, BSSID[i]);
 297         }
 298 }
 299
 300
 301 // Shall USB interface init this?
 302 static void
 303 _InitInterrupt(
 304   PADAPTER Adapter
 305         )
 306 {
 307         u32     value32;
 308
 309         // HISR - turn all on
 310         value32 = 0xFFFFFFFF;
 311         rtw_write32(Adapter, REG_HISR, value32);
 312
 313         // HIMR - turn all on
 314         rtw_write32(Adapter, REG_HIMR, value32);
 315 }
 316
 317
 318 static void
 319 _InitQueueReservedPage(
 320   PADAPTER Adapter
 321         )
 322 {
 323         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 324         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 325
 326         u32                     outEPNum        = (u32)pHalData->OutEpNumber;
 327         u32                     numHQ           = 0;
 328         u32                     numLQ           = 0;
 329         u32                     numNQ           = 0;
 330         u32                     numPubQ;
 331         u32                     value32;
 332         u8                      value8;
 333         bool            bWiFiConfig     = pregistrypriv->wifi_spec;
 334         //u32                   txQPageNum, txQPageUnit,txQRemainPage;
 335
 336         { //for WMM
 337                 //RT_ASSERT((outEPNum>=2), ("for WMM ,number of out-ep must more than or equal to 2!\n"));
 338
 339                 numPubQ = bWiFiConfig?WMM_NORMAL_PAGE_NUM_PUBQ:NORMAL_PAGE_NUM_PUBQ;
 340
 341                 if (pHalData->OutEpQueueSel & TX_SELE_HQ)
 342                 {
 343                         numHQ = bWiFiConfig?WMM_NORMAL_PAGE_NUM_HPQ:NORMAL_PAGE_NUM_HPQ;
 344                 }
 345
 346                 if (pHalData->OutEpQueueSel & TX_SELE_LQ)
 347                 {
 348                         numLQ = bWiFiConfig?WMM_NORMAL_PAGE_NUM_LPQ:NORMAL_PAGE_NUM_LPQ;
 349                 }
 350                 // NOTE: This step shall be proceed before writting REG_RQPN.
 351                 if(pHalData->OutEpQueueSel & TX_SELE_NQ){
 352                         numNQ = bWiFiConfig?WMM_NORMAL_PAGE_NUM_NPQ:NORMAL_PAGE_NUM_NPQ;
 353                 }
 354                 value8 = (u8)_NPQ(numNQ);
 355                 rtw_write8(Adapter, REG_RQPN_NPQ, value8);
 356         }
 357
 358         // TX DMA
 359         value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
 360         rtw_write32(Adapter, REG_RQPN, value32);
 361 }
 362
 363 static void
 364 _InitTxBufferBoundary(
 365   PADAPTER Adapter
 366         )
 367 {
 368         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 369         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 370
 371         u8      txpktbuf_bndy;
 372
 373         if(!pregistrypriv->wifi_spec){
 374                 txpktbuf_bndy = TX_PAGE_BOUNDARY;
 375         }
 376         else{//for WMM
 377                 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY;
 378         }
 379
 380         rtw_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 381         rtw_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 382         rtw_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
 383         rtw_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy);
 384 #if 1
 385         rtw_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy);
 386 #else
 387         txdmactrl = PlatformIORead2Byte(Adapter, REG_TDECTRL);
 388         txdmactrl &= ~BCN_HEAD_MASK;
 389         txdmactrl |= BCN_HEAD(txpktbuf_bndy);
 390         PlatformIOWrite2Byte(Adapter, REG_TDECTRL, txdmactrl);
 391 #endif
 392 }
 393
 394 static void
 395 _InitPageBoundary(
 396   PADAPTER Adapter
 397         )
 398 {
 399         // RX Page Boundary
 400         //srand(static_cast<unsigned int>(time(NULL)) );
 401         u16 rxff_bndy = 0x27FF;//(rand() % 1) ? 0x27FF : 0x23FF;
 402
 403         rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
 404
 405         // TODO: ?? shall we set tx boundary?
 406 }
 407
 408
 409 static void
 410 _InitNormalChipRegPriority(
 411         PADAPTER        Adapter,
 412         u16             beQ,
 413         u16             bkQ,
 414         u16             viQ,
 415         u16             voQ,
 416         u16             mgtQ,
 417         u16             hiQ
 418         )
 419 {
 420         u16 value16             = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
 421
 422         value16 |=      _TXDMA_BEQ_MAP(beQ)     | _TXDMA_BKQ_MAP(bkQ) |
 423                                 _TXDMA_VIQ_MAP(viQ)     | _TXDMA_VOQ_MAP(voQ) |
 424                                 _TXDMA_MGQ_MAP(mgtQ)| _TXDMA_HIQ_MAP(hiQ);
 425
 426         rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
 427 }
 428
 429 static void
 430 _InitNormalChipOneOutEpPriority(
 431         PADAPTER Adapter
 432         )
 433 {
 434         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 435
 436         u16     value = 0;
 437         switch(pHalData->OutEpQueueSel)
 438         {
 439                 case TX_SELE_HQ:
 440                         value = QUEUE_HIGH;
 441                         break;
 442                 case TX_SELE_LQ:
 443                         value = QUEUE_LOW;
 444                         break;
 445                 case TX_SELE_NQ:
 446                         value = QUEUE_NORMAL;
 447                         break;
 448                 default:
 449                         //RT_ASSERT(FALSE,("Shall not reach here!\n"));
 450                         break;
 451         }
 452
 453         _InitNormalChipRegPriority(Adapter,
 454                                                                 value,
 455                                                                 value,
 456                                                                 value,
 457                                                                 value,
 458                                                                 value,
 459                                                                 value
 460                                                                 );
 461
 462 }
 463
 464 static void
 465 _InitNormalChipTwoOutEpPriority(
 466         PADAPTER Adapter
 467         )
 468 {
 469         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 470         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 471         u16                     beQ,bkQ,viQ,voQ,mgtQ,hiQ;
 472
 473
 474         u16     valueHi = 0;
 475         u16     valueLow = 0;
 476
 477         switch(pHalData->OutEpQueueSel)
 478         {
 479                 case (TX_SELE_HQ | TX_SELE_LQ):
 480                         valueHi = QUEUE_HIGH;
 481                         valueLow = QUEUE_LOW;
 482                         break;
 483                 case (TX_SELE_NQ | TX_SELE_LQ):
 484                         valueHi = QUEUE_NORMAL;
 485                         valueLow = QUEUE_LOW;
 486                         break;
 487                 case (TX_SELE_HQ | TX_SELE_NQ):
 488                         valueHi = QUEUE_HIGH;
 489                         valueLow = QUEUE_NORMAL;
 490                         break;
 491                 default:
 492                         //RT_ASSERT(FALSE,("Shall not reach here!\n"));
 493                         break;
 494         }
 495
 496         if(!pregistrypriv->wifi_spec ){
 497                 beQ             = valueLow;
 498                 bkQ             = valueLow;
 499                 viQ             = valueHi;
 500                 voQ             = valueHi;
 501                 mgtQ    = valueHi;
 502                 hiQ             = valueHi;
 503         }
 504         else{//for WMM ,CONFIG_OUT_EP_WIFI_MODE
 505                 beQ             = valueLow;
 506                 bkQ             = valueHi;
 507                 viQ             = valueHi;
 508                 voQ             = valueLow;
 509                 mgtQ    = valueHi;
 510                 hiQ             = valueHi;
 511         }
 512
 513         _InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
 514
 515 }
 516
 517 static void
 518 _InitNormalChipThreeOutEpPriority(
 519         PADAPTER Adapter
 520         )
 521 {
 522         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 523         u16                     beQ,bkQ,viQ,voQ,mgtQ,hiQ;
 524
 525         if(!pregistrypriv->wifi_spec ){// typical setting
 526                 beQ             = QUEUE_LOW;
 527                 bkQ             = QUEUE_LOW;
 528                 viQ             = QUEUE_NORMAL;
 529                 voQ             = QUEUE_HIGH;
 530                 mgtQ    = QUEUE_HIGH;
 531                 hiQ             = QUEUE_HIGH;
 532         }
 533         else{// for WMM
 534                 beQ             = QUEUE_LOW;
 535                 bkQ             = QUEUE_NORMAL;
 536                 viQ             = QUEUE_NORMAL;
 537                 voQ             = QUEUE_HIGH;
 538                 mgtQ    = QUEUE_HIGH;
 539                 hiQ             = QUEUE_HIGH;
 540         }
 541         _InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
 542 }
 543
 544 static void
 545 _InitNormalChipQueuePriority(
 546         PADAPTER Adapter
 547         )
 548 {
 549         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 550
 551         switch(pHalData->OutEpNumber)
 552         {
 553                 case 1:
 554                         _InitNormalChipOneOutEpPriority(Adapter);
 555                         break;
 556                 case 2:
 557                         _InitNormalChipTwoOutEpPriority(Adapter);
 558                         break;
 559                 case 3:
 560                         _InitNormalChipThreeOutEpPriority(Adapter);
 561                         break;
 562                 default:
 563                         //RT_ASSERT(FALSE,("Shall not reach here!\n"));
 564                         break;
 565         }
 566
 567
 568 }
 569
 570 static void
 571 _InitQueuePriority(
 572   PADAPTER Adapter
 573         )
 574 {
 575         _InitNormalChipQueuePriority(Adapter);
 576 }
 577
 578 static void
 579 _InitHardwareDropIncorrectBulkOut(
 580   PADAPTER Adapter
 581         )
 582 {
 583         u32     value32 = rtw_read32(Adapter, REG_TXDMA_OFFSET_CHK);
 584         value32 |= DROP_DATA_EN;
 585         rtw_write32(Adapter, REG_TXDMA_OFFSET_CHK, value32);
 586 }
 587
 588 static void
 589 _InitNetworkType(
 590   PADAPTER Adapter
 591         )
 592 {
 593         u32     value32;
 594
 595         value32 = rtw_read32(Adapter, REG_CR);
 596
 597         // TODO: use the other function to set network type
 598 #if RTL8191C_FPGA_NETWORKTYPE_ADHOC
 599         value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC);
 600 #else
 601         value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
 602 #endif
 603         rtw_write32(Adapter, REG_CR, value32);
 604 //      RASSERT(pIoBase->rtw_read8(REG_CR + 2) == 0x2);
 605 }
 606
 607 static void
 608 _InitTransferPageSize(
 609   PADAPTER Adapter
 610         )
 611 {
 612         // Tx page size is always 128.
 613
 614         u8      value8;
 615         value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
 616         rtw_write8(Adapter, REG_PBP, value8);
 617 }
 618
 619 static void
 620 _InitDriverInfoSize(
 621   PADAPTER      Adapter,
 622         u8              drvInfoSize
 623         )
 624 {
 625         rtw_write8(Adapter,REG_RX_DRVINFO_SZ, drvInfoSize);
 626 }
 627
 628 static void
 629 _InitWMACSetting(
 630   PADAPTER Adapter
 631         )
 632 {
 633         //u32                   value32;
 634         //u16                   value16;
 635         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 636
 637         //pHalData->ReceiveConfig = AAP | APM | AM | AB | APP_ICV | ADF | AMF | APP_FCS | HTC_LOC_CTRL | APP_MIC | APP_PHYSTS;
 638         //pHalData->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AB |RCR_CBSSID_DATA| RCR_CBSSID_BCN| RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYSTS;
 639          // don't turn on AAP, it will allow all packets to driver
 640         pHalData->ReceiveConfig = RCR_APM | RCR_AM | RCR_AB |RCR_CBSSID_DATA| RCR_CBSSID_BCN| RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYSTS;
 641 #if (1 == RTL8192C_RX_PACKET_INCLUDE_CRC)
 642         pHalData->ReceiveConfig |= ACRC32;
 643 #endif
 644
 645         // some REG_RCR will be modified later by phy_ConfigMACWithHeaderFile()
 646         rtw_write32(Adapter, REG_RCR, pHalData->ReceiveConfig);
 647
 648         // Accept all multicast address
 649         rtw_write32(Adapter, REG_MAR, 0xFFFFFFFF);
 650         rtw_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF);
 651
 652
 653         // Accept all data frames
 654         //value16 = 0xFFFF;
 655         //rtw_write16(Adapter, REG_RXFLTMAP2, value16);
 656
 657         // 2010.09.08 hpfan
 658         // Since ADF is removed from RCR, ps-poll will not be indicate to driver,
 659         // RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll.
 660         //value16 = 0x400;
 661         //rtw_write16(Adapter, REG_RXFLTMAP1, value16);
 662
 663         // Accept all management frames
 664         //value16 = 0xFFFF;
 665         //rtw_write16(Adapter, REG_RXFLTMAP0, value16);
 666
 667         //enable RX_SHIFT bits
 668         //rtw_write8(Adapter, REG_TRXDMA_CTRL, rtw_read8(Adapter, REG_TRXDMA_CTRL)|BIT(1));
 669
 670 }
 671
 672 static void
 673 _InitAdaptiveCtrl(
 674   PADAPTER Adapter
 675         )
 676 {
 677         u16     value16;
 678         u32     value32;
 679
 680         // Response Rate Set
 681         value32 = rtw_read32(Adapter, REG_RRSR);
 682         value32 &= ~RATE_BITMAP_ALL;
 683         value32 |= RATE_RRSR_CCK_ONLY_1M;
 684         rtw_write32(Adapter, REG_RRSR, value32);
 685
 686         // CF-END Threshold
 687         //m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1);
 688
 689         // SIFS (used in NAV)
 690         value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
 691         rtw_write16(Adapter, REG_SPEC_SIFS, value16);
 692
 693         // Retry Limit
 694         value16 = _LRL(0x30) | _SRL(0x30);
 695         rtw_write16(Adapter, REG_RL, value16);
 696
 697 }
 698
 699 static void
 700 _InitRateFallback(
 701   PADAPTER Adapter
 702         )
 703 {
 704         // Set Data Auto Rate Fallback Retry Count register.
 705         rtw_write32(Adapter, REG_DARFRC, 0x00000000);
 706         rtw_write32(Adapter, REG_DARFRC+4, 0x10080404);
 707         rtw_write32(Adapter, REG_RARFRC, 0x04030201);
 708         rtw_write32(Adapter, REG_RARFRC+4, 0x08070605);
 709
 710 }
 711
 712
 713 static void
 714 _InitEDCA(
 715   PADAPTER Adapter
 716         )
 717 {
 718         // Set Spec SIFS (used in NAV)
 719         rtw_write16(Adapter,REG_SPEC_SIFS, 0x100a);
 720         rtw_write16(Adapter,REG_MAC_SPEC_SIFS, 0x100a);
 721
 722         // Set SIFS for CCK
 723         rtw_write16(Adapter,REG_SIFS_CTX, 0x100a);
 724
 725         // Set SIFS for OFDM
 726         rtw_write16(Adapter,REG_SIFS_TRX, 0x100a);
 727
 728         // TXOP
 729         rtw_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
 730         rtw_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
 731         rtw_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
 732         rtw_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
 733 }
 734
 735 #ifdef CONFIG_LED
 736 static void _InitHWLed(PADAPTER Adapter)
 737 {
 738         struct led_priv *pledpriv = &(Adapter->ledpriv);
 739
 740         if( pledpriv->LedStrategy != HW_LED)
 741                 return;
 742
 743 // HW led control
 744 // to do ....
 745 //must consider cases of antenna diversity/ commbo card/solo card/mini card
 746
 747 }
 748 #endif //CONFIG_LED
 749
 750 static void
 751 _InitRDGSetting(
 752         PADAPTER Adapter
 753         )
 754 {
 755         rtw_write8(Adapter,REG_RD_CTRL,0xFF);
 756         rtw_write16(Adapter, REG_RD_NAV_NXT, 0x200);
 757         rtw_write8(Adapter,REG_RD_RESP_PKT_TH,0x05);
 758 }
 759
 760 static void
 761 _InitRxSetting(
 762         PADAPTER Adapter
 763         )
 764 {
 765         rtw_write32(Adapter, REG_MACID, 0x87654321);
 766         rtw_write32(Adapter, 0x0700, 0x87654321);
 767 }
 768
 769 static void
 770 _InitRetryFunction(
 771   PADAPTER Adapter
 772         )
 773 {
 774         u8      value8;
 775
 776         value8 = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL);
 777         value8 |= EN_AMPDU_RTY_NEW;
 778         rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
 779
 780         // Set ACK timeout
 781         rtw_write8(Adapter, REG_ACKTO, 0x40);
 782 }
 783
 784 /*-----------------------------------------------------------------------------
 785  * Function:    usb_AggSettingTxUpdate()
 786  *
 787  * Overview:    Seperate TX/RX parameters update independent for TP detection and
 788  *                      dynamic TX/RX aggreagtion parameters update.
 789  *
 790  * Input:                       PADAPTER
 791  *
 792  * Output/Return:       NONE
 793  *
 794  * Revised History:
 795  *      When            Who             Remark
 796  *      12/10/2010      MHC             Seperate to smaller function.
 797  *
 798  *---------------------------------------------------------------------------*/
 799 static void
 800 usb_AggSettingTxUpdate(
 801         PADAPTER                        Adapter
 802         )
 803 {
 804 #ifdef CONFIG_USB_TX_AGGREGATION
 805         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 806         //PMGNT_INFO            pMgntInfo = &(Adapter->MgntInfo);
 807         u32                     value32;
 808
 809         if(Adapter->registrypriv.wifi_spec)
 810                 pHalData->UsbTxAggMode = _FALSE;
 811
 812         if(pHalData->UsbTxAggMode){
 813                 value32 = rtw_read32(Adapter, REG_TDECTRL);
 814                 value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT);
 815                 value32 |= ((pHalData->UsbTxAggDescNum & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT);
 816
 817                 rtw_write32(Adapter, REG_TDECTRL, value32);
 818         }
 819
 820 #endif
 821 }       // usb_AggSettingTxUpdate
 822
 823
 824 /*-----------------------------------------------------------------------------
 825  * Function:    usb_AggSettingRxUpdate()
 826  *
 827  * Overview:    Seperate TX/RX parameters update independent for TP detection and
 828  *                      dynamic TX/RX aggreagtion parameters update.
 829  *
 830  * Input:                       PADAPTER
 831  *
 832  * Output/Return:       NONE
 833  *
 834  * Revised History:
 835  *      When            Who             Remark
 836  *      12/10/2010      MHC             Seperate to smaller function.
 837  *
 838  *---------------------------------------------------------------------------*/
 839 static void
 840 usb_AggSettingRxUpdate(
 841         PADAPTER                        Adapter
 842         )
 843 {
 844 #ifdef CONFIG_USB_RX_AGGREGATION
 845         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 846         //PMGNT_INFO            pMgntInfo = &(Adapter->MgntInfo);
 847         u8                      valueDMA;
 848         u8                      valueUSB;
 849
 850         valueDMA = rtw_read8(Adapter, REG_TRXDMA_CTRL);
 851         valueUSB = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION);
 852
 853         switch(pHalData->UsbRxAggMode)
 854         {
 855                 case USB_RX_AGG_DMA:
 856                         valueDMA |= RXDMA_AGG_EN;
 857                         valueUSB &= ~USB_AGG_EN;
 858                         break;
 859                 case USB_RX_AGG_USB:
 860                         valueDMA &= ~RXDMA_AGG_EN;
 861                         valueUSB |= USB_AGG_EN;
 862                         break;
 863                 case USB_RX_AGG_MIX:
 864                         valueDMA |= RXDMA_AGG_EN;
 865                         valueUSB |= USB_AGG_EN;
 866                         break;
 867                 case USB_RX_AGG_DISABLE:
 868                 default:
 869                         valueDMA &= ~RXDMA_AGG_EN;
 870                         valueUSB &= ~USB_AGG_EN;
 871                         break;
 872         }
 873
 874         rtw_write8(Adapter, REG_TRXDMA_CTRL, valueDMA);
 875         rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, valueUSB);
 876
 877         switch(pHalData->UsbRxAggMode)
 878         {
 879                 case USB_RX_AGG_DMA:
 880                         rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, pHalData->UsbRxAggPageCount);
 881                         rtw_write8(Adapter, REG_USB_DMA_AGG_TO, pHalData->UsbRxAggPageTimeout);
 882                         break;
 883                 case USB_RX_AGG_USB:
 884                         rtw_write8(Adapter, REG_USB_AGG_TH, pHalData->UsbRxAggBlockCount);
 885                         rtw_write8(Adapter, REG_USB_AGG_TO, pHalData->UsbRxAggBlockTimeout);
 886                         break;
 887                 case USB_RX_AGG_MIX:
 888                         rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, pHalData->UsbRxAggPageCount);
 889                         rtw_write8(Adapter, REG_USB_DMA_AGG_TO, pHalData->UsbRxAggPageTimeout);
 890                         rtw_write8(Adapter, REG_USB_AGG_TH, pHalData->UsbRxAggBlockCount);
 891                         rtw_write8(Adapter, REG_USB_AGG_TO, pHalData->UsbRxAggBlockTimeout);
 892                         break;
 893                 case USB_RX_AGG_DISABLE:
 894                 default:
 895                         // TODO:
 896                         break;
 897         }
 898
 899         switch(PBP_128)
 900         {
 901                 case PBP_128:
 902                         pHalData->HwRxPageSize = 128;
 903                         break;
 904                 case PBP_64:
 905                         pHalData->HwRxPageSize = 64;
 906                         break;
 907                 case PBP_256:
 908                         pHalData->HwRxPageSize = 256;
 909                         break;
 910                 case PBP_512:
 911                         pHalData->HwRxPageSize = 512;
 912                         break;
 913                 case PBP_1024:
 914                         pHalData->HwRxPageSize = 1024;
 915                         break;
 916                 default:
 917                         //RT_ASSERT(FALSE, ("RX_PAGE_SIZE_REG_VALUE definition is incorrect!\n"));
 918                         break;
 919         }
 920 #endif
 921 }       // usb_AggSettingRxUpdate
 922
 923 static void
 924 InitUsbAggregationSetting(
 925   PADAPTER Adapter
 926         )
 927 {
 928         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 929
 930         // Tx aggregation setting
 931         usb_AggSettingTxUpdate(Adapter);
 932
 933         // Rx aggregation setting
 934         usb_AggSettingRxUpdate(Adapter);
 935
 936         // 201/12/10 MH Add for USB agg mode dynamic switch.
 937         pHalData->UsbRxHighSpeedMode = _FALSE;
 938 }
 939
 940 /*-----------------------------------------------------------------------------
 941  * Function:    USB_AggModeSwitch()
 942  *
 943  * Overview:    When RX traffic is more than 40M, we need to adjust some parameters to increase
 944  *                      RX speed by increasing batch indication size. This will decrease TCP ACK speed, we
 945  *                      need to monitor the influence of FTP/network share.
 946  *                      For TX mode, we are still ubder investigation.
 947  *
 948  * Input:               PADAPTER
 949  *
 950  * Output:              NONE
 951  *
 952  * Return:              NONE
 953  *
 954  * Revised History:
 955  *      When            Who             Remark
 956  *      12/10/2010      MHC             Create Version 0.
 957  *
 958  *---------------------------------------------------------------------------*/
 959 void
 960 USB_AggModeSwitch(
 961         PADAPTER                        Adapter
 962         )
 963 {
 964 }       // USB_AggModeSwitch
 965
 966 static void
 967 _InitOperationMode(
 968         PADAPTER                        Adapter
 969         )
 970 {
 971 }
 972
 973 static void
 974 _InitRFType(
 975         PADAPTER Adapter
 976         )
 977 {
 978         struct registry_priv     *pregpriv = &Adapter->registrypriv;
 979         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 980         bool                    is92CU          = IS_92C_SERIAL(pHalData->VersionID);
 981
 982 #if     DISABLE_BB_RF
 983         pHalData->rf_chip       = RF_PSEUDO_11N;
 984         return;
 985 #endif
 986
 987         pHalData->rf_chip       = RF_6052;
 988
 989         if(_FALSE == is92CU){
 990                 pHalData->rf_type = RF_1T1R;
 991                 DBG_8723A("Set RF Chip ID to RF_6052 and RF type to 1T1R.\n");
 992                 return;
 993         }
 994
 995         // TODO: Consider that EEPROM set 92CU to 1T1R later.
 996         // Force to overwrite setting according to chip version. Ignore EEPROM setting.
 997         //pHalData->RF_Type = is92CU ? RF_2T2R : RF_1T1R;
 998         MSG_8723A("Set RF Chip ID to RF_6052 and RF type to %d.\n", pHalData->rf_type);
 999
1000 }
1001
1002 static void _InitAdhocWorkaroundParams(PADAPTER Adapter)
1003 {
1004 #ifdef RTL8192CU_ADHOC_WORKAROUND_SETTING
1005         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1006         pHalData->RegBcnCtrlVal = rtw_read8(Adapter, REG_BCN_CTRL);
1007         pHalData->RegTxPause = rtw_read8(Adapter, REG_TXPAUSE);
1008         pHalData->RegFwHwTxQCtrl = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL+2);
1009         pHalData->RegReg542 = rtw_read8(Adapter, REG_TBTT_PROHIBIT+2);
1010 #endif
1011 }
1012
1013 // Set CCK and OFDM Block "ON"
1014 static void _BBTurnOnBlock(
1015         PADAPTER                Adapter
1016         )
1017 {
1018 #if (DISABLE_BB_RF)
1019         return;
1020 #endif
1021
1022         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
1023         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
1024 }
1025
1026 #define MgntActSet_RF_State(...)
1027 static void _RfPowerSave(PADAPTER padapter)
1028 {
1029 }
1030
1031 enum {
1032         Antenna_Lfet = 1,
1033         Antenna_Right = 2,
1034 };
1035
1036 //
1037 // 2010/08/09 MH Add for power down check.
1038 //
1039 static bool
1040 HalDetectPwrDownMode(
1041  PADAPTER                               Adapter
1042         )
1043 {
1044         u8      tmpvalue;
1045         HAL_DATA_TYPE           *pHalData       = GET_HAL_DATA(Adapter);
1046         struct pwrctrl_priv             *pwrctrlpriv = &Adapter->pwrctrlpriv;
1047
1048         EFUSE_ShadowRead(Adapter, 1, EEPROM_RF_OPT3, (u32 *)&tmpvalue);
1049
1050         // 2010/08/25 MH INF priority > PDN Efuse value.
1051         if(tmpvalue & BIT4 && pwrctrlpriv->reg_pdnmode)
1052         {
1053                 pHalData->pwrdown = _TRUE;
1054         }
1055         else
1056         {
1057                 pHalData->pwrdown = _FALSE;
1058         }
1059
1060         DBG_8723A("HalDetectPwrDownMode(): PDN=%d\n", pHalData->pwrdown);
1061         return pHalData->pwrdown;
1062
1063 }       // HalDetectPwrDownMode
1064
1065
1066 //
1067 // 2010/08/26 MH Add for selective suspend mode check.
1068 // If Efuse 0x0e bit1 is not enabled, we can not support selective suspend for Minicard and
1069 // slim card.
1070 //
1071 static void
1072 HalDetectSelectiveSuspendMode(
1073  PADAPTER                               Adapter
1074         )
1075 {
1076         u8      tmpvalue;
1077         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1078         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(Adapter);
1079
1080         // If support HW radio detect, we need to enable WOL ability, otherwise, we
1081         // can not use FW to notify host the power state switch.
1082
1083         EFUSE_ShadowRead(Adapter, 1, EEPROM_USB_OPTIONAL1, (u32 *)&tmpvalue);
1084
1085         DBG_8723A("HalDetectSelectiveSuspendMode(): SS ");
1086         if(tmpvalue & BIT1)
1087         {
1088                 DBG_8723A("Enable\n");
1089         }
1090         else
1091         {
1092                 DBG_8723A("Disable\n");
1093                 pdvobjpriv->RegUsbSS = _FALSE;
1094         }
1095
1096         // 2010/09/01 MH According to Dongle Selective Suspend INF. We can switch SS mode.
1097         if (pdvobjpriv->RegUsbSS && !SUPPORT_HW_RADIO_DETECT(pHalData))
1098         {
1099                 //PMGNT_INFO                            pMgntInfo = &(Adapter->MgntInfo);
1100
1101                 //if (!pMgntInfo->bRegDongleSS)
1102                 //{
1103                 //      RT_TRACE(COMP_INIT, DBG_LOUD, ("Dongle disable SS\n"));
1104                         pdvobjpriv->RegUsbSS = _FALSE;
1105                 //}
1106         }
1107 }       // HalDetectSelectiveSuspendMode
1108 /*-----------------------------------------------------------------------------
1109  * Function:    HwSuspendModeEnable92Cu()
1110  *
1111  * Overview:    HW suspend mode switch.
1112  *
1113  * Input:               NONE
1114  *
1115  * Output:      NONE
1116  *
1117  * Return:      NONE
1118  *
1119  * Revised History:
1120  *      When            Who             Remark
1121  *      08/23/2010      MHC             HW suspend mode switch test..
1122  *---------------------------------------------------------------------------*/
1123 static void
1124 HwSuspendModeEnable92Cu(
1125         PADAPTER        pAdapter,
1126         u8                      Type
1127         )
1128 {
1129 }       // HwSuspendModeEnable92Cu
1130
1131 rt_rf_power_state RfOnOffDetect(PADAPTER pAdapter )
1132 {
1133         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(pAdapter);
1134         u8      val8;
1135         rt_rf_power_state rfpowerstate = rf_off;
1136
1137         if(pAdapter->pwrctrlpriv.bHWPowerdown)
1138         {
1139                 val8 = rtw_read8(pAdapter, REG_HSISR);
1140                 DBG_8723A("pwrdown, 0x5c(BIT7)=%02x\n", val8);
1141                 rfpowerstate = (val8 & BIT7) ? rf_off: rf_on;
1142         }
1143         else // rf on/off
1144         {
1145                 rtw_write8(     pAdapter, REG_MAC_PINMUX_CFG,rtw_read8(pAdapter, REG_MAC_PINMUX_CFG)&~(BIT3));
1146                 val8 = rtw_read8(pAdapter, REG_GPIO_IO_SEL);
1147                 DBG_8723A("GPIO_IN=%02x\n", val8);
1148                 rfpowerstate = (val8 & BIT3) ? rf_on : rf_off;
1149         }
1150         return rfpowerstate;
1151 }       // HalDetectPwrDownMode
1152
1153 void _ps_open_RF(_adapter *padapter);
1154
1155 u32 rtl8723au_hal_init(PADAPTER Adapter)
1156 {
1157         u8      val8 = 0;
1158         u32     boundary, status = _SUCCESS;
1159         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
1160         struct pwrctrl_priv             *pwrctrlpriv = &Adapter->pwrctrlpriv;
1161         struct registry_priv    *pregistrypriv = &Adapter->registrypriv;
1162         u8      is92C = IS_92C_SERIAL(pHalData->VersionID);
1163         rt_rf_power_state               eRfPowerStateToSet;
1164         u32 NavUpper = WiFiNavUpperUs;
1165
1166         u32 init_start_time = rtw_get_current_time();
1167
1168
1169 #ifdef DBG_HAL_INIT_PROFILING
1170
1171         enum HAL_INIT_STAGES {
1172                 HAL_INIT_STAGES_BEGIN = 0,
1173                 HAL_INIT_STAGES_INIT_PW_ON,
1174                 HAL_INIT_STAGES_INIT_LLTT,
1175                 HAL_INIT_STAGES_MISC01,
1176                 HAL_INIT_STAGES_DOWNLOAD_FW,
1177                 HAL_INIT_STAGES_MAC,
1178                 HAL_INIT_STAGES_BB,
1179                 HAL_INIT_STAGES_RF,
1180                 HAL_INIT_STAGES_MISC02,
1181                 HAL_INIT_STAGES_TURN_ON_BLOCK,
1182                 HAL_INIT_STAGES_INIT_SECURITY,
1183                 HAL_INIT_STAGES_MISC11,
1184                 //HAL_INIT_STAGES_RF_PS,
1185                 HAL_INIT_STAGES_IQK,
1186                 HAL_INIT_STAGES_PW_TRACK,
1187                 HAL_INIT_STAGES_LCK,
1188                 HAL_INIT_STAGES_MISC21,
1189                 //HAL_INIT_STAGES_INIT_PABIAS,
1190                 #ifdef CONFIG_BT_COEXIST
1191                 HAL_INIT_STAGES_BT_COEXIST,
1192                 #endif
1193                 //HAL_INIT_STAGES_ANTENNA_SEL,
1194                 HAL_INIT_STAGES_INIT_HAL_DM,
1195                 HAL_INIT_STAGES_MISC31,
1196                 HAL_INIT_STAGES_END,
1197                 HAL_INIT_STAGES_NUM
1198         };
1199
1200         char * hal_init_stages_str[] = {
1201                 "HAL_INIT_STAGES_BEGIN",
1202                 "HAL_INIT_STAGES_INIT_PW_ON",
1203                 "HAL_INIT_STAGES_INIT_LLTT",
1204                 "HAL_INIT_STAGES_MISC01",
1205                 "HAL_INIT_STAGES_DOWNLOAD_FW",
1206                 "HAL_INIT_STAGES_MAC",
1207                 "HAL_INIT_STAGES_BB",
1208                 "HAL_INIT_STAGES_RF",
1209                 "HAL_INIT_STAGES_MISC02",
1210                 "HAL_INIT_STAGES_TURN_ON_BLOCK",
1211                 "HAL_INIT_STAGES_INIT_SECURITY",
1212                 "HAL_INIT_STAGES_MISC11",
1213                 //"HAL_INIT_STAGES_RF_PS",
1214                 "HAL_INIT_STAGES_IQK",
1215                 "HAL_INIT_STAGES_PW_TRACK",
1216                 "HAL_INIT_STAGES_LCK",
1217                 "HAL_INIT_STAGES_MISC21",
1218                 //"HAL_INIT_STAGES_INIT_PABIAS",
1219                 #ifdef CONFIG_BT_COEXIST
1220                 "HAL_INIT_STAGES_BT_COEXIST",
1221                 #endif
1222                 //"HAL_INIT_STAGES_ANTENNA_SEL",
1223                 "HAL_INIT_STAGES_INIT_HAL_DM",
1224                 "HAL_INIT_STAGES_MISC31",
1225                 "HAL_INIT_STAGES_END",
1226         };
1227
1228         int hal_init_profiling_i;
1229         u32 hal_init_stages_timestamp[HAL_INIT_STAGES_NUM]; //used to record the time of each stage's starting point
1230
1231         for(hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM;hal_init_profiling_i++)
1232                 hal_init_stages_timestamp[hal_init_profiling_i]=0;
1233
1234         #define HAL_INIT_PROFILE_TAG(stage) hal_init_stages_timestamp[(stage)]=rtw_get_current_time();
1235 #else
1236         #define HAL_INIT_PROFILE_TAG(stage) do {} while(0)
1237 #endif //DBG_HAL_INIT_PROFILING
1238
1239
1240
1241 _func_enter_;
1242
1243 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
1244         if(Adapter->pwrctrlpriv.bkeepfwalive)
1245         {
1246                 _ps_open_RF(Adapter);
1247
1248                 if(pHalData->bIQKInitialized ){
1249                         rtl8192c_PHY_IQCalibrate(Adapter,_TRUE);
1250                 }
1251                 else{
1252                         rtl8192c_PHY_IQCalibrate(Adapter,_FALSE);
1253                         pHalData->bIQKInitialized = _TRUE;
1254                 }
1255                 rtl8192c_odm_CheckTXPowerTracking(Adapter);
1256                 rtl8192c_PHY_LCCalibrate(Adapter);
1257
1258                 goto exit;
1259         }
1260
1261 //      pHalData->bMACFuncEnable = _FALSE;
1262         // Check if MAC has already power on. by tynli. 2011.05.27.
1263         val8 = rtw_read8(Adapter, REG_CR);
1264         RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1265                          ("%s: REG_CR 0x100=0x%02x\n", __FUNCTION__, val8));
1266         //Fix 92DU-VC S3 hang with the reason is that secondary mac is not initialized.
1267         //0x100 value of first mac is 0xEA while 0x100 value of secondary is 0x00
1268         //by sherry 20111102
1269         if (val8 == 0xEA) {
1270                 pHalData->bMACFuncEnable = _FALSE;
1271         } else {
1272                 pHalData->bMACFuncEnable = _TRUE;
1273                 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1274                                  ("%s: MAC has already power on\n", __FUNCTION__));
1275         }
1276
1277 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
1278         status = _InitPowerOn(Adapter);
1279         if(status == _FAIL){
1280                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init power on!\n"));
1281                 goto exit;
1282         }
1283
1284 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
1285         if (!pregistrypriv->wifi_spec) {
1286                 boundary = TX_PAGE_BOUNDARY;
1287         } else {
1288                 // for WMM
1289                 boundary = WMM_NORMAL_TX_PAGE_BOUNDARY;
1290         }
1291
1292         if (!pHalData->bMACFuncEnable)
1293         {
1294                 status =  InitLLTTable(Adapter, boundary);
1295                 if(status == _FAIL){
1296                         RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT table\n"));
1297                         goto exit;
1298                 }
1299         }
1300
1301
1302 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01);
1303         if(pHalData->bRDGEnable){
1304                 _InitRDGSetting(Adapter);
1305         }
1306
1307
1308 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
1309 {
1310         status = rtl8723a_FirmwareDownload(Adapter);
1311         if(status != _SUCCESS)
1312         {
1313                 Adapter->bFWReady = _FALSE;
1314                 pHalData->fw_ractrl = _FALSE;
1315                 DBG_8723A("fw download fail!\n");
1316                 goto exit;
1317         }
1318         else
1319         {
1320                 Adapter->bFWReady = _TRUE;
1321                 pHalData->fw_ractrl = _TRUE;
1322                 DBG_8723A("fw download ok!\n");
1323         }
1324 }
1325
1326         rtl8723a_InitializeFirmwareVars(Adapter);
1327
1328         if(pwrctrlpriv->reg_rfoff == _TRUE){
1329                 pwrctrlpriv->rf_pwrstate = rf_off;
1330         }
1331
1332         // 2010/08/09 MH We need to check if we need to turnon or off RF after detecting
1333         // HW GPIO pin. Before PHY_RFConfig8192C.
1334         //HalDetectPwrDownMode(Adapter);
1335         // 2010/08/26 MH If Efuse does not support sective suspend then disable the function.
1336         //HalDetectSelectiveSuspendMode(Adapter);
1337
1338         // Set RF type for BB/RF configuration
1339         _InitRFType(Adapter);//->_ReadRFType()
1340
1341         // Save target channel
1342         // <Roger_Notes> Current Channel will be updated again later.
1343         pHalData->CurrentChannel = 6;//default set to 6
1344
1345
1346 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
1347 #if (HAL_MAC_ENABLE == 1)
1348         status = PHY_MACConfig8723A(Adapter);
1349         if(status == _FAIL)
1350         {
1351                 DBG_8723A("PHY_MACConfig8723A fault !!\n");
1352                 goto exit;
1353         }
1354 #endif
1355
1356
1357 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB);
1358         //
1359         //d. Initialize BB related configurations.
1360         //
1361 #if (HAL_BB_ENABLE == 1)
1362         status = PHY_BBConfig8723A(Adapter);
1363         if(status == _FAIL)
1364         {
1365                 DBG_8723A("PHY_BBConfig8723A fault !!\n");
1366                 goto exit;
1367         }
1368 #endif
1369
1370         //
1371         // 2011/11/15 MH Add for tx power by rate fine tune. We need to call the function after BB config.
1372         // Because the tx power by rate table is inited in BB config.
1373         //
1374 //      HAL_AdjustPwrIndexDiffRateOffset(Adapter);
1375 //      HAL_AdjustPwrIndexbyRegistry(Adapter);
1376
1377 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF);
1378 #if (HAL_RF_ENABLE == 1)
1379         status = PHY_RFConfig8723A(Adapter);
1380         if(status == _FAIL)
1381         {
1382                 DBG_8723A("PHY_RFConfig8723A fault !!\n");
1383                 goto exit;
1384         }
1385
1386         //reducing 80M spur
1387         PHY_SetBBReg(Adapter, RF_T_METER, bMaskDWord, 0x0381808d);
1388         PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff83);
1389         PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff82);
1390         PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff83);
1391
1392         //RFSW Control
1393         PHY_SetBBReg(Adapter, rFPGA0_TxInfo, bMaskDWord, 0x00000003);   //0x804[14]=0
1394         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFInterfaceSW, bMaskDWord, 0x07000760);        //0x870[6:5]=b'11
1395         PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, 0x66F60210); //0x860[6:5]=b'00
1396
1397         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("%s: 0x870 = value 0x%x\n", __FUNCTION__, PHY_QueryBBReg(Adapter, 0x870, bMaskDWord)));
1398
1399 #endif
1400
1401         //
1402         // Joseph Note: Keep RfRegChnlVal for later use.
1403         //
1404         pHalData->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, (RF_RADIO_PATH_E)0, RF_CHNLBW, bRFRegOffsetMask);
1405         pHalData->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, (RF_RADIO_PATH_E)1, RF_CHNLBW, bRFRegOffsetMask);
1406
1407
1408 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
1409         if (!pHalData->bMACFuncEnable) {
1410                 _InitQueueReservedPage(Adapter);
1411                 _InitTxBufferBoundary(Adapter);
1412         }
1413         _InitQueuePriority(Adapter);
1414         _InitPageBoundary(Adapter);
1415         _InitTransferPageSize(Adapter);
1416
1417         // Get Rx PHY status in order to report RSSI and others.
1418         _InitDriverInfoSize(Adapter, DRVINFO_SZ);
1419
1420         _InitInterrupt(Adapter);
1421         hal_init_macaddr(Adapter);//set mac_address
1422         _InitNetworkType(Adapter);//set msr
1423         _InitWMACSetting(Adapter);
1424         _InitAdaptiveCtrl(Adapter);
1425         _InitEDCA(Adapter);
1426         _InitRateFallback(Adapter);
1427         _InitRetryFunction(Adapter);
1428         InitUsbAggregationSetting(Adapter);
1429         _InitOperationMode(Adapter);//todo
1430         rtl8723a_InitBeaconParameters(Adapter);
1431         rtl8723a_InitBeaconMaxError(Adapter, _TRUE);
1432
1433 #ifdef RTL8192CU_ADHOC_WORKAROUND_SETTING
1434         _InitAdhocWorkaroundParams(Adapter);
1435 #endif
1436
1437 #if ENABLE_USB_DROP_INCORRECT_OUT
1438         _InitHardwareDropIncorrectBulkOut(Adapter);
1439 #endif
1440
1441 #if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_TX_MCAST2UNI)
1442         // Enable lifetime check for the four ACs
1443         rtw_write8(Adapter, REG_LIFETIME_EN, 0x0F);
1444 #ifdef CONFIG_TX_MCAST2UNI
1445         rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400);  // unit: 256us. 256ms
1446         rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400);  // unit: 256us. 256ms
1447 #else   // CONFIG_TX_MCAST2UNI
1448         rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x3000);  // unit: 256us. 3s
1449         rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x3000);  // unit: 256us. 3s
1450 #endif  // CONFIG_TX_MCAST2UNI
1451 #endif  // CONFIG_CONCURRENT_MODE || CONFIG_TX_MCAST2UNI
1452
1453
1454 #ifdef CONFIG_LED
1455         _InitHWLed(Adapter);
1456 #endif //CONFIG_LED
1457
1458 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK);
1459         _BBTurnOnBlock(Adapter);
1460         //NicIFSetMacAddress(padapter, padapter->PermanentAddress);
1461
1462 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY);
1463         invalidate_cam_all(Adapter);
1464
1465 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
1466         // 2010/12/17 MH We need to set TX power according to EFUSE content at first.
1467         PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
1468
1469         rtl8723a_InitAntenna_Selection(Adapter);
1470
1471         // HW SEQ CTRL
1472         //set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM.
1473         rtw_write8(Adapter,REG_HWSEQ_CTRL, 0xFF);
1474
1475         //
1476         // Disable BAR, suggested by Scott
1477         // 2010.04.09 add by hpfan
1478         //
1479         rtw_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff);
1480
1481         if(pregistrypriv->wifi_spec)
1482                 rtw_write16(Adapter,REG_FAST_EDCA_CTRL ,0);
1483
1484         // Move by Neo for USB SS from above setp
1485         _RfPowerSave(Adapter);
1486
1487         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK);
1488                 // 2010/08/26 MH Merge from 8192CE.
1489                 //sherry masked that it has been done in _RfPowerSave
1490                 //20110927
1491                 //recovery for 8192cu and 9723Au 20111017
1492                 if(pwrctrlpriv->rf_pwrstate == rf_on)
1493                 {
1494                         if(pHalData->bIQKInitialized ){
1495                                 rtl8192c_PHY_IQCalibrate(Adapter,_TRUE);
1496                         } else {
1497                                 rtl8192c_PHY_IQCalibrate(Adapter,_FALSE);
1498                                 pHalData->bIQKInitialized = _TRUE;
1499                         }
1500
1501         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK);
1502                         rtl8192c_odm_CheckTXPowerTracking(Adapter);
1503
1504         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
1505                         rtl8192c_PHY_LCCalibrate(Adapter);
1506
1507 #ifdef CONFIG_BT_COEXIST
1508                         rtl8723a_SingleDualAntennaDetection(Adapter);
1509 #endif
1510                 }
1511
1512
1513 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC21);
1514 #ifdef USB_INTERFERENCE_ISSUE
1515  //fixed USB interface interference issue
1516         rtw_write8(Adapter, 0xfe40, 0xe0);
1517         rtw_write8(Adapter, 0xfe41, 0x8d);
1518         rtw_write8(Adapter, 0xfe42, 0x80);
1519         rtw_write32(Adapter,0x20c,0xfd0320);
1520 #if 1
1521         //2011/01/07 ,suggest by Johnny,for solved the problem that too many protocol error on USB bus
1522         if(!IS_81xxC_VENDOR_UMC_A_CUT(pHalData->VersionID) )//&& !IS_92C_SERIAL(pHalData->VersionID))// TSMC , 8188
1523         {
1524                 // 0xE6=0x94
1525                 rtw_write8(Adapter, 0xFE40, 0xE6);
1526                 rtw_write8(Adapter, 0xFE41, 0x94);
1527                 rtw_write8(Adapter, 0xFE42, 0x80);
1528
1529                 // 0xE0=0x19
1530                 rtw_write8(Adapter, 0xFE40, 0xE0);
1531                 rtw_write8(Adapter, 0xFE41, 0x19);
1532                 rtw_write8(Adapter, 0xFE42, 0x80);
1533
1534                 // 0xE5=0x91
1535                 rtw_write8(Adapter, 0xFE40, 0xE5);
1536                 rtw_write8(Adapter, 0xFE41, 0x91);
1537                 rtw_write8(Adapter, 0xFE42, 0x80);
1538
1539                 // 0xE2=0x81
1540                 rtw_write8(Adapter, 0xFE40, 0xE2);
1541                 rtw_write8(Adapter, 0xFE41, 0x81);
1542                 rtw_write8(Adapter, 0xFE42, 0x80);
1543
1544         }
1545
1546 #endif
1547 #endif //USB_INTERFERENCE_ISSUE
1548
1549 //HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS);
1550 //      _InitPABias(Adapter);
1551
1552 #ifdef CONFIG_BT_COEXIST
1553 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BT_COEXIST);
1554         // Init BT hw config.
1555         BT_InitHwConfig(Adapter);
1556 #endif
1557
1558 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
1559         rtl8723a_InitHalDm(Adapter);
1560
1561 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC31);
1562         rtw_hal_set_hwreg(Adapter, HW_VAR_NAV_UPPER, (u8*)&NavUpper);
1563
1564         // 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test, but we need to fin root cause.
1565         if (((rtw_read32(Adapter, rFPGA0_RFMOD) & 0xFF000000) != 0x83000000)) {
1566                 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(24), 1);
1567                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("%s: IQK fail recorver\n", __FUNCTION__));
1568         }
1569
1570 #ifdef CONFIG_XMIT_ACK
1571         //ack for xmit mgmt frames.
1572         rtw_write32(Adapter, REG_FWHW_TXQ_CTRL, rtw_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12));
1573 #endif //CONFIG_XMIT_ACK
1574
1575         //_dbg_dump_macreg(padapter);
1576
1577 exit:
1578 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
1579
1580         DBG_8723A("%s in %dms\n", __FUNCTION__, rtw_get_passing_time_ms(init_start_time));
1581
1582         #ifdef DBG_HAL_INIT_PROFILING
1583         hal_init_stages_timestamp[HAL_INIT_STAGES_END]=rtw_get_current_time();
1584
1585         for(hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM-1;hal_init_profiling_i++) {
1586                 DBG_8723A("DBG_HAL_INIT_PROFILING: %35s, %u, %5u, %5u\n"
1587                         , hal_init_stages_str[hal_init_profiling_i]
1588                         , hal_init_stages_timestamp[hal_init_profiling_i]
1589                         , (hal_init_stages_timestamp[hal_init_profiling_i+1]-hal_init_stages_timestamp[hal_init_profiling_i])
1590                         , rtw_get_time_interval_ms(hal_init_stages_timestamp[hal_init_profiling_i], hal_init_stages_timestamp[hal_init_profiling_i+1])
1591                 );
1592         }
1593         #endif
1594
1595 _func_exit_;
1596
1597         return status;
1598 }
1599
1600
1601 #define SYNC_SD7_20110802_phy_SsPwrSwitch92CU
1602 #ifdef SYNC_SD7_20110802_phy_SsPwrSwitch92CU
1603 void
1604 phy_SsPwrSwitch92CU(
1605         PADAPTER                        Adapter,
1606         rt_rf_power_state       eRFPowerState,
1607         int bRegSSPwrLvl
1608         )
1609 {
1610         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
1611         u8                              value8;
1612
1613         switch( eRFPowerState )
1614         {
1615                 case rf_on:
1616                         if (bRegSSPwrLvl == 1)
1617                         {
1618                                 // 1. Enable MAC Clock. Can not be enabled now.
1619                                 //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) | BIT(3));
1620
1621                                 // 2. Force PWM, Enable SPS18_LDO_Marco_Block
1622                                 rtw_write8(Adapter, REG_SPS0_CTRL,
1623                                 rtw_read8(Adapter, REG_SPS0_CTRL) | (BIT0|BIT3));
1624
1625                                 // 3. restore BB, AFE control register.
1626                                 //RF
1627                                 if (pHalData->rf_type ==  RF_2T2R)
1628                                         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x380038, 1);
1629                                 else
1630                                         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 1);
1631                                 PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1);
1632                                 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1, 0);
1633
1634                                 //AFE
1635                                 //DbgPrint("0x0e70 = %x\n", Adapter->PS_BBRegBackup[PSBBREG_AFE0]);
1636                                 //PHY_SetBBReg(Adapter, 0x0e70, bMaskDWord ,Adapter->PS_BBRegBackup[PSBBREG_AFE0] );
1637                                 //PHY_SetBBReg(Adapter, 0x0e70, bMaskDWord ,0x631B25A0 );
1638                                 if (pHalData->rf_type ==  RF_2T2R)
1639                                         PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x63DB25A0 );
1640                                 else if (pHalData->rf_type ==  RF_1T1R)
1641                                         PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x631B25A0 );
1642
1643                                 // 4. issue 3-wire command that RF set to Rx idle mode. This is used to re-write the RX idle mode.
1644                                 // We can only prvide a usual value instead and then HW will modify the value by itself.
1645                                 PHY_SetRFReg(Adapter,RF_PATH_A, 0, bRFRegOffsetMask,0x32D95);
1646                                 if (pHalData->rf_type ==  RF_2T2R)
1647                                 {
1648                                         PHY_SetRFReg(Adapter,RF_PATH_B, 0, bRFRegOffsetMask,0x32D95);
1649                                 }
1650                         }
1651                         else            // Level 2 or others.
1652                         {
1653                                 //h.    AFE_PLL_CTRL 0x28[7:0] = 0x80                   //disable AFE PLL
1654                                 rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x81);
1655
1656                                 // i.   AFE_XTAL_CTRL 0x24[15:0] = 0x880F               //gated AFE DIG_CLOCK
1657                                 rtw_write16(Adapter, REG_AFE_XTAL_CTRL, 0x800F);
1658                                 rtw_mdelay_os(1);
1659
1660                                 // 1. Enable MAC Clock. Can not be enabled now.
1661                                 //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) | BIT(3));
1662
1663                                 // 2. Force PWM, Enable SPS18_LDO_Marco_Block
1664                                 rtw_write8(Adapter, REG_SPS0_CTRL,
1665                                 rtw_read8(Adapter, REG_SPS0_CTRL) | (BIT0|BIT3));
1666
1667                                 // 3. restore BB, AFE control register.
1668                                 //RF
1669                                 if (pHalData->rf_type ==  RF_2T2R)
1670                                         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x380038, 1);
1671                                 else
1672                                         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 1);
1673                                 PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1);
1674                                 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1, 0);
1675
1676                                 //AFE
1677                                 if (pHalData->rf_type ==  RF_2T2R)
1678                                         PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x63DB25A0 );
1679                                 else if (pHalData->rf_type ==  RF_1T1R)
1680                                         PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x631B25A0 );
1681
1682                                 // 4. issue 3-wire command that RF set to Rx idle mode. This is used to re-write the RX idle mode.
1683                                 // We can only prvide a usual value instead and then HW will modify the value by itself.
1684                                 PHY_SetRFReg(Adapter,RF_PATH_A, 0, bRFRegOffsetMask,0x32D95);
1685                                 if (pHalData->rf_type ==  RF_2T2R)
1686                                 {
1687                                         PHY_SetRFReg(Adapter,RF_PATH_B, 0, bRFRegOffsetMask,0x32D95);
1688                                 }
1689
1690                                 // 5. gated MAC Clock
1691                                 //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) & ~(BIT(3)));
1692                                 //rtw_write8(Adapter, REG_SYS_CLKR+1, rtw_read8(Adapter, REG_SYS_CLKR+1)|(BIT3));
1693
1694                                 {
1695                                         //u8                    eRFPath = RF_PATH_A,value8 = 0, retry = 0;
1696                                         u8              bytetmp;
1697                                         //PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x0, bMaskByte0, 0x0);
1698                                         // 2010/08/12 MH Add for B path under SS test.
1699                                         //if (pHalData->RF_Type ==  RF_2T2R)
1700                                                 //PHY_SetRFReg(Adapter, RF_PATH_B, 0x0, bMaskByte0, 0x0);
1701
1702                                         bytetmp = rtw_read8(Adapter, REG_APSD_CTRL);
1703                                         rtw_write8(Adapter, REG_APSD_CTRL, bytetmp & ~BIT6);
1704
1705                                         rtw_mdelay_os(10);
1706
1707                                         // Set BB reset at first
1708                                         rtw_write8(Adapter, REG_SYS_FUNC_EN, 0x17 );//0x16
1709
1710                                         // Enable TX
1711                                         rtw_write8(Adapter, REG_TXPAUSE, 0x0);
1712                                 }
1713                                 //CardSelectiveSuspendLeave(Adapter);
1714                         }
1715
1716                         break;
1717
1718                 case rf_sleep:
1719                 case rf_off:
1720                                 value8 = rtw_read8(Adapter, REG_SPS0_CTRL) ;
1721                                 if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID))
1722                                         value8 &= ~(BIT0);
1723                                 else
1724                                         value8 &= ~(BIT0|BIT3);
1725                                 if (bRegSSPwrLvl == 1)
1726                                 {
1727                                         RT_TRACE(_module_hal_init_c_, _drv_err_, ("SS LVL1\n"));
1728                                         // Disable RF and BB only for SelectSuspend.
1729
1730                                         // 1. Set BB/RF to shutdown.
1731                                         //      (1) Reg878[5:3]= 0      // RF rx_code for preamble power saving
1732                                         //      (2)Reg878[21:19]= 0     //Turn off RF-B
1733                                         //      (3) RegC04[7:4]= 0      // turn off all paths for packet detection
1734                                         //      (4) Reg800[1] = 1               // enable preamble power saving
1735                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] = PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter, bMaskDWord);
1736                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] = PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskDWord);
1737                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] = PHY_QueryBBReg(Adapter, rFPGA0_RFMOD, bMaskDWord);
1738                                         if (pHalData->rf_type ==  RF_2T2R)
1739                                         {
1740                                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x380038, 0);
1741                                         }
1742                                         else if (pHalData->rf_type ==  RF_1T1R)
1743                                         {
1744                                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 0);
1745                                         }
1746                                         PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0);
1747                                         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1,1);
1748
1749                                         // 2 .AFE control register to power down. bit[30:22]
1750                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] = PHY_QueryBBReg(Adapter, rRx_Wait_CCA, bMaskDWord);
1751                                         if (pHalData->rf_type ==  RF_2T2R)
1752                                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x00DB25A0);
1753                                         else if (pHalData->rf_type ==  RF_1T1R)
1754                                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x001B25A0);
1755
1756                                         // 3. issue 3-wire command that RF set to power down.
1757                                         PHY_SetRFReg(Adapter,RF_PATH_A, 0, bRFRegOffsetMask,0);
1758                                         if (pHalData->rf_type ==  RF_2T2R)
1759                                         {
1760                                                 PHY_SetRFReg(Adapter,RF_PATH_B, 0, bRFRegOffsetMask,0);
1761                                         }
1762
1763                                         // 4. Force PFM , disable SPS18_LDO_Marco_Block
1764                                         rtw_write8(Adapter, REG_SPS0_CTRL, value8);
1765
1766                                         // 5. gated MAC Clock
1767                                         //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) & ~(BIT(3)));
1768                                 }
1769                                 else    // Level 2 or others.
1770                                 {
1771                                         RT_TRACE(_module_hal_init_c_, _drv_err_, ("SS LVL2\n"));
1772                                         {
1773                                                 u8                      eRFPath = RF_PATH_A,value8 = 0;
1774                                                 rtw_write8(Adapter, REG_TXPAUSE, 0xFF);
1775                                                 PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x0, bMaskByte0, 0x0);
1776                                                 // 2010/08/12 MH Add for B path under SS test.
1777                                                 //if (pHalData->RF_Type ==  RF_2T2R)
1778                                                         //PHY_SetRFReg(Adapter, RF_PATH_B, 0x0, bMaskByte0, 0x0);
1779
1780                                                 value8 |= APSDOFF;
1781                                                 rtw_write8(Adapter, REG_APSD_CTRL, value8);//0x40
1782
1783                                                 // After switch APSD, we need to delay for stability
1784                                                 rtw_mdelay_os(10);
1785
1786                                                 // Set BB reset at first
1787                                                 value8 = 0 ;
1788                                                 value8 |=( FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
1789                                                 rtw_write8(Adapter, REG_SYS_FUNC_EN,value8 );//0x16
1790                                         }
1791
1792                                         // Disable RF and BB only for SelectSuspend.
1793
1794                                         // 1. Set BB/RF to shutdown.
1795                                         //      (1) Reg878[5:3]= 0      // RF rx_code for preamble power saving
1796                                         //      (2)Reg878[21:19]= 0     //Turn off RF-B
1797                                         //      (3) RegC04[7:4]= 0      // turn off all paths for packet detection
1798                                         //      (4) Reg800[1] = 1               // enable preamble power saving
1799                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] = PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter, bMaskDWord);
1800                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] = PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskDWord);
1801                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] = PHY_QueryBBReg(Adapter, rFPGA0_RFMOD, bMaskDWord);
1802                                         if (pHalData->rf_type ==  RF_2T2R)
1803                                         {
1804                                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x380038, 0);
1805                                         }
1806                                         else if (pHalData->rf_type ==  RF_1T1R)
1807                                         {
1808                                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 0);
1809                                         }
1810                                         PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0);
1811                                         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1,1);
1812
1813                                         // 2 .AFE control register to power down. bit[30:22]
1814                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] = PHY_QueryBBReg(Adapter, rRx_Wait_CCA, bMaskDWord);
1815                                         if (pHalData->rf_type ==  RF_2T2R)
1816                                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x00DB25A0);
1817                                         else if (pHalData->rf_type ==  RF_1T1R)
1818                                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x001B25A0);
1819
1820                                         // 3. issue 3-wire command that RF set to power down.
1821                                         PHY_SetRFReg(Adapter,RF_PATH_A, 0, bRFRegOffsetMask,0);
1822                                         if (pHalData->rf_type ==  RF_2T2R)
1823                                         {
1824                                                 PHY_SetRFReg(Adapter,RF_PATH_B, 0, bRFRegOffsetMask,0);
1825                                         }
1826
1827                                         // 4. Force PFM , disable SPS18_LDO_Marco_Block
1828                                         rtw_write8(Adapter, REG_SPS0_CTRL, value8);
1829
1830                                         // 2010/10/13 MH/Isaachsu exchange sequence.
1831                                         //h.    AFE_PLL_CTRL 0x28[7:0] = 0x80                   //disable AFE PLL
1832                                         rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x80);
1833                                         rtw_mdelay_os(1);
1834
1835                                         // i.   AFE_XTAL_CTRL 0x24[15:0] = 0x880F               //gated AFE DIG_CLOCK
1836                                         rtw_write16(Adapter, REG_AFE_XTAL_CTRL, 0xA80F);
1837
1838                                         // 5. gated MAC Clock
1839                                         //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) & ~(BIT(3)));
1840                                         //rtw_write8(Adapter, REG_SYS_CLKR+1, rtw_read8(Adapter, REG_SYS_CLKR+1)& ~(BIT3))
1841
1842                                         //CardSelectiveSuspendEnter(Adapter);
1843                                 }
1844
1845                         break;
1846
1847                 default:
1848                         break;
1849         }
1850
1851 }       // phy_PowerSwitch92CU
1852
1853 void _ps_open_RF(_adapter *padapter) {
1854         //here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified
1855         phy_SsPwrSwitch92CU(padapter, rf_on, 1);
1856 }
1857
1858 void _ps_close_RF(_adapter *padapter){
1859         //here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified
1860         phy_SsPwrSwitch92CU(padapter, rf_off, 1);
1861 }
1862 #endif //SYNC_SD7_20110802_phy_SsPwrSwitch92CU
1863
1864
1865
1866 static void
1867 _DisableGPIO(
1868         PADAPTER        Adapter
1869         )
1870 {
1871 /***************************************
1872 j. GPIO_PIN_CTRL 0x44[31:0]=0x000               //
1873 k. Value = GPIO_PIN_CTRL[7:0]
1874 l.  GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); //write external PIN level
1875 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
1876 n. LEDCFG 0x4C[15:0] = 0x8080
1877 ***************************************/
1878         u8      value8;
1879         u16     value16;
1880         u32     value32;
1881
1882         //1. Disable GPIO[7:0]
1883         rtw_write16(Adapter, REG_GPIO_PIN_CTRL+2, 0x0000);
1884         value32 = rtw_read32(Adapter, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1885         value8 = (u8) (value32&0x000000FF);
1886         value32 |= ((value8<<8) | 0x00FF0000);
1887         rtw_write32(Adapter, REG_GPIO_PIN_CTRL, value32);
1888
1889         //2. Disable GPIO[10:8]
1890         rtw_write8(Adapter, REG_GPIO_MUXCFG+3, 0x00);
1891             value16 = rtw_read16(Adapter, REG_GPIO_MUXCFG+2) & 0xFF0F;
1892         value8 = (u8) (value16&0x000F);
1893         value16 |= ((value8<<4) | 0x0780);
1894         rtw_write16(Adapter, REG_GPIO_MUXCFG+2, value16);
1895
1896         //3. Disable LED0 & 1
1897         rtw_write16(Adapter, REG_LEDCFG0, 0x8080);
1898
1899         //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Disable GPIO and LED.\n"));
1900
1901 } //end of _DisableGPIO()
1902
1903 static void
1904 _ResetFWDownloadRegister(
1905  PADAPTER                       Adapter
1906         )
1907 {
1908         u32     value32;
1909
1910         value32 = rtw_read32(Adapter, REG_MCUFWDL);
1911         value32 &= ~(MCUFWDL_EN | MCUFWDL_RDY);
1912         rtw_write32(Adapter, REG_MCUFWDL, value32);
1913         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset FW download register.\n"));
1914 }
1915
1916
1917 static int
1918 _DisableRF_AFE(
1919  PADAPTER                       Adapter
1920         )
1921 {
1922         int             rtStatus = _SUCCESS;
1923         u32                     pollingCount = 0;
1924         u8                      value8;
1925
1926         //disable RF/ AFE AD/DA
1927         value8 = APSDOFF;
1928         rtw_write8(Adapter, REG_APSD_CTRL, value8);
1929
1930
1931 #if (RTL8192CU_ASIC_VERIFICATION)
1932
1933         do
1934         {
1935                 if(rtw_read8(Adapter, REG_APSD_CTRL) & APSDOFF_STATUS){
1936                         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Disable RF, AFE, AD, DA Done!\n"));
1937                         break;
1938                 }
1939
1940                 if(pollingCount++ > POLLING_READY_TIMEOUT_COUNT){
1941                         //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("Failed to polling APSDOFF_STATUS done!\n"));
1942                         return _FAIL;
1943                 }
1944
1945         }while(_TRUE);
1946
1947 #endif
1948
1949         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Disable RF, AFE,AD, DA.\n"));
1950         return rtStatus;
1951
1952 }
1953
1954 static void
1955 _ResetBB(
1956  PADAPTER                       Adapter
1957         )
1958 {
1959         u16     value16;
1960
1961         //reset BB
1962         value16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
1963         value16 &= ~(FEN_BBRSTB | FEN_BB_GLB_RSTn);
1964         rtw_write16(Adapter, REG_SYS_FUNC_EN, value16);
1965         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset BB.\n"));
1966 }
1967
1968 static void
1969 _ResetMCU(
1970  PADAPTER                       Adapter
1971         )
1972 {
1973         u16     value16;
1974
1975         // reset MCU
1976         value16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
1977         value16 &= ~FEN_CPUEN;
1978         rtw_write16(Adapter, REG_SYS_FUNC_EN, value16);
1979         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset MCU.\n"));
1980 }
1981
1982 static void
1983 _DisableMAC_AFE_PLL(
1984  PADAPTER                       Adapter
1985         )
1986 {
1987         u32     value32;
1988
1989         //disable MAC/ AFE PLL
1990         value32 = rtw_read32(Adapter, REG_APS_FSMCO);
1991         value32 |= APDM_MAC;
1992         rtw_write32(Adapter, REG_APS_FSMCO, value32);
1993
1994         value32 |= APFM_OFF;
1995         rtw_write32(Adapter, REG_APS_FSMCO, value32);
1996         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Disable MAC, AFE PLL.\n"));
1997 }
1998
1999 static void
2000 _AutoPowerDownToHostOff(
2001         PADAPTER                Adapter
2002         )
2003 {
2004         u32                     value32;
2005         rtw_write8(Adapter, REG_SPS0_CTRL, 0x22);
2006
2007         value32 = rtw_read32(Adapter, REG_APS_FSMCO);
2008
2009         value32 |= APDM_HOST;//card disable
2010         rtw_write32(Adapter, REG_APS_FSMCO, value32);
2011         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Auto Power Down to Host-off state.\n"));
2012
2013         // set USB suspend
2014         value32 = rtw_read32(Adapter, REG_APS_FSMCO);
2015         value32 &= ~AFSM_PCIE;
2016         rtw_write32(Adapter, REG_APS_FSMCO, value32);
2017
2018 }
2019
2020 static void
2021 _SetUsbSuspend(
2022  PADAPTER                       Adapter
2023         )
2024 {
2025         u32                     value32;
2026
2027         value32 = rtw_read32(Adapter, REG_APS_FSMCO);
2028
2029         // set USB suspend
2030         value32 |= AFSM_HSUS;
2031         rtw_write32(Adapter, REG_APS_FSMCO, value32);
2032
2033         //RT_ASSERT(0 == (rtw_read32(Adapter, REG_APS_FSMCO) & BIT(12)),(""));
2034         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Set USB suspend.\n"));
2035
2036 }
2037
2038 static void
2039 _DisableRFAFEAndResetBB(
2040  PADAPTER                       Adapter
2041         )
2042 {
2043 /**************************************
2044 a.      TXPAUSE 0x522[7:0] = 0xFF             //Pause MAC TX queue
2045 b.      RF path 0 offset 0x00 = 0x00            // disable RF
2046 c.      APSD_CTRL 0x600[7:0] = 0x40
2047 d.      SYS_FUNC_EN 0x02[7:0] = 0x16            //reset BB state machine
2048 e.      SYS_FUNC_EN 0x02[7:0] = 0x14            //reset BB state machine
2049 ***************************************/
2050         u8 eRFPath = 0,value8 = 0;
2051         rtw_write8(Adapter, REG_TXPAUSE, 0xFF);
2052         PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x0, bMaskByte0, 0x0);
2053
2054         value8 |= APSDOFF;
2055         rtw_write8(Adapter, REG_APSD_CTRL, value8);//0x40
2056
2057         value8 = 0 ;
2058         value8 |=( FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
2059         rtw_write8(Adapter, REG_SYS_FUNC_EN,value8 );//0x16
2060
2061         value8 &=( ~FEN_BB_GLB_RSTn );
2062         rtw_write8(Adapter, REG_SYS_FUNC_EN, value8); //0x14
2063
2064         //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> RF off and reset BB.\n"));
2065 }
2066
2067 static void
2068 _ResetDigitalProcedure1(
2069         PADAPTER                        Adapter,
2070         bool                            bWithoutHWSM
2071         )
2072 {
2073
2074         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2075
2076         if(pHalData->FirmwareVersion <=  0x20){
2077                 /*****************************
2078                 f.      MCUFWDL 0x80[7:0]=0                             // reset MCU ready status
2079                 g.      SYS_FUNC_EN 0x02[10]= 0                 // reset MCU register, (8051 reset)
2080                 h.      SYS_FUNC_EN 0x02[15-12]= 5              // reset MAC register, DCORE
2081                 i.     SYS_FUNC_EN 0x02[10]= 1                  // enable MCU register, (8051 enable)
2082                 ******************************/
2083                         u16 valu16 = 0;
2084                         rtw_write8(Adapter, REG_MCUFWDL, 0);
2085
2086                         valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
2087                         rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 & (~FEN_CPUEN)));//reset MCU ,8051
2088
2089                         valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN)&0x0FFF;
2090                         rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 |(FEN_HWPDN|FEN_ELDR)));//reset MAC
2091
2092                         #ifdef DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE
2093                         {
2094                                 u8 val;
2095                                 if( (val=rtw_read8(Adapter, REG_MCUFWDL)))
2096                                         DBG_8723A("DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE %s:%d REG_MCUFWDL:0x%02x\n", __FUNCTION__, __LINE__, val);
2097                         }
2098                         #endif
2099
2100
2101                         valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
2102                         rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 | FEN_CPUEN));//enable MCU ,8051
2103         } else{
2104                 u8 retry_cnts = 0;
2105
2106                 if(rtw_read8(Adapter, REG_MCUFWDL) & BIT1)
2107                 { //IF fw in RAM code, do reset
2108
2109                         rtw_write8(Adapter, REG_MCUFWDL, 0);
2110                         if(Adapter->bFWReady){
2111                                 // 2010/08/25 MH Accordign to RD alfred's suggestion, we need to disable other
2112                                 // HRCV INT to influence 8051 reset.
2113                                 rtw_write8(Adapter, REG_FWIMR, 0x20);
2114
2115                                 rtw_write8(Adapter, REG_HMETFR+3, 0x20);//8051 reset by self
2116
2117                                 while( (retry_cnts++ <100) && (FEN_CPUEN &rtw_read16(Adapter, REG_SYS_FUNC_EN)))
2118                                 {
2119                                         rtw_udelay_os(50);//PlatformStallExecution(50);//us
2120                                 }
2121
2122                                 if(retry_cnts >= 100){
2123                                         DBG_8723A("%s #####=> 8051 reset failed!.........................\n", __FUNCTION__);
2124                                         // if 8051 reset fail we trigger GPIO 0 for LA
2125                                         //PlatformEFIOWrite4Byte(       Adapter,
2126                                         //                                              REG_GPIO_PIN_CTRL,
2127                                         //                                              0x00010100);
2128                                         // 2010/08/31 MH According to Filen's info, if 8051 reset fail, reset MAC directly.
2129                                         rtw_write8(Adapter, REG_SYS_FUNC_EN+1, 0x50);   //Reset MAC and Enable 8051
2130                                         rtw_mdelay_os(10);
2131                                 }
2132                                 else {
2133                                         //DBG_8723A("%s =====> 8051 reset success (%d) .\n", __FUNCTION__, retry_cnts);
2134                                 }
2135                         }
2136                         else {
2137                                 DBG_8723A("%s =====> 8051 in RAM but !Adapter->bFWReady\n", __FUNCTION__);
2138                         }
2139                 }
2140                 else{
2141                         //DBG_8723A("%s =====> 8051 in ROM.\n", __FUNCTION__);
2142                 }
2143
2144                 #ifdef DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE
2145                 {
2146                         u8 val;
2147                         if( (val=rtw_read8(Adapter, REG_MCUFWDL)))
2148                                 DBG_8723A("DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE %s:%d REG_MCUFWDL:0x%02x\n", __FUNCTION__, __LINE__, val);
2149                 }
2150                 #endif
2151
2152                 rtw_write8(Adapter, REG_SYS_FUNC_EN+1, 0x54);   //Reset MAC and Enable 8051
2153         }
2154
2155         // Clear rpwm value for initial toggle bit trigger.
2156         rtw_write8(Adapter, REG_USB_HRPWM, 0x00);
2157
2158         if(bWithoutHWSM){
2159         /*****************************
2160                 Without HW auto state machine
2161         g.      SYS_CLKR 0x08[15:0] = 0x30A3                    //disable MAC clock
2162         h.      AFE_PLL_CTRL 0x28[7:0] = 0x80                   //disable AFE PLL
2163         i.      AFE_XTAL_CTRL 0x24[15:0] = 0x880F               //gated AFE DIG_CLOCK
2164         j.      SYS_ISO_CTRL 0x00[7:0] = 0xF9                   // isolated digital to PON
2165         ******************************/
2166                 //rtw_write16(Adapter, REG_SYS_CLKR, 0x30A3);
2167                 rtw_write16(Adapter, REG_SYS_CLKR, 0x70A3);//modify to 0x70A3 by Scott.
2168                 rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x80);
2169                 rtw_write16(Adapter, REG_AFE_XTAL_CTRL, 0x880F);
2170                 rtw_write8(Adapter, REG_SYS_ISO_CTRL, 0xF9);
2171         }
2172         else
2173         {
2174                 // Disable all RF/BB power
2175                 rtw_write8(Adapter, REG_RF_CTRL, 0x00);
2176         }
2177         //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Reset Digital.\n"));
2178
2179 }
2180
2181 static void
2182 _ResetDigitalProcedure2(
2183         PADAPTER                        Adapter
2184 )
2185 {
2186 /*****************************
2187 k.      SYS_FUNC_EN 0x03[7:0] = 0x44                    // disable ELDR runction
2188 l.      SYS_CLKR 0x08[15:0] = 0x3083                    // disable ELDR clock
2189 m.      SYS_ISO_CTRL 0x01[7:0] = 0x83                   // isolated ELDR to PON
2190 ******************************/
2191         //rtw_write8(Adapter, REG_SYS_FUNC_EN+1, 0x44);//marked by Scott.
2192         //rtw_write16(Adapter, REG_SYS_CLKR, 0x3083);
2193         //rtw_write8(Adapter, REG_SYS_ISO_CTRL+1, 0x83);
2194
2195         rtw_write16(Adapter, REG_SYS_CLKR, 0x70a3); //modify to 0x70a3 by Scott.
2196         rtw_write8(Adapter, REG_SYS_ISO_CTRL+1, 0x82); //modify to 0x82 by Scott.
2197 }
2198
2199 static void
2200 _DisableAnalog(
2201  PADAPTER                       Adapter,
2202  bool                   bWithoutHWSM
2203         )
2204 {
2205         u16 value16 = 0;
2206         u8 value8=0;
2207         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2208
2209         if(bWithoutHWSM){
2210         /*****************************
2211         n.      LDOA15_CTRL 0x20[7:0] = 0x04            // disable A15 power
2212         o.      LDOV12D_CTRL 0x21[7:0] = 0x54           // disable digital core power
2213         r.      When driver call disable, the ASIC will turn off remaining clock automatically
2214         ******************************/
2215
2216                 rtw_write8(Adapter, REG_LDOA15_CTRL, 0x04);
2217                 //PlatformIOWrite1Byte(Adapter, REG_LDOV12D_CTRL, 0x54);
2218
2219                 value8 = rtw_read8(Adapter, REG_LDOV12D_CTRL);
2220                 value8 &= (~LDV12_EN);
2221                 rtw_write8(Adapter, REG_LDOV12D_CTRL, value8);
2222                 //RT_TRACE(COMP_INIT, DBG_LOUD, (" REG_LDOV12D_CTRL Reg0x21:0x%02x.\n",value8));
2223         }
2224
2225 /*****************************
2226 h.      SPS0_CTRL 0x11[7:0] = 0x23                      //enter PFM mode
2227 i.      APS_FSMCO 0x04[15:0] = 0x4802           // set USB suspend
2228 ******************************/
2229
2230
2231         value8 = 0x23;
2232         if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID))
2233                 value8 |= BIT3;
2234
2235         rtw_write8(Adapter, REG_SPS0_CTRL, value8);
2236
2237
2238         if(bWithoutHWSM)
2239         {
2240                 //value16 |= (APDM_HOST | /*AFSM_HSUS |*/PFM_ALDN);
2241                 // 2010/08/31 According to Filen description, we need to use HW to shut down 8051 automatically.
2242                 // Becasue suspend operatione need the asistance of 8051 to wait for 3ms.
2243                 value16 |= (APDM_HOST | AFSM_HSUS |PFM_ALDN);
2244         }
2245         else
2246         {
2247                 value16 |= (APDM_HOST | AFSM_HSUS |PFM_ALDN);
2248         }
2249
2250         rtw_write16(Adapter, REG_APS_FSMCO,value16 );//0x4802
2251
2252         rtw_write8(Adapter, REG_RSV_CTRL, 0x0e);
2253 }
2254
2255 static void rtl8723au_hw_power_down(_adapter *padapter)
2256 {
2257         u8      u1bTmp;
2258
2259         DBG_8723A("PowerDownRTL8723U\n");
2260
2261
2262         // 1. Run Card Disable Flow
2263         // Done before this function call.
2264
2265         // 2. 0x04[16] = 0                      // reset WLON
2266         u1bTmp = rtw_read8(padapter, REG_APS_FSMCO+2);
2267         rtw_write8(padapter, REG_APS_FSMCO+2, (u1bTmp&(~BIT0)));
2268
2269         // 3. 0x04[12:11] = 2b'11 // enable suspend
2270         // Done before this function call.
2271
2272         // 4. 0x04[15] = 1                      // enable PDN
2273         u1bTmp = rtw_read8(padapter, REG_APS_FSMCO+1);
2274         rtw_write8(padapter, REG_APS_FSMCO+1, (u1bTmp|BIT7));
2275 }
2276
2277 //
2278 // Description: RTL8723e card disable power sequence v003 which suggested by Scott.
2279 // First created by tynli. 2011.01.28.
2280 //
2281 void
2282 CardDisableRTL8723U(
2283         PADAPTER                        Adapter
2284 )
2285 {
2286         u8              u1bTmp;
2287 //      PMGNT_INFO      pMgntInfo       = &(Adapter->MgntInfo);
2288
2289         DBG_8723A("CardDisableRTL8723U\n");
2290
2291         // USB-MF Card Disable Flow
2292         // 1. Run LPS WL RFOFF flow
2293         HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, rtl8723A_enter_lps_flow);
2294
2295         // 2. 0x1F[7:0] = 0             // turn off RF
2296         rtw_write8(Adapter, REG_RF_CTRL, 0x00);
2297
2298         //      ==== Reset digital sequence   ======
2299         if((rtw_read8(Adapter, REG_MCUFWDL)&BIT7) &&
2300                 Adapter->bFWReady) //8051 RAM code
2301         {
2302                 rtl8723a_FirmwareSelfReset(Adapter);
2303         }
2304
2305         // Reset MCU. Suggested by Filen. 2011.01.26. by tynli.
2306         u1bTmp = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
2307         rtw_write8(Adapter, REG_SYS_FUNC_EN+1, (u1bTmp&(~BIT2)));
2308
2309         // g.   MCUFWDL 0x80[1:0]=0                             // reset MCU ready status
2310         rtw_write8(Adapter, REG_MCUFWDL, 0x00);
2311
2312         //      ==== Reset digital sequence end ======
2313 //      if((pMgntInfo->RfOffReason & RF_CHANGE_BY_HW) )
2314         {
2315                 // Card disable power action flow
2316                 HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, rtl8723A_card_disable_flow);
2317         }
2318
2319         // Reset MCU IO Wrapper, added by Roger, 2011.08.30.
2320         u1bTmp = rtw_read8(Adapter, REG_RSV_CTRL+1);
2321         rtw_write8(Adapter, REG_RSV_CTRL+1, (u1bTmp&(~BIT0)));
2322         u1bTmp = rtw_read8(Adapter, REG_RSV_CTRL+1);
2323         rtw_write8(Adapter, REG_RSV_CTRL+1, u1bTmp|BIT0);
2324
2325         // 7. RSV_CTRL 0x1C[7:0] = 0x0E                 // lock ISO/CLK/Power control register
2326         rtw_write8(Adapter, REG_RSV_CTRL, 0x0e);
2327
2328 }
2329
2330
2331 u32 rtl8723au_hal_deinit(PADAPTER padapter)
2332 {
2333         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(padapter);
2334
2335
2336         DBG_8723A("==> %s\n", __FUNCTION__);
2337
2338 #ifdef CONFIG_BT_COEXIST
2339         BT_HaltProcess(padapter);
2340 #endif
2341         // 2011/02/18 To Fix RU LNA  power leakage problem. We need to execute below below in
2342         // Adapter init and halt sequence. Accordingto EEchou's opinion, we can enable the ability for all
2343         // IC. Accord to johnny's opinion, only RU need the support.
2344         CardDisableRTL8723U(padapter);
2345
2346         return _SUCCESS;
2347 }
2348
2349
2350 unsigned int rtl8723au_inirp_init(PADAPTER Adapter)
2351 {
2352         u8 i;
2353         struct recv_buf *precvbuf;
2354         uint    status;
2355         struct dvobj_priv *pdev= adapter_to_dvobj(Adapter);
2356         struct intf_hdl * pintfhdl=&Adapter->iopriv.intf;
2357         struct recv_priv *precvpriv = &(Adapter->recvpriv);
2358         u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
2359 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2360         u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
2361         HAL_DATA_TYPE   *pHalData=GET_HAL_DATA(Adapter);
2362 #endif //CONFIG_USB_INTERRUPT_IN_PIPE
2363
2364 _func_enter_;
2365
2366         _read_port = pintfhdl->io_ops._read_port;
2367
2368         status = _SUCCESS;
2369
2370         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("===> usb_inirp_init \n"));
2371
2372         precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR;
2373
2374         //issue Rx irp to receive data
2375         precvbuf = (struct recv_buf *)precvpriv->precv_buf;
2376         for(i=0; i<NR_RECVBUFF; i++)
2377         {
2378                 if(_read_port(pintfhdl, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf) == _FALSE )
2379                 {
2380                         RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_port error \n"));
2381                         status = _FAIL;
2382                         goto exit;
2383                 }
2384
2385                 precvbuf++;
2386                 precvpriv->free_recv_buf_queue_cnt--;
2387         }
2388
2389 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2390         _read_interrupt = pintfhdl->io_ops._read_interrupt;
2391         if(_read_interrupt(pintfhdl, RECV_INT_IN_ADDR) == _FALSE )
2392         {
2393                 RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_interrupt error \n"));
2394                 status = _FAIL;
2395         }
2396         pHalData->IntrMask[0]=rtw_read32(Adapter, REG_USB_HIMR);
2397         MSG_8723A("pHalData->IntrMask = 0x%04x\n", pHalData->IntrMask[0]);
2398         pHalData->IntrMask[0]|=UHIMR_C2HCMD|UHIMR_CPWM;
2399         rtw_write32(Adapter, REG_USB_HIMR,pHalData->IntrMask[0]);
2400 #endif //CONFIG_USB_INTERRUPT_IN_PIPE
2401
2402 exit:
2403
2404         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("<=== usb_inirp_init \n"));
2405
2406 _func_exit_;
2407
2408         return status;
2409
2410 }
2411
2412 unsigned int rtl8723au_inirp_deinit(PADAPTER Adapter)
2413 {
2414 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2415         u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
2416         HAL_DATA_TYPE   *pHalData=GET_HAL_DATA(Adapter);
2417 #endif //CONFIG_USB_INTERRUPT_IN_PIPE
2418         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("\n ===> usb_rx_deinit \n"));
2419
2420         rtw_read_port_cancel(Adapter);
2421 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2422         pHalData->IntrMask[0]=rtw_read32(Adapter, REG_USB_HIMR);
2423         MSG_8723A("%s pHalData->IntrMask = 0x%04x\n",__FUNCTION__, pHalData->IntrMask[0]);
2424         pHalData->IntrMask[0]=0x0;
2425         rtw_write32(Adapter, REG_USB_HIMR,pHalData->IntrMask[0]);
2426         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("\n <=== usb_rx_deinit \n"));
2427 #endif //CONFIG_USB_INTERRUPT_IN_PIPE
2428         return _SUCCESS;
2429 }
2430
2431
2432 static u32
2433 _GetChannelGroup(
2434         u32     channel
2435         )
2436 {
2437         //RT_ASSERT((channel < 14), ("Channel %d no is supported!\n"));
2438
2439         if(channel < 3){        // Channel 1~3
2440                 return 0;
2441         }
2442         else if(channel < 9){ // Channel 4~9
2443                 return 1;
2444         }
2445
2446         return 2;                               // Channel 10~14
2447 }
2448
2449
2450 //-------------------------------------------------------------------
2451 //
2452 //      EEPROM/EFUSE Content Parsing
2453 //
2454 //-------------------------------------------------------------------
2455 static void
2456 _ReadIDs(
2457         PADAPTER        Adapter,
2458         u8*             PROMContent,
2459         bool            AutoloadFail
2460         )
2461 {
2462         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2463
2464         if(_FALSE == AutoloadFail){
2465                 // VID, PID
2466                 pHalData->EEPROMVID = le16_to_cpu( *(u16 *)&PROMContent[EEPROM_VID]);
2467                 pHalData->EEPROMPID = le16_to_cpu( *(u16 *)&PROMContent[EEPROM_PID]);
2468
2469                 // Customer ID, 0x00 and 0xff are reserved for Realtek.
2470                 pHalData->EEPROMCustomerID = *(u8 *)&PROMContent[EEPROM_CUSTOMER_ID];
2471                 pHalData->EEPROMSubCustomerID = *(u8 *)&PROMContent[EEPROM_SUBCUSTOMER_ID];
2472
2473         }
2474         else{
2475                 pHalData->EEPROMVID      = EEPROM_Default_VID;
2476                 pHalData->EEPROMPID      = EEPROM_Default_PID;
2477
2478                 // Customer ID, 0x00 and 0xff are reserved for Realtek.
2479                 pHalData->EEPROMCustomerID      = EEPROM_Default_CustomerID;
2480                 pHalData->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID;
2481
2482         }
2483
2484         // For customized behavior.
2485         if((pHalData->EEPROMVID == 0x103C) || (pHalData->EEPROMVID == 0x1629))// HP Lite-On for RTL8188CUS Slim Combo.
2486                 pHalData->CustomerID = RT_CID_819x_HP;
2487
2488         //      Decide CustomerID according to VID/DID or EEPROM
2489         switch(pHalData->EEPROMCustomerID)
2490         {
2491                 case EEPROM_CID_DEFAULT:
2492                         if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3308))
2493                                 pHalData->CustomerID = RT_CID_DLINK;
2494                         else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3309))
2495                                 pHalData->CustomerID = RT_CID_DLINK;
2496                         else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x330a))
2497                                 pHalData->CustomerID = RT_CID_DLINK;
2498                         break;
2499                 case EEPROM_CID_WHQL:
2500 /*
2501                         Adapter->bInHctTest = TRUE;
2502
2503                         pMgntInfo->bSupportTurboMode = FALSE;
2504                         pMgntInfo->bAutoTurboBy8186 = FALSE;
2505
2506                         pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
2507                         pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
2508                         pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
2509
2510                         pMgntInfo->keepAliveLevel = 0;
2511
2512                         Adapter->bUnloadDriverwhenS3S4 = FALSE;
2513 */
2514                         break;
2515                 default:
2516                         pHalData->CustomerID = RT_CID_DEFAULT;
2517                         break;
2518
2519         }
2520
2521         MSG_8723A("EEPROMVID = 0x%04x\n", pHalData->EEPROMVID);
2522         MSG_8723A("EEPROMPID = 0x%04x\n", pHalData->EEPROMPID);
2523         MSG_8723A("EEPROMCustomerID : 0x%02x\n", pHalData->EEPROMCustomerID);
2524         MSG_8723A("EEPROMSubCustomerID: 0x%02x\n", pHalData->EEPROMSubCustomerID);
2525
2526         MSG_8723A("RT_CustomerID: 0x%02x\n", pHalData->CustomerID);
2527
2528 }
2529
2530
2531 static void
2532 _ReadMACAddress(
2533         PADAPTER        Adapter,
2534         u8*             PROMContent,
2535         bool            AutoloadFail
2536         )
2537 {
2538         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
2539
2540         if(_FALSE == AutoloadFail){
2541                 //Read Permanent MAC address and set value to hardware
2542                 memcpy(pEEPROM->mac_addr, &PROMContent[EEPROM_MAC_ADDR], ETH_ALEN);
2543         }
2544         else{
2545                 //Random assigh MAC address
2546                 u8 sMacAddr[MAC_ADDR_LEN] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00};
2547                 //sMacAddr[5] = (u8)GetRandomNumber(1, 254);
2548                 memcpy(pEEPROM->mac_addr, sMacAddr, ETH_ALEN);
2549         }
2550         DBG_8723A("%s MAC Address from EFUSE = "MAC_FMT"\n",__FUNCTION__, MAC_ARG(pEEPROM->mac_addr));
2551         //NicIFSetMacAddress(Adapter, Adapter->PermanentAddress);
2552         //RT_PRINT_ADDR(COMP_INIT|COMP_EFUSE, DBG_LOUD, "MAC Addr: %s", Adapter->PermanentAddress);
2553
2554 }
2555
2556 static void
2557 _ReadBoardType(
2558         PADAPTER        Adapter,
2559         u8*             PROMContent,
2560         bool            AutoloadFail
2561         )
2562 {
2563         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
2564         u32                     value32;
2565         u8                      boardType = BOARD_USB_DONGLE;
2566
2567         if(AutoloadFail){
2568                 if(IS_8723_SERIES(pHalData->VersionID))
2569                         pHalData->rf_type = RF_1T1R;
2570                 else
2571                         pHalData->rf_type = RF_2T2R;
2572
2573                 pHalData->BoardType = boardType;
2574                 return;
2575         }
2576
2577         boardType = PROMContent[EEPROM_NORMAL_BoardType];
2578         boardType &= BOARD_TYPE_NORMAL_MASK;//bit[7:5]
2579         boardType >>= 5;
2580
2581         pHalData->BoardType = boardType;
2582         MSG_8723A("_ReadBoardType(%x)\n",pHalData->BoardType);
2583
2584         if (boardType == BOARD_USB_High_PA)
2585                 pHalData->ExternalPA = 1;
2586 }
2587
2588
2589 static void
2590 _ReadLEDSetting(
2591         PADAPTER        Adapter,
2592         u8*             PROMContent,
2593         bool            AutoloadFail
2594         )
2595 {
2596         struct led_priv *pledpriv = &(Adapter->ledpriv);
2597         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2598 #ifdef CONFIG_SW_LED
2599         pledpriv->bRegUseLed = _TRUE;
2600
2601         //
2602         // Led mode
2603         //
2604         switch(pHalData->CustomerID)
2605         {
2606                 case RT_CID_DEFAULT:
2607                         pledpriv->LedStrategy = SW_LED_MODE1;
2608                         pledpriv->bRegUseLed = _TRUE;
2609                         break;
2610
2611                 case RT_CID_819x_HP:
2612                         pledpriv->LedStrategy = SW_LED_MODE6;
2613                         break;
2614
2615                 default:
2616                         pledpriv->LedStrategy = SW_LED_MODE1;
2617                         break;
2618         }
2619
2620         if( BOARD_MINICARD == pHalData->BoardType )
2621         {
2622                 pledpriv->LedStrategy = SW_LED_MODE6;
2623         }
2624         pHalData->bLedOpenDrain = _TRUE;// Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
2625 #else // HW LED
2626         pledpriv->LedStrategy = HW_LED;
2627 #endif //CONFIG_SW_LED
2628 }
2629
2630 static void
2631 _ReadThermalMeter(
2632         PADAPTER        Adapter,
2633         u8*     PROMContent,
2634         bool            AutoloadFail
2635         )
2636 {
2637         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2638         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
2639         u8      tempval;
2640
2641         //
2642         // ThermalMeter from EEPROM
2643         //
2644         if(!AutoloadFail)
2645                 tempval = PROMContent[EEPROM_THERMAL_METER];
2646         else
2647                 tempval = EEPROM_Default_ThermalMeter;
2648
2649         pHalData->EEPROMThermalMeter = (tempval&0x1f);  //[4:0]
2650
2651         if(pHalData->EEPROMThermalMeter == 0x1f || AutoloadFail)
2652                 pdmpriv->bAPKThermalMeterIgnore = _TRUE;
2653
2654         pdmpriv->ThermalMeter[0] = pHalData->EEPROMThermalMeter;
2655 }
2656
2657 static void
2658 _ReadRFSetting(
2659         PADAPTER        Adapter,
2660         u8*     PROMContent,
2661         bool            AutoloadFail
2662         )
2663 {
2664 }
2665
2666 // Read HW power down mode selection
2667 static void _ReadPSSetting(PADAPTER Adapter, u8*PROMContent, u8 AutoloadFail)
2668 {
2669         if(AutoloadFail){
2670                 Adapter->pwrctrlpriv.bHWPowerdown = _FALSE;
2671                 Adapter->pwrctrlpriv.bSupportRemoteWakeup = _FALSE;
2672         }
2673         else    {
2674                 //if(SUPPORT_HW_RADIO_DETECT(Adapter))
2675                         Adapter->pwrctrlpriv.bHWPwrPindetect = Adapter->registrypriv.hwpwrp_detect;
2676                 //else
2677                         //Adapter->pwrctrlpriv.bHWPwrPindetect = _FALSE;//dongle not support new
2678
2679
2680                 //hw power down mode selection , 0:rf-off / 1:power down
2681
2682                 if(Adapter->registrypriv.hwpdn_mode==2)
2683                         Adapter->pwrctrlpriv.bHWPowerdown = (PROMContent[EEPROM_RF_OPT3] & BIT4);
2684                 else
2685                         Adapter->pwrctrlpriv.bHWPowerdown = Adapter->registrypriv.hwpdn_mode;
2686
2687                 // decide hw if support remote wakeup function
2688                 // if hw supported, 8051 (SIE) will generate WeakUP signal( D+/D- toggle) when autoresume
2689                 Adapter->pwrctrlpriv.bSupportRemoteWakeup = (PROMContent[EEPROM_TEST_USB_OPT] & BIT1)?_TRUE :_FALSE;
2690
2691                 //if(SUPPORT_HW_RADIO_DETECT(Adapter))
2692                         //Adapter->registrypriv.usbss_enable = Adapter->pwrctrlpriv.bSupportRemoteWakeup ;
2693
2694                 DBG_8723A("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) ,bSupportRemoteWakeup(%x)\n",__FUNCTION__,
2695                 Adapter->pwrctrlpriv.bHWPwrPindetect,Adapter->pwrctrlpriv.bHWPowerdown ,Adapter->pwrctrlpriv.bSupportRemoteWakeup);
2696
2697                 DBG_8723A("### PS params=>  power_mgnt(%x),usbss_enable(%x) ###\n",Adapter->registrypriv.power_mgnt,Adapter->registrypriv.usbss_enable);
2698
2699         }
2700
2701 }
2702
2703
2704
2705
2706
2707
2708 void
2709 Hal_EfuseParsePIDVID_8723AU(
2710         PADAPTER                pAdapter,
2711         u8*                     hwinfo,
2712         bool                    AutoLoadFail
2713         )
2714 {
2715         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
2716
2717         if(AutoLoadFail)
2718         {
2719                 pHalData->EEPROMVID = 0;
2720                 pHalData->EEPROMPID = 0;
2721         }
2722         else
2723         {
2724                         // VID, PID
2725                 pHalData->EEPROMVID = le16_to_cpu(*(u16*)&hwinfo[EEPROM_VID_8723AU]);
2726                 pHalData->EEPROMPID = le16_to_cpu(*(u16*)&hwinfo[EEPROM_PID_8723AU]);
2727
2728         }
2729
2730         MSG_8723A("EEPROM VID = 0x%4x\n", pHalData->EEPROMVID);
2731         MSG_8723A("EEPROM PID = 0x%4x\n", pHalData->EEPROMPID);
2732 }
2733
2734
2735 static void
2736 Hal_EfuseParseMACAddr_8723AU(
2737         PADAPTER                padapter,
2738         u8*                     hwinfo,
2739         bool                    AutoLoadFail
2740         )
2741 {
2742         u16                     i, usValue;
2743         u8                      sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x87, 0x23, 0x00};
2744         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
2745
2746         if (AutoLoadFail)
2747         {
2748 //              sMacAddr[5] = (u8)GetRandomNumber(1, 254);
2749                 for (i=0; i<6; i++)
2750                         pEEPROM->mac_addr[i] = sMacAddr[i];
2751         }
2752         else
2753         {
2754                 //Read Permanent MAC address
2755 #if 1
2756                 memcpy(pEEPROM->mac_addr, &hwinfo[EEPROM_MAC_ADDR_8723AU], ETH_ALEN);
2757 #else
2758                 for(i=0; i<6; i+=2)
2759                 {
2760                         usValue = *(u16*)&hwinfo[EEPROM_MAC_ADDR_8723S+i];
2761                         *((u16*)(&pEEPROM->mac_addr[i])) = usValue;
2762                 }
2763 #endif
2764         }
2765 //      NicIFSetMacAddress(pAdapter, pAdapter->PermanentAddress);
2766
2767         RT_TRACE(_module_hci_hal_init_c_, _drv_notice_,
2768                  ("Hal_EfuseParseMACAddr_8723AU: Permanent Address=%02x:%02x:%02x:%02x:%02x:%02x\n",
2769                   pEEPROM->mac_addr[0], pEEPROM->mac_addr[1],
2770                   pEEPROM->mac_addr[2], pEEPROM->mac_addr[3],
2771                   pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]));
2772 }
2773
2774
2775 #ifdef CONFIG_EFUSE_CONFIG_FILE
2776 static u32 Hal_readPGDataFromConfigFile(
2777         PADAPTER        padapter)
2778 {
2779         u32 i;
2780         struct file *fp;
2781         mm_segment_t fs;
2782         u8 temp[3];
2783         loff_t pos = 0;
2784         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
2785         u8      *PROMContent = pEEPROM->efuse_eeprom_data;
2786
2787
2788         temp[2] = 0; // add end of string '\0'
2789
2790         fp = filp_open("/system/etc/wifi/wifi_efuse.map", O_RDWR,  0644);
2791         if (IS_ERR(fp)) {
2792                 pEEPROM->bloadfile_fail_flag= _TRUE;
2793                 DBG_8723A("Error, Efuse configure file doesn't exist.\n");
2794                 return _FAIL;
2795         }
2796
2797         fs = get_fs();
2798         set_fs(KERNEL_DS);
2799
2800         DBG_8723A("Efuse configure file:\n");
2801         for (i=0; i<HWSET_MAX_SIZE_88E; i++) {
2802                 vfs_read(fp, temp, 2, &pos);
2803                 PROMContent[i] = simple_strtoul(temp, NULL, 16 );
2804                 pos += 1; // Filter the space character
2805                 DBG_8723A("%02X \n", PROMContent[i]);
2806         }
2807         DBG_8723A("\n");
2808         set_fs(fs);
2809
2810         filp_close(fp, NULL);
2811
2812         pEEPROM->bloadfile_fail_flag= _FALSE;
2813         return _SUCCESS;
2814 }
2815
2816
2817 static void
2818 Hal_ReadMACAddrFromFile_8723AU(
2819         PADAPTER                padapter
2820         )
2821 {
2822         u32 i;
2823         struct file *fp;
2824         mm_segment_t fs;
2825         u8 source_addr[18];
2826         loff_t pos = 0;
2827         u32 curtime = rtw_get_current_time();
2828         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
2829         u8 *head, *end;
2830
2831         u8 null_mac_addr[ETH_ALEN] = {0, 0, 0,0, 0, 0};
2832         u8 multi_mac_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
2833
2834         memset(source_addr, 0, 18);
2835         memset(pEEPROM->mac_addr, 0, ETH_ALEN);
2836
2837         fp = filp_open("/data/wifimac.txt", O_RDWR,  0644);
2838         if (IS_ERR(fp)) {
2839                 pEEPROM->bloadmac_fail_flag = _TRUE;
2840                 DBG_8723A("Error, wifi mac address file doesn't exist.\n");
2841         } else {
2842                 fs = get_fs();
2843                 set_fs(KERNEL_DS);
2844
2845                 DBG_8723A("wifi mac address:\n");
2846                 vfs_read(fp, source_addr, 18, &pos);
2847                 source_addr[17] = ':';
2848
2849                 head = end = source_addr;
2850                 for (i=0; i<ETH_ALEN; i++) {
2851                         while (end && (*end != ':') )
2852                                 end++;
2853
2854                         if (end && (*end == ':') )
2855                                 *end = '\0';
2856
2857                         pEEPROM->mac_addr[i] = simple_strtoul(head, NULL, 16 );
2858
2859                         if (end) {
2860                                 end++;
2861                                 head = end;
2862                         }
2863                         DBG_8723A("%02x \n", pEEPROM->mac_addr[i]);
2864                 }
2865                 DBG_8723A("\n");
2866                 set_fs(fs);
2867
2868                 filp_close(fp, NULL);
2869         }
2870
2871         if ((!memcmp(pEEPROM->mac_addr, null_mac_addr, ETH_ALEN)) ||
2872             (!memcmp(pEEPROM->mac_addr, multi_mac_addr, ETH_ALEN)) ) {
2873                 pEEPROM->mac_addr[0] = 0x00;
2874                 pEEPROM->mac_addr[1] = 0xe0;
2875                 pEEPROM->mac_addr[2] = 0x4c;
2876                 pEEPROM->mac_addr[3] = (u8)(curtime & 0xff) ;
2877                 pEEPROM->mac_addr[4] = (u8)((curtime>>8) & 0xff) ;
2878                 pEEPROM->mac_addr[5] = (u8)((curtime>>16) & 0xff) ;
2879         }
2880
2881         pEEPROM->bloadmac_fail_flag = _FALSE;
2882
2883          DBG_8723A("Hal_ReadMACAddrFromFile_8188ES: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
2884                   pEEPROM->mac_addr[0], pEEPROM->mac_addr[1],
2885                   pEEPROM->mac_addr[2], pEEPROM->mac_addr[3],
2886                   pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]);
2887 }
2888 #endif //CONFIG_EFUSE_CONFIG_FILE
2889
2890
2891 static void
2892 readAdapterInfo(
2893         PADAPTER        padapter
2894         )
2895 {
2896         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
2897         //PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
2898         u8                      hwinfo[HWSET_MAX_SIZE];
2899
2900 #ifdef CONFIG_EFUSE_CONFIG_FILE
2901         Hal_readPGDataFromConfigFile(padapter);
2902 #else //CONFIG_EFUSE_CONFIG_FILE
2903         Hal_InitPGData(padapter, hwinfo);
2904 #endif  //CONFIG_EFUSE_CONFIG_FILE
2905         Hal_EfuseParseIDCode(padapter, hwinfo);
2906         Hal_EfuseParsePIDVID_8723AU(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
2907         Hal_EfuseParseEEPROMVer(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
2908 #ifdef CONFIG_EFUSE_CONFIG_FILE
2909         Hal_ReadMACAddrFromFile_8723AU(padapter);
2910 #else //CONFIG_EFUSE_CONFIG_FILE
2911         Hal_EfuseParseMACAddr_8723AU(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
2912 #endif
2913         Hal_EfuseParseTxPowerInfo_8723A(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
2914         _ReadBoardType(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
2915         Hal_EfuseParseBTCoexistInfo_8723A(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
2916
2917         rtl8723a_EfuseParseChnlPlan(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
2918         Hal_EfuseParseThermalMeter_8723A(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
2919         _ReadLEDSetting(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
2920 //      _ReadRFSetting(Adapter, PROMContent, pEEPROM->bautoload_fail_flag);
2921 //      _ReadPSSetting(Adapter, PROMContent, pEEPROM->bautoload_fail_flag);
2922         Hal_EfuseParseAntennaDiversity(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
2923
2924         Hal_EfuseParseEEPROMVer(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
2925         Hal_EfuseParseCustomerID(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
2926         Hal_EfuseParseRateIndicationOption(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
2927         Hal_EfuseParseXtal_8723A(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
2928         //
2929         // The following part initialize some vars by PG info.
2930         //
2931         Hal_InitChannelPlan(padapter);
2932
2933
2934
2935         //hal_CustomizedBehavior_8723U(Adapter);
2936
2937 //      Adapter->bDongle = (PROMContent[EEPROM_EASY_REPLACEMENT] == 1)? 0: 1;
2938         DBG_8723A("%s(): REPLACEMENT = %x\n",__FUNCTION__,padapter->bDongle);
2939 }
2940
2941 static void _ReadPROMContent(
2942  PADAPTER               Adapter
2943         )
2944 {
2945         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
2946         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2947         u8                      PROMContent[HWSET_MAX_SIZE]={0};
2948         u8                      eeValue;
2949         u32                     i;
2950         u16                     value16;
2951
2952         eeValue = rtw_read8(Adapter, REG_9346CR);
2953         // To check system boot selection.
2954         pEEPROM->EepromOrEfuse          = (eeValue & BOOT_FROM_EEPROM) ? _TRUE : _FALSE;
2955         pEEPROM->bautoload_fail_flag    = (eeValue & EEPROM_EN) ? _FALSE : _TRUE;
2956
2957
2958         DBG_8723A("Boot from %s, Autoload %s !\n", (pEEPROM->EepromOrEfuse ? "EEPROM" : "EFUSE"),
2959                                 (pEEPROM->bautoload_fail_flag ? "Fail" : "OK") );
2960
2961         readAdapterInfo(Adapter);
2962 }
2963
2964
2965 static void
2966 _InitOtherVariable(
2967  PADAPTER               Adapter
2968         )
2969 {
2970         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2971
2972
2973         //if(Adapter->bInHctTest){
2974         //      pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
2975         //      pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
2976         //      pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
2977         //      pMgntInfo->keepAliveLevel = 0;
2978         //}
2979
2980
2981 }
2982
2983 static void
2984 _ReadRFType(
2985         PADAPTER        Adapter
2986         )
2987 {
2988         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2989
2990 #if DISABLE_BB_RF
2991         pHalData->rf_chip = RF_PSEUDO_11N;
2992 #else
2993         pHalData->rf_chip = RF_6052;
2994 #endif
2995 }
2996
2997 void _ReadSilmComboMode(PADAPTER Adapter)
2998 {
2999         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3000
3001         pHalData->SlimComboDbg = _FALSE;        // Default is not debug mode.
3002 }
3003
3004 //
3005 //      Description:
3006 //              We should set Efuse cell selection to WiFi cell in default.
3007 //
3008 //      Assumption:
3009 //              PASSIVE_LEVEL
3010 //
3011 //      Added by Roger, 2010.11.23.
3012 //
3013 void
3014 hal_EfuseCellSel(
3015         PADAPTER        Adapter
3016         )
3017 {
3018         u32                     value32;
3019
3020         value32 = rtw_read32(Adapter, EFUSE_TEST);
3021         value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
3022         rtw_write32(Adapter, EFUSE_TEST, value32);
3023 }
3024
3025 static int _ReadAdapterInfo8723AU(PADAPTER      Adapter)
3026 {
3027         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
3028         u32 start=rtw_get_current_time();
3029
3030         MSG_8723A("====> _ReadAdapterInfo8723AU\n");
3031
3032         //Efuse_InitSomeVar(Adapter);
3033
3034         hal_EfuseCellSel(Adapter);
3035
3036         _ReadRFType(Adapter);//rf_chip -> _InitRFType()
3037         _ReadPROMContent(Adapter);
3038
3039         // 2010/10/25 MH THe function must be called after borad_type & IC-Version recognize.
3040         _ReadSilmComboMode(Adapter);
3041
3042         _InitOtherVariable(Adapter);
3043
3044         //MSG_8723A("%s()(done), rf_chip=0x%x, rf_type=0x%x\n",  __FUNCTION__, pHalData->rf_chip, pHalData->rf_type);
3045
3046         MSG_8723A("<==== _ReadAdapterInfo8723AU in %d ms\n", rtw_get_passing_time_ms(start));
3047
3048         return _SUCCESS;
3049 }
3050
3051
3052 static void ReadAdapterInfo8723AU(PADAPTER Adapter)
3053 {
3054         // Read EEPROM size before call any EEPROM function
3055         Adapter->EepromAddressSize = GetEEPROMSize8723A(Adapter);
3056
3057         _ReadAdapterInfo8723AU(Adapter);
3058 }
3059
3060
3061 #define GPIO_DEBUG_PORT_NUM 0
3062 static void rtl8192cu_trigger_gpio_0(_adapter *padapter)
3063 {
3064
3065         u32 gpioctrl;
3066         DBG_8723A("==> trigger_gpio_0...\n");
3067         rtw_write16_async(padapter,REG_GPIO_PIN_CTRL,0);
3068         rtw_write8_async(padapter,REG_GPIO_PIN_CTRL+2,0xFF);
3069         gpioctrl = (BIT(GPIO_DEBUG_PORT_NUM)<<24 )|(BIT(GPIO_DEBUG_PORT_NUM)<<16);
3070         rtw_write32_async(padapter,REG_GPIO_PIN_CTRL,gpioctrl);
3071         gpioctrl |= (BIT(GPIO_DEBUG_PORT_NUM)<<8);
3072         rtw_write32_async(padapter,REG_GPIO_PIN_CTRL,gpioctrl);
3073         DBG_8723A("<=== trigger_gpio_0...\n");
3074
3075 }
3076
3077 /*
3078  * If variable not handled here,
3079  * some variables will be processed in SetHwReg8723A()
3080  */
3081 void SetHwReg8723AU(PADAPTER Adapter, u8 variable, u8* val)
3082 {
3083         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(Adapter);
3084
3085 _func_enter_;
3086
3087         switch(variable)
3088         {
3089                 case HW_VAR_RXDMA_AGG_PG_TH:
3090 #ifdef CONFIG_USB_RX_AGGREGATION
3091                         {
3092                                 u8 threshold = *val;
3093                                 if (threshold == 0)
3094                                         threshold = pHalData->UsbRxAggPageCount;
3095                                 SetHwReg8723A(Adapter, HW_VAR_RXDMA_AGG_PG_TH, &threshold);
3096                         }
3097 #endif
3098                         break;
3099
3100                 case HW_VAR_SET_RPWM:
3101                         rtw_write8(Adapter, REG_USB_HRPWM, *val);
3102                         break;
3103
3104                 case HW_VAR_TRIGGER_GPIO_0:
3105                         rtl8192cu_trigger_gpio_0(Adapter);
3106                         break;
3107
3108                 default:
3109                         SetHwReg8723A(Adapter, variable, val);
3110                         break;
3111         }
3112
3113 _func_exit_;
3114 }
3115
3116 /*
3117  * If variable not handled here,
3118  * some variables will be processed in GetHwReg8723A()
3119  */
3120 void GetHwReg8723AU(PADAPTER Adapter, u8 variable, u8* val)
3121 {
3122         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(Adapter);
3123
3124 _func_enter_;
3125
3126         switch (variable)
3127         {
3128                 default:
3129                         GetHwReg8723A(Adapter, variable, val);
3130                         break;
3131         }
3132
3133 _func_exit_;
3134 }
3135
3136 //
3137 //      Description:
3138 //              Query setting of specified variable.
3139 //
3140 u8
3141 GetHalDefVar8192CUsb(
3142         PADAPTER                                Adapter,
3143         HAL_DEF_VARIABLE                eVariable,
3144         void *                                  pValue
3145         )
3146 {
3147         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3148         u8                      bResult = _SUCCESS;
3149
3150         switch(eVariable)
3151         {
3152                 case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
3153                         *((int *)pValue) = pHalData->dmpriv.UndecoratedSmoothedPWDB;
3154                         break;
3155                 case HAL_DEF_IS_SUPPORT_ANT_DIV:
3156                         #ifdef CONFIG_ANTENNA_DIVERSITY
3157                         *((u8 *)pValue) = (IS_92C_SERIAL(pHalData->VersionID) ||(pHalData->AntDivCfg==0))?_FALSE:_TRUE;
3158                         #endif
3159                         break;
3160                 case HAL_DEF_CURRENT_ANTENNA:
3161                         #ifdef CONFIG_ANTENNA_DIVERSITY
3162                         *(( u8*)pValue) = pHalData->CurAntenna;
3163                         #endif
3164                         break;
3165                 case HAL_DEF_DRVINFO_SZ:
3166                         *(( u32*)pValue) = DRVINFO_SZ;
3167                         break;
3168                 case HAL_DEF_MAX_RECVBUF_SZ:
3169                         *(( u32*)pValue) = MAX_RECVBUF_SZ;
3170                         break;
3171                 case HAL_DEF_RX_PACKET_OFFSET:
3172                         *(( u32*)pValue) = RXDESC_SIZE + DRVINFO_SZ;
3173                         break;
3174                 case HAL_DEF_DBG_DUMP_RXPKT:
3175                         *(( u8*)pValue) = pHalData->bDumpRxPkt;
3176                         break;
3177                 case HAL_DEF_DBG_DM_FUNC:
3178                         *(( u32*)pValue) =pHalData->odmpriv.SupportAbility;
3179                         break;
3180                 case HW_VAR_MAX_RX_AMPDU_FACTOR:
3181                         *(( u32*)pValue) = IEEE80211_HT_MAX_AMPDU_64K;
3182                         break;
3183                 case HW_DEF_ODM_DBG_FLAG:
3184                         {
3185                                 u8Byte  DebugComponents = *((u32*)pValue);
3186                                 PDM_ODM_T       pDM_Odm = &(pHalData->odmpriv);
3187                                 printk("pDM_Odm->DebugComponents = 0x%llx \n",pDM_Odm->DebugComponents );
3188                         }
3189                         break;
3190                 default:
3191                         //RT_TRACE(COMP_INIT, DBG_WARNING, ("GetHalDefVar8192CUsb(): Unkown variable: %d!\n", eVariable));
3192                         bResult = _FAIL;
3193                         break;
3194         }
3195
3196         return bResult;
3197 }
3198
3199
3200
3201
3202 //
3203 //      Description:
3204 //              Change default setting of specified variable.
3205 //
3206 u8
3207 SetHalDefVar8192CUsb(
3208         PADAPTER                                Adapter,
3209         HAL_DEF_VARIABLE                eVariable,
3210         void *                                  pValue
3211         )
3212 {
3213         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3214         u8                      bResult = _SUCCESS;
3215
3216         switch(eVariable)
3217         {
3218                 case HAL_DEF_DBG_DUMP_RXPKT:
3219                         pHalData->bDumpRxPkt = *(( u8*)pValue);
3220                         break;
3221                 case HAL_DEF_DBG_DM_FUNC:
3222                         {
3223                                 u8 dm_func = *(( u8*)pValue);
3224                                 struct dm_priv  *pdmpriv = &pHalData->dmpriv;
3225                                 DM_ODM_T                *podmpriv = &pHalData->odmpriv;
3226
3227                                 if(dm_func == 0){ //disable all dynamic func
3228                                         podmpriv->SupportAbility = DYNAMIC_FUNC_DISABLE;
3229                                         DBG_8723A("==> Disable all dynamic function...\n");
3230                                 }
3231                                 else if(dm_func == 1){//disable DIG
3232                                         podmpriv->SupportAbility  &= (~DYNAMIC_BB_DIG);
3233                                         DBG_8723A("==> Disable DIG...\n");
3234                                 }
3235                                 else if(dm_func == 2){//disable High power
3236                                         podmpriv->SupportAbility  &= (~DYNAMIC_BB_DYNAMIC_TXPWR);
3237                                 }
3238                                 else if(dm_func == 3){//disable tx power tracking
3239                                         podmpriv->SupportAbility  &= (~DYNAMIC_RF_CALIBRATION);
3240                                         DBG_8723A("==> Disable tx power tracking...\n");
3241                                 }
3242                                 else if(dm_func == 4){//disable BT coexistence
3243                                         pdmpriv->DMFlag &= (~DYNAMIC_FUNC_BT);
3244                                 }
3245                                 else if(dm_func == 5){//disable antenna diversity
3246                                         podmpriv->SupportAbility  &= (~DYNAMIC_BB_ANT_DIV);
3247                                 }
3248                                 else if(dm_func == 6){//turn on all dynamic func
3249                                         if(!(podmpriv->SupportAbility  & DYNAMIC_BB_DIG))
3250                                         {
3251                                                 DIG_T   *pDigTable = &podmpriv->DM_DigTable;
3252                                                 pDigTable->CurIGValue= rtw_read8(Adapter,0xc50);
3253                                         }
3254                                         pdmpriv->DMFlag |= DYNAMIC_FUNC_BT;
3255                                         podmpriv->SupportAbility = DYNAMIC_ALL_FUNC_ENABLE;
3256                                         DBG_8723A("==> Turn on all dynamic function...\n");
3257                                 }
3258                         }
3259                         break;
3260                 case HW_DEF_FA_CNT_DUMP:
3261                         {
3262                                 u8 bRSSIDump = *((u8*)pValue);
3263                                 PDM_ODM_T               pDM_Odm = &(pHalData->odmpriv);
3264                                 if(bRSSIDump)
3265                                         pDM_Odm->DebugComponents        =       ODM_COMP_DIG|ODM_COMP_FA_CNT    ;
3266                                 else
3267                                         pDM_Odm->DebugComponents        = 0;
3268
3269                         }
3270                         break;
3271                 case HW_DEF_ODM_DBG_FLAG:
3272                         {
3273                                 u8Byte  DebugComponents = *((u8Byte*)pValue);
3274                                 PDM_ODM_T       pDM_Odm = &(pHalData->odmpriv);
3275                                 pDM_Odm->DebugComponents = DebugComponents;
3276                         }
3277                         break;
3278                 default:
3279                         //RT_TRACE(COMP_INIT, DBG_TRACE, ("SetHalDefVar819xUsb(): Unkown variable: %d!\n", eVariable));
3280                         bResult = _FAIL;
3281                         break;
3282         }
3283
3284         return bResult;
3285 }
3286
3287 /*
3288 u32  _update_92cu_basic_rate(_adapter *padapter, unsigned int mask)
3289 {
3290         PHAL_DATA_TYPE          pHalData = GET_HAL_DATA(padapter);
3291         unsigned int BrateCfg = 0;
3292
3293
3294         if(pHalData->VersionID != VERSION_TEST_CHIP_88C)
3295                 BrateCfg = mask  & 0x15F;
3296         else    //for 88CU 46PING setting, Disable CCK 2M, 5.5M, Others must tuning
3297                 BrateCfg = mask  & 0x159;
3298
3299         BrateCfg |= 0x01; // default enable 1M ACK rate
3300
3301         return BrateCfg;
3302 }
3303 */
3304 void _update_response_rate(_adapter *padapter,unsigned int mask)
3305 {
3306         u8      RateIndex = 0;
3307         // Set RRSR rate table.
3308         rtw_write8(padapter, REG_RRSR, mask&0xff);
3309         rtw_write8(padapter,REG_RRSR+1, (mask>>8)&0xff);
3310
3311         // Set RTS initial rate
3312         while(mask > 0x1)
3313         {
3314                 mask = (mask>> 1);
3315                 RateIndex++;
3316         }
3317         rtw_write8(padapter, REG_INIRTS_RATE_SEL, RateIndex);
3318 }
3319
3320 void UpdateHalRAMask8192CUsb(PADAPTER padapter, u32 mac_id,u8 rssi_level )
3321 {
3322         //volatile unsigned int result;
3323         u8      init_rate=0;
3324         u8      networkType, raid;
3325         u32     mask,rate_bitmap;
3326         u8      shortGIrate = _FALSE;
3327         int     supportRateNum = 0;
3328         struct sta_info *psta;
3329         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);
3330         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
3331         struct mlme_ext_priv    *pmlmeext = &padapter->mlmeextpriv;
3332         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
3333         WLAN_BSSID_EX           *cur_network = &(pmlmeinfo->network);
3334 #ifdef CONFIG_CONCURRENT_MODE
3335         if(rtw_buddy_adapter_up(padapter) && padapter->adapter_type > PRIMARY_ADAPTER)
3336                 pHalData = GET_HAL_DATA(padapter->pbuddy_adapter);
3337 #endif //CONFIG_CONCURRENT_MODE
3338
3339         if (mac_id >= NUM_STA) //CAM_SIZE
3340         {
3341                 return;
3342         }
3343
3344         psta = pmlmeinfo->FW_sta_info[mac_id].psta;
3345         if(psta == NULL)
3346         {
3347                 return;
3348         }
3349
3350         switch (mac_id)
3351         {
3352                 case 0:// for infra mode
3353 #ifdef CONFIG_CONCURRENT_MODE
3354                 case 2:// first station uses macid=0, second station uses macid=2
3355 #endif
3356                         supportRateNum = rtw_get_rateset_len(cur_network->SupportedRates);
3357                         networkType = judge_network_type(padapter, cur_network->SupportedRates, supportRateNum) & 0xf;
3358                         //pmlmeext->cur_wireless_mode = networkType;
3359                         raid = networktype_to_raid(networkType);
3360
3361                         mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
3362                         mask |= (pmlmeinfo->HT_enable)? update_MSC_rate(&(pmlmeinfo->HT_caps)): 0;
3363
3364
3365                         if (support_short_GI(padapter, &(pmlmeinfo->HT_caps)))
3366                         {
3367                                 shortGIrate = _TRUE;
3368                         }
3369
3370                         break;
3371
3372                 case 1://for broadcast/multicast
3373                         supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
3374                         if(pmlmeext->cur_wireless_mode & WIRELESS_11B)
3375                                 networkType = WIRELESS_11B;
3376                         else
3377                                 networkType = WIRELESS_11G;
3378                         raid = networktype_to_raid(networkType);
3379
3380                         mask = update_basic_rate(cur_network->SupportedRates, supportRateNum);
3381
3382                         break;
3383
3384                 default: //for each sta in IBSS
3385                         supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
3386                         networkType = judge_network_type(padapter, pmlmeinfo->FW_sta_info[mac_id].SupportedRates, supportRateNum) & 0xf;
3387                         //pmlmeext->cur_wireless_mode = networkType;
3388                         raid = networktype_to_raid(networkType);
3389
3390                         mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
3391
3392
3393                         //todo: support HT in IBSS
3394
3395                         break;
3396         }
3397
3398         //mask &=0x0fffffff;
3399         rate_bitmap = 0x0fffffff;
3400 #ifdef  CONFIG_ODM_REFRESH_RAMASK
3401         {
3402                 rate_bitmap = ODM_Get_Rate_Bitmap(&pHalData->odmpriv,mac_id,mask,rssi_level);
3403                 printk("%s => mac_id:%d, networkType:0x%02x, mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n",
3404                         __FUNCTION__,mac_id,networkType,mask,rssi_level,rate_bitmap);
3405         }
3406 #endif
3407
3408         mask &= rate_bitmap;
3409         mask |= ((raid<<28)&0xf0000000);
3410
3411
3412         init_rate = get_highest_rate_idx(mask)&0x3f;
3413
3414         if(pHalData->fw_ractrl == _TRUE)
3415         {
3416                 u8 arg = 0;
3417
3418                 //arg = (cam_idx-4)&0x1f;//MACID
3419                 arg = mac_id&0x1f;//MACID
3420
3421                 arg |= BIT(7);
3422
3423                 if (shortGIrate==_TRUE)
3424                         arg |= BIT(5);
3425
3426                 DBG_8723A("update raid entry, mask=0x%x, arg=0x%x\n", mask, arg);
3427
3428                 rtl8192c_set_raid_cmd(padapter, mask, arg);
3429
3430         }
3431         else
3432         {
3433                 if (shortGIrate==_TRUE)
3434                         init_rate |= BIT(6);
3435
3436                 rtw_write8(padapter, (REG_INIDATA_RATE_SEL+mac_id), init_rate);
3437         }
3438
3439
3440         //set ra_id
3441         psta->raid = raid;
3442         psta->init_rate = init_rate;
3443
3444         //set correct initial date rate for each mac_id
3445         pdmpriv->INIDATA_RATE[mac_id] = init_rate;
3446 }
3447
3448 static void rtl8723au_init_default_value(PADAPTER padapter)
3449 {
3450         rtl8723a_init_default_value(padapter);
3451 }
3452
3453 static u8 rtl8192cu_ps_func(PADAPTER Adapter,HAL_INTF_PS_FUNC efunc_id, u8 *val)
3454 {
3455         u8 bResult = _TRUE;
3456         switch(efunc_id){
3457
3458                 #if defined(CONFIG_AUTOSUSPEND) && defined(SUPPORT_HW_RFOFF_DETECTED)
3459                 case HAL_USB_SELECT_SUSPEND:
3460                         {
3461                                 u8 bfwpoll = *(( u8*)val);
3462                                 rtl8192c_set_FwSelectSuspend_cmd(Adapter,bfwpoll ,500);//note fw to support hw power down ping detect
3463                         }
3464                         break;
3465                 #endif //CONFIG_AUTOSUSPEND && SUPPORT_HW_RFOFF_DETECTED
3466
3467                 default:
3468                         break;
3469         }
3470         return bResult;
3471 }
3472
3473 void rtl8723au_set_hal_ops(_adapter * padapter)
3474 {
3475         struct hal_ops  *pHalFunc = &padapter->HalFunc;
3476
3477 _func_enter_;
3478
3479         padapter->HalData = kzalloc(sizeof(HAL_DATA_TYPE), GFP_KERNEL);
3480         if(padapter->HalData == NULL){
3481                 DBG_8723A("cant not alloc memory for HAL DATA \n");
3482         }
3483         //memset(padapter->HalData, 0, sizeof(HAL_DATA_TYPE));
3484         padapter->hal_data_sz = sizeof(HAL_DATA_TYPE);
3485
3486         pHalFunc->hal_init = &rtl8723au_hal_init;
3487         pHalFunc->hal_deinit = &rtl8723au_hal_deinit;
3488
3489         //pHalFunc->free_hal_data = &rtl8192c_free_hal_data;
3490
3491         pHalFunc->inirp_init = &rtl8723au_inirp_init;
3492         pHalFunc->inirp_deinit = &rtl8723au_inirp_deinit;
3493
3494         pHalFunc->init_xmit_priv = &rtl8192cu_init_xmit_priv;
3495         pHalFunc->free_xmit_priv = &rtl8192cu_free_xmit_priv;
3496
3497         pHalFunc->init_recv_priv = &rtl8192cu_init_recv_priv;
3498         pHalFunc->free_recv_priv = &rtl8192cu_free_recv_priv;
3499 #ifdef CONFIG_SW_LED
3500         pHalFunc->InitSwLeds = &rtl8723au_InitSwLeds;
3501         pHalFunc->DeInitSwLeds = &rtl8723au_DeInitSwLeds;
3502 #else //case of hw led or no led
3503         pHalFunc->InitSwLeds = NULL;
3504         pHalFunc->DeInitSwLeds = NULL;
3505 #endif//CONFIG_SW_LED
3506
3507         pHalFunc->init_default_value = &rtl8723au_init_default_value;
3508         pHalFunc->intf_chip_configure = &rtl8192cu_interface_configure;
3509         pHalFunc->read_adapter_info = &ReadAdapterInfo8723AU;
3510
3511         //pHalFunc->set_bwmode_handler = &PHY_SetBWMode8192C;
3512         //pHalFunc->set_channel_handler = &PHY_SwChnl8192C;
3513
3514         //pHalFunc->hal_dm_watchdog = &rtl8192c_HalDmWatchDog;
3515
3516         pHalFunc->SetHwRegHandler = &SetHwReg8723AU;
3517         pHalFunc->GetHwRegHandler = &GetHwReg8723AU;
3518         pHalFunc->GetHalDefVarHandler = &GetHalDefVar8192CUsb;
3519         pHalFunc->SetHalDefVarHandler = &SetHalDefVar8192CUsb;
3520
3521         pHalFunc->UpdateRAMaskHandler = &UpdateHalRAMask8192CUsb;
3522
3523         pHalFunc->hal_xmit = &rtl8192cu_hal_xmit;
3524         pHalFunc->mgnt_xmit = &rtl8192cu_mgnt_xmit;
3525         pHalFunc->hal_xmitframe_enqueue = &rtl8723au_hal_xmitframe_enqueue;
3526
3527 #ifdef CONFIG_HOSTAPD_MLME
3528         pHalFunc->hostap_mgnt_xmit_entry = &rtl8192cu_hostap_mgnt_xmit_entry;
3529 #endif
3530         pHalFunc->interface_ps_func = &rtl8192cu_ps_func;
3531
3532         rtl8723a_set_hal_ops(pHalFunc);
3533
3534 _func_exit_;
3535
3536 }