1 ; -*- coding: utf-8 -*-
3 ; Fast Forth For Texas Instrument MSP430FR6989
5 ; Copyright (C) <2014> <J.M. THOORENS>
7 ; This program is free software: you can redistribute it and/or modify
8 ; it under the terms of the GNU General Public License as published by
9 ; the Free Software Foundation, either version 3 of the License, or
10 ; (at your option) any later version.
12 ; This program is distributed in the hope that it will be useful,
13 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ; GNU General Public License for more details.
17 ; You should have received a copy of the GNU General Public License
18 ; along with this program. If not, see <http://www.gnu.org/licenses/>.
20 ; ======================================================================
21 ; INIT MSP-EXP430FR6989 board
22 ; ======================================================================
25 ; http://www.ebay.fr/itm/CP2102-USB-UART-Board-mini-Data-Transfer-Convertor-Module-Development-Board-/251433941479
27 ; for sd card socket be carefull : pin CD must be present !
28 ; http://www.ebay.com/itm/2-PCS-SD-Card-Module-Slot-Socket-Reader-For-Arduino-MCU-/181211954262?pt=LH_DefaultDomain_0&hash=item2a3112fc56
31 ; J101 eZ-FET <-> target
32 ; -----------------------
34 ; P3 <-> P4 - TEST - TEST
35 ; P5 <-> P6 - RST - RST
36 ; P7 <-> P8 - TX1 - P3.4 UCA1 TXD ---> RX UARTtoUSB module
37 ; P9 <->P10 - RX1 - P3.5 UCA1 RXD <--- TX UARTtoUSB module
38 ; P11<->P12 - CTS - P3.1
39 ; P13<->P14 - RTS - P3.0
40 ; P15<->P16 - VCC - 3V3
42 ; P19<->P20 - GND - VSS
44 ; Launchpad Header Left J1
45 ; ------------------------
57 ; Launchpad Header Left J3
58 ; ------------------------
70 ; Launchpad Header Right J2
71 ; -------------------------
74 ; P18- P1.5 TA0.0 UCA0 CLK
81 ; P11- P4.7 TA1.2 UCB1 SOMI/SCL
83 ; Launchpad Header Right J4
84 ; -------------------------
93 ; P32- P3.1 UCB1 SIMO/SDA
156 ; ===================================================================================
157 ; in case of 3.3V powered by UARTtoUSB bridge, open J13 straps {RST,TST,V+,5V} BEFORE
158 ; then wire VCC and GND of bridge onto J13 connector
159 ; ===================================================================================
161 ; ---------------------------------------------------
162 ; MSP - MSP-EXP430FR6989 LAUNCHPAD <--> OUTPUT WORLD
163 ; ---------------------------------------------------
167 ; P1.1 - Switch S1 <--- LCD contrast + (finger :-)
168 ; P1.2 - Switch S2 <--- LCD contrast - (finger ;-)
170 ; note : ESI1.1 = lowest left pin
171 ; note : ESI1.2 is not connected to 3.3V
172 ; GND/ESIVSS - ESI1.3 <-------+---0V0----------> 1 LCD_Vss
173 ; VCC/ESIVCC - ESI1.4 >------ | --3V3-----+----> 2 LCD_Vdd
180 ; P3.6 - UCA1 CLK TB0.2 J4.37 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
181 ; P9.0/ESICH0 - ESI1.14 <------------------------> 11 LCD_DB4
182 ; P9.1/ESICH1 - ESI1.13 <------------------------> 12 LCD_DB5
183 ; P9.2/ESICH2 - ESI1.12 <------------------------> 13 LCD_DB5
184 ; P9.3/ESICH3 - ESI1.11 <------------------------> 14 LCD_DB7
185 ; P9.4/ESICI0 - ESI1.10 -------------------------> 4 LCD_RS
186 ; P9.5/ESICI1 - ESI1.9 -------------------------> 5 LCD_R/W
187 ; P9.6/ESICI2 - ESI1.8 -------------------------> 6 LCD_EN
189 ; +--4k7-< DeepRST <-- GND
191 ; P3.4 - UCA1 TXD J101.8 <-+-> RX UARTtoUSB bridge
192 ; P3.5 - UCA1 RXD J101.10 <---- TX UARTtoUSB bridge
193 ; P3.0 - RTS J101.14 ----> CTS UARTtoUSB bridge (optional hardware control flow)
194 ; VCC - J101.16 <---- VCC (optional supply from UARTtoUSB bridge - WARNING ! 3.3V !)
195 ; GND - J101.20 <---> GND (optional supply from UARTtoUSB bridge)
197 ; VCC - J1.1 ----> VCC SD_CardAdapter
198 ; GND - J2.20 <---> GND SD_CardAdapter
199 ; P2.2 - UCA0 CLK J4.35 ----> CLK SD_CardAdapter (SCK)
200 ; P2.6 - J4.39 ----> CS SD_CardAdapter (Card Select)
201 ; P2.0 - UCA0 TXD/SIMO J1.8 ----> SDI SD_CardAdapter (MOSI)
202 ; P2.1 - UCA0 RXD/SOMI J2.19 <---- SDO SD_CardAdapter (MISO)
203 ; P2.7 - J4.40 <---- CD SD_CardAdapter (Card Detect)
205 ; P4.0 - J1.10 <---- OUT IR_Receiver (1 TSOP32236)
206 ; VCC - J6.1 ----> VCC IR_Receiver (2 TSOP32236)
207 ; GND - J6.2 <---> GND IR_Receiver (3 TSOP32236)
209 ; P1.3 - J4.34 <---> SDA software I2C Master
210 ; P1.5 - J2.18 ----> SCL software I2C Master
212 ; P1.4 -UCB0 CLK TA1.0 J1.7 <---> free
214 ; P1.6 -UCB0 SDA/SIMO J2.15 <---> SDA hardware I2C Master or Slave
215 ; P1.7 -UCB0 SCL/SOMI J2.14 ----> SCL hardware I2C Master or Slave
217 ; P3.0 -UCB1 CLK J4.33 ----> free (if UARTtoUSB with software control flow)
218 ; P3.1 -UCB1 SDA/SIMO J4.32 <---> free
219 ; P3.2 -UCB1 SCL/SOMI J1.5 ----> free
220 ; P3.3 - TA1.1 J1.5 <---> free
222 ; PJ.4 - LFXI 32768Hz quartz
223 ; PJ.5 - LFXO 32768Hz quartz
228 ; ----------------------------------------------------------------------
229 ; INIT order : WDT, GPIOs, FRAM, Clock, UARTs...
230 ; ----------------------------------------------------------------------
232 ; ----------------------------------------------------------------------
233 ; POWER ON RESET AND INITIALIZATION : LOCK PMM_LOCKLPM5
234 ; ----------------------------------------------------------------------
236 ; BIS #LOCKLPM5,&PM5CTL0 ; unlocked by WARM
238 ; ----------------------------------------------------------------------
239 ; POWER ON RESET AND INITIALIZATION : WATCHDOG TIMER A
240 ; ----------------------------------------------------------------------
242 MOV #WDTPW+WDTHOLD+WDTCNTCL,&WDTCTL ; stop WDT
244 ; ----------------------------------------------------------------------
245 ; POWER ON RESET AND INITIALIZATION : I/O
246 ; ----------------------------------------------------------------------
248 ; ----------------------------------------------------------------------
249 ; POWER ON RESET AND INITIALIZATION : PORT1/2
250 ; ----------------------------------------------------------------------
252 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
256 SD_SEL .equ PASEL0 ; to configure UCB0
257 SD_REN .equ PAREN ; to configure pullup resistors
258 SD_BUS .equ 0700h ; pins P2.2 as UCA0CLK, P2.0 as UCA0SIMO & P2.1 as UCA0SOMI
262 ; P1.0 - LED1 red output low
265 SWITCHIN .set P1IN ; port
266 S1 .set 2 ; P1.1 bit position
270 SD_CS .equ 40h ; P2.6 as SD_CS
271 SD_CD .equ 80h ; P2.7 as SD_CD
276 ; PORTx default wanted state : pins as input with pullup resistor
278 MOV #-2,&PAOUT ; all pins with pullup resistors else P1.0
279 BIS #-1,&PAREN ; all pins with pull up/down resistor
281 ; ----------------------------------------------------------------------
282 ; POWER ON RESET AND INITIALIZATION : PORT3/4
283 ; ----------------------------------------------------------------------
285 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
286 ; PORTx default wanted state : pins as input with pullup resistor
296 HANDSHAKOUT .equ P3OUT
300 TXD .equ 10h ; P3.4 = TXD + FORTH Deep_RST pin
301 RXD .equ 20h ; P3.4 = RXD
302 TERM_BUS .equ 30h ; P3.5 = RX
303 TERM_IN .equ P3IN ; TERMINAL TX pin as FORTH Deep_RST
310 MOV #-1,&PBREN ; all pins as input with resistor
311 MOV #-1,&PBOUT ; all pins as input with resistor
313 .IFDEF TERMINAL4WIRES
314 ; RTS output is wired to the CTS input of UART2USB bridge
315 ; configure RTS as output high to disable RX TERM during start FORTH
316 BIS.B #RTS,&P3DIR ; RTS as output high
317 .IFDEF TERMINAL5WIRES
318 ; CTS input must be wired to the RTS output of UART2USB bridge
319 ; configure CTS as input low (true) to avoid lock when CTS is not wired
320 BIC.B #CTS,&P3OUT ; CTS input pulled down
321 .ENDIF ; TERMINAL5WIRES
322 .ENDIF ; TERMINAL4WIRES
324 ; ----------------------------------------------------------------------
325 ; POWER ON RESET AND INITIALIZATION : PORT5/6
326 ; ----------------------------------------------------------------------
328 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
334 ; PORTx default wanted state : pins as input with pullup resistor
336 MOV #-1,&PCOUT ; all pins 1
337 MOV #-1,&PCREN ; all pins with pull resistors
340 ; ----------------------------------------------------------------------
341 ; POWER ON RESET AND INITIALIZATION : PORT7/8
342 ; ----------------------------------------------------------------------
344 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
350 ; PORTx default wanted state : pins as input with pullup resistor
352 MOV #-1,&PDOUT ; all pins 1
353 MOV #-1,&PDREN ; all pins with pull resistors
357 ; ----------------------------------------------------------------------
358 ; POWER ON RESET AND INITIALIZATION : PORT9/10
359 ; ----------------------------------------------------------------------
361 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
364 ; P9.7 Green LED2 as output low
368 ; PORTx default wanted state : pins as input with pullup resistor
370 MOV #0FF7Fh,&PEOUT ; all pins high else P9.7
371 MOV #-1,&PEREN ; all pins with pull resistors else P9.7
373 ; ----------------------------------------------------------------------
374 ; POWER ON RESET AND INITIALIZATION : PORTJ
375 ; ----------------------------------------------------------------------
377 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
381 ; PORTx default wanted state : pins as input with pullup resistor
383 MOV.B #-1,&PJOUT ; pullup resistors
384 MOV.B #-1,&PJREN ; enable pullup/pulldown resistors
386 ; ----------------------------------------------------------------------
388 ; ----------------------------------------------------------------------
391 MOV.B #0A5h, &FRCTL0_H ; enable FRCTL0 access
392 MOV.B #10h, &FRCTL0 ; 1 waitstate @ 16 MHz
393 MOV.B #01h, &FRCTL0_H ; disable FRCTL0 access
396 ; ----------------------------------------------------------------------
397 ; POWER ON RESET AND INITIALIZATION : CLOCK SYSTEM
398 ; ----------------------------------------------------------------------
400 ; DCOCLK: Internal digitally controlled oscillator (DCO).
403 ; CS code for MSP430FR5948
404 MOV.B #CSKEY,&CSCTL0_H ; Unlock CS registers
407 ; MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 8MHZ DCO setting (default value)
408 MOV #DIVA_0 + DIVS_32 + DIVM_32,&CSCTL3
411 .ELSEIF FREQUENCY = 0.5
412 MOV #0,&CSCTL1 ; Set 1MHZ DCO setting
413 MOV #DIVA_2 + DIVS_2 + DIVM_2,&CSCTL3 ; set all dividers as 2
416 .ELSEIF FREQUENCY = 1
417 MOV #0,&CSCTL1 ; Set 1MHZ DCO setting
418 MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
421 .ELSEIF FREQUENCY = 2
422 MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 4MHZ DCO setting
423 MOV #DIVA_0 + DIVS_2 + DIVM_2,&CSCTL3
426 .ELSEIF FREQUENCY = 4
427 MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 4MHZ DCO setting
428 MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
431 .ELSEIF FREQUENCY = 8
432 ; MOV #DCOFSEL2+DCOFSEL1,&CSCTL1 ; Set 8MHZ DCO setting (default value)
433 MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
436 .ELSEIF FREQUENCY = 16
437 MOV #DCORSEL+DCOFSEL2,&CSCTL1 ; Set 16MHZ DCO setting
438 MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
442 .error "bad frequency setting, only 0.5,1,2,4,8,16 MHz"
446 MOV #SELA_LFXCLK+SELS_DCOCLK+SELM_DCOCLK,&CSCTL2
448 MOV #SELA_VLOCLK+SELS_DCOCLK+SELM_DCOCLK,&CSCTL2
450 MOV.B #01h, &CSCTL0_H ; Lock CS Registers
452 BIS &SYSRSTIV,&SAVE_SYSRSTIV ; store volatile SYSRSTIV preserving a pending request for DEEP_RST
453 ; MOV &SAVE_SYSRSTIV,TOS ;
454 ; CMP #2,TOS ; POWER ON ?
455 ; JZ ClockWaitX ; yes
456 ; RRUM #2,X ; wait only 125 ms
457 ClockWaitX MOV #5209,Y ; wait 0.5s before starting after POWER ON
458 ClockWaitY SUB #1,Y ;1
459 JNZ ClockWaitY ;2 5209x3 = 15625 cycles delay = 15.625ms @ 1MHz
460 SUB #1,X ; x 32 @ 1 MHZ = 500ms
461 JNZ ClockWaitX ; time to stabilize power source ( 500ms )
463 ; ----------------------------------------------------------------------
464 ; POWER ON RESET AND INITIALIZATION : REF
465 ; ----------------------------------------------------------------------
467 MOV #REFTCOFF, &REFCTL
470 ; ----------------------------------------------------------------------
471 ; POWER ON RESET AND INITIALIZATION : RTC_C REGISTERS
472 ; ----------------------------------------------------------------------
475 ; LFXIN : PJ.4, LFXOUT : PJ.5
476 BIS.B #010h,&PJSEL0 ; SEL0 for only LXIN
477 BIC.B #RTCHOLD,&RTCCTL1 ; Clear RTCHOLD = start RTC_B
480 ; ----------------------------------------------------------------------
481 ; POWER ON RESET AND INITIALIZATION : SYS REGISTERS
482 ; ----------------------------------------------------------------------