2 * Copyright © 2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
36 #include <pciaccess.h>
38 #include "libdrm_macros.h"
39 #include "intel_bufmgr.h"
40 #include "intel_bufmgr_priv.h"
43 /** @file intel_bufmgr.c
45 * Convenience functions for buffer management methods.
49 drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
50 unsigned long size, unsigned int alignment)
52 return bufmgr->bo_alloc(bufmgr, name, size, alignment);
56 drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, const char *name,
57 unsigned long size, unsigned int alignment)
59 return bufmgr->bo_alloc_for_render(bufmgr, name, size, alignment);
63 drm_intel_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
64 const char *name, void *addr,
70 if (bufmgr->bo_alloc_userptr)
71 return bufmgr->bo_alloc_userptr(bufmgr, name, addr, tiling_mode,
77 drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
78 int x, int y, int cpp, uint32_t *tiling_mode,
79 unsigned long *pitch, unsigned long flags)
81 return bufmgr->bo_alloc_tiled(bufmgr, name, x, y, cpp,
82 tiling_mode, pitch, flags);
86 drm_intel_bo_reference(drm_intel_bo *bo)
88 bo->bufmgr->bo_reference(bo);
92 drm_intel_bo_unreference(drm_intel_bo *bo)
97 bo->bufmgr->bo_unreference(bo);
101 drm_intel_bo_map(drm_intel_bo *buf, int write_enable)
103 return buf->bufmgr->bo_map(buf, write_enable);
107 drm_intel_bo_unmap(drm_intel_bo *buf)
109 return buf->bufmgr->bo_unmap(buf);
113 drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
114 unsigned long size, const void *data)
116 return bo->bufmgr->bo_subdata(bo, offset, size, data);
120 drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
121 unsigned long size, void *data)
124 if (bo->bufmgr->bo_get_subdata)
125 return bo->bufmgr->bo_get_subdata(bo, offset, size, data);
127 if (size == 0 || data == NULL)
130 ret = drm_intel_bo_map(bo, 0);
133 memcpy(data, (unsigned char *)bo->virtual + offset, size);
134 drm_intel_bo_unmap(bo);
139 drm_intel_bo_wait_rendering(drm_intel_bo *bo)
141 bo->bufmgr->bo_wait_rendering(bo);
145 drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr)
147 bufmgr->destroy(bufmgr);
151 drm_intel_bo_exec(drm_intel_bo *bo, int used,
152 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
154 return bo->bufmgr->bo_exec(bo, used, cliprects, num_cliprects, DR4);
158 drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
159 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
162 if (bo->bufmgr->bo_mrb_exec)
163 return bo->bufmgr->bo_mrb_exec(bo, used,
164 cliprects, num_cliprects, DR4,
168 case I915_EXEC_DEFAULT:
169 case I915_EXEC_RENDER:
170 return bo->bufmgr->bo_exec(bo, used,
171 cliprects, num_cliprects, DR4);
178 drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug)
180 bufmgr->debug = enable_debug;
184 drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count)
186 return bo_array[0]->bufmgr->check_aperture_space(bo_array, count);
190 drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name)
192 if (bo->bufmgr->bo_flink)
193 return bo->bufmgr->bo_flink(bo, name);
199 drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
200 drm_intel_bo *target_bo, uint32_t target_offset,
201 uint32_t read_domains, uint32_t write_domain)
203 return bo->bufmgr->bo_emit_reloc(bo, offset,
204 target_bo, target_offset,
205 read_domains, write_domain);
208 /* For fence registers, not GL fences */
210 drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
211 drm_intel_bo *target_bo, uint32_t target_offset,
212 uint32_t read_domains, uint32_t write_domain)
214 return bo->bufmgr->bo_emit_reloc_fence(bo, offset,
215 target_bo, target_offset,
216 read_domains, write_domain);
221 drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment)
223 if (bo->bufmgr->bo_pin)
224 return bo->bufmgr->bo_pin(bo, alignment);
230 drm_intel_bo_unpin(drm_intel_bo *bo)
232 if (bo->bufmgr->bo_unpin)
233 return bo->bufmgr->bo_unpin(bo);
239 drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
242 if (bo->bufmgr->bo_set_tiling)
243 return bo->bufmgr->bo_set_tiling(bo, tiling_mode, stride);
245 *tiling_mode = I915_TILING_NONE;
250 drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
251 uint32_t * swizzle_mode)
253 if (bo->bufmgr->bo_get_tiling)
254 return bo->bufmgr->bo_get_tiling(bo, tiling_mode, swizzle_mode);
256 *tiling_mode = I915_TILING_NONE;
257 *swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
262 drm_intel_bo_set_softpin_offset(drm_intel_bo *bo, uint64_t offset)
264 if (bo->bufmgr->bo_set_softpin_offset)
265 return bo->bufmgr->bo_set_softpin_offset(bo, offset);
271 drm_intel_bo_disable_reuse(drm_intel_bo *bo)
273 if (bo->bufmgr->bo_disable_reuse)
274 return bo->bufmgr->bo_disable_reuse(bo);
279 drm_intel_bo_is_reusable(drm_intel_bo *bo)
281 if (bo->bufmgr->bo_is_reusable)
282 return bo->bufmgr->bo_is_reusable(bo);
287 drm_intel_bo_busy(drm_intel_bo *bo)
289 if (bo->bufmgr->bo_busy)
290 return bo->bufmgr->bo_busy(bo);
295 drm_intel_bo_madvise(drm_intel_bo *bo, int madv)
297 if (bo->bufmgr->bo_madvise)
298 return bo->bufmgr->bo_madvise(bo, madv);
303 drm_intel_bo_use_48b_address_range(drm_intel_bo *bo, uint32_t enable)
305 if (bo->bufmgr->bo_use_48b_address_range) {
306 bo->bufmgr->bo_use_48b_address_range(bo, enable);
314 drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
316 return bo->bufmgr->bo_references(bo, target_bo);
320 drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
322 if (bufmgr->get_pipe_from_crtc_id)
323 return bufmgr->get_pipe_from_crtc_id(bufmgr, crtc_id);
329 drm_intel_probe_agp_aperture_size(int fd)
331 struct pci_device *pci_dev;
335 ret = pci_system_init();
339 /* XXX handle multiple adaptors? */
340 pci_dev = pci_device_find_by_slot(0, 0, 2, 0);
344 ret = pci_device_probe(pci_dev);
348 size = pci_dev->regions[2].size;
350 pci_system_cleanup ();
355 drm_intel_probe_agp_aperture_size(int fd)
357 /* Nothing seems to rely on this value on Android anyway... */
358 fprintf(stderr, "%s: Mappable aperture size hardcoded to 64MiB\n", __func__);
359 return 64 * 1024 * 1024;
364 drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total)
367 struct drm_i915_gem_get_aperture aperture;
370 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
375 /* XXX add a query for the kernel value? */
377 *mappable = drm_intel_probe_agp_aperture_size(fd);
379 *mappable = 64 * 1024 * 1024; /* minimum possible value */
380 *total = aperture.aper_size;