linux-core/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon_drv.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33
  34 union atom_supported_devices {
  35   struct _ATOM_SUPPORTED_DEVICES_INFO info;
  36   struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  37   struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  38 };
  39
  40 static inline struct radeon_i2c_bus_rec radeon_lookup_gpio_for_ddc(struct drm_device *dev, uint8_t id)
  41 {
  42         struct drm_radeon_private *dev_priv = dev->dev_private;
  43         struct atom_context *ctx = dev_priv->mode_info.atom_context;
  44         ATOM_GPIO_I2C_ASSIGMENT gpio;
  45         struct radeon_i2c_bus_rec i2c;
  46         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  47         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  48         uint16_t data_offset;
  49
  50         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  51         i2c.valid = false;
  52
  53         atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
  54
  55         i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
  56
  57         gpio = i2c_info->asGPIO_Info[id];
  58
  59         i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4;
  60         i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4;
  61         i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4;
  62         i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4;
  63         i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4;
  64         i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4;
  65         i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift);
  66         i2c.mask_data_mask = (1 << gpio.ucDataMaskShift);
  67         i2c.put_clk_mask = (1 << gpio.ucClkEnShift);
  68         i2c.put_data_mask = (1 << gpio.ucDataEnShift);
  69         i2c.get_clk_mask = (1 << gpio.ucClkY_Shift);
  70         i2c.get_data_mask = (1 <<  gpio.ucDataY_Shift);
  71         i2c.valid = true;
  72
  73         return i2c;
  74 }
  75
  76 static void radeon_atom_apply_quirks(struct drm_device *dev, int index)
  77 {
  78         struct drm_radeon_private *dev_priv = dev->dev_private;
  79         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
  80
  81         if ((dev->pdev->device == 0x791e) &&
  82             (dev->pdev->subsystem_vendor == 0x1043) &&
  83             (dev->pdev->subsystem_device == 0x826d)) {
  84                 if ((mode_info->bios_connector[index].connector_type == CONNECTOR_HDMI_TYPE_A) &&
  85                     (mode_info->bios_connector[index].tmds_type == TMDS_LVTMA)) {
  86                         mode_info->bios_connector[index].connector_type = CONNECTOR_DVI_D;
  87                 }
  88         }
  89
  90         if ((dev->pdev->device == 0x5653) &&
  91             (dev->pdev->subsystem_vendor == 0x1462) &&
  92             (dev->pdev->subsystem_device == 0x0291)) {
  93                 if (mode_info->bios_connector[index].connector_type == CONNECTOR_LVDS) {
  94                         mode_info->bios_connector[index].ddc_i2c.valid = false;
  95                 }
  96         }
  97 }
  98
  99 bool radeon_get_atom_connector_info_from_bios_connector_table(struct drm_device *dev)
 100 {
 101         struct drm_radeon_private *dev_priv = dev->dev_private;
 102         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 103         struct atom_context *ctx = mode_info->atom_context;
 104         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 105         uint16_t size, data_offset;
 106         uint8_t frev, crev;
 107         uint16_t device_support;
 108
 109         union atom_supported_devices *supported_devices;
 110         int i,j;
 111         atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 112
 113         supported_devices = (union atom_supported_devices *)(ctx->bios + data_offset);
 114
 115         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 116
 117         for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
 118
 119                 ATOM_CONNECTOR_INFO_I2C ci = supported_devices->info.asConnInfo[i];
 120
 121                 if (!(device_support & (1 << i))) {
 122                         mode_info->bios_connector[i].valid = false;
 123                         continue;
 124                 }
 125
 126                 if (i == ATOM_DEVICE_CV_INDEX) {
 127                         DRM_DEBUG("Skipping Component Video\n");
 128                         mode_info->bios_connector[i].valid = false;
 129                         continue;
 130                 }
 131
 132                 if (i == ATOM_DEVICE_TV1_INDEX) {
 133                         DRM_DEBUG("Skipping TV Out\n");
 134                         mode_info->bios_connector[i].valid = false;
 135                         continue;
 136                 }
 137
 138                 mode_info->bios_connector[i].valid = true;
 139                 mode_info->bios_connector[i].output_id = ci.sucI2cId.sbfAccess.bfI2C_LineMux;
 140                 mode_info->bios_connector[i].devices = 1 << i;
 141                 mode_info->bios_connector[i].connector_type = ci.sucConnectorInfo.sbfAccess.bfConnectorType;
 142
 143                 if (mode_info->bios_connector[i].connector_type == CONNECTOR_NONE) {
 144                         mode_info->bios_connector[i].valid = false;
 145                         continue;
 146                 }
 147
 148                 mode_info->bios_connector[i].dac_type = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 149
 150                 if ((i == ATOM_DEVICE_TV1_INDEX) ||
 151                     (i == ATOM_DEVICE_TV2_INDEX) ||
 152                     (i == ATOM_DEVICE_TV1_INDEX))
 153                         mode_info->bios_connector[i].ddc_i2c.valid = false;
 154                 else if ((dev_priv->chip_family == CHIP_RS600) ||
 155                          (dev_priv->chip_family == CHIP_RS690) ||
 156                          (dev_priv->chip_family == CHIP_RS740)) {
 157                         if ((i == ATOM_DEVICE_DFP2_INDEX) || (i == ATOM_DEVICE_DFP3_INDEX))
 158                                 mode_info->bios_connector[i].ddc_i2c =
 159                                         radeon_lookup_gpio_for_ddc(dev, ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1);
 160                         else
 161                                 mode_info->bios_connector[i].ddc_i2c =
 162                                         radeon_lookup_gpio_for_ddc(dev, ci.sucI2cId.sbfAccess.bfI2C_LineMux);
 163                 } else
 164                         mode_info->bios_connector[i].ddc_i2c =
 165                                 radeon_lookup_gpio_for_ddc(dev, ci.sucI2cId.sbfAccess.bfI2C_LineMux);
 166
 167                 if (i == ATOM_DEVICE_DFP1_INDEX)
 168                         mode_info->bios_connector[i].tmds_type = TMDS_INT;
 169                 else if (i == ATOM_DEVICE_DFP2_INDEX) {
 170                         if ((dev_priv->chip_family == CHIP_RS600) ||
 171                             (dev_priv->chip_family == CHIP_RS690) ||
 172                             (dev_priv->chip_family == CHIP_RS740))
 173                                 mode_info->bios_connector[i].tmds_type = TMDS_DDIA;
 174                         else
 175                                 mode_info->bios_connector[i].tmds_type = TMDS_EXT;
 176                 } else if (i == ATOM_DEVICE_DFP3_INDEX)
 177                         mode_info->bios_connector[i].tmds_type = TMDS_LVTMA;
 178                 else
 179                         mode_info->bios_connector[i].tmds_type = TMDS_NONE;
 180
 181                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
 182                  * shared with a DVI port, we'll pick up the DVI connector below when we
 183                  * merge the outputs
 184                  */
 185                 if ((i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) &&
 186                     (mode_info->bios_connector[i].connector_type == CONNECTOR_DVI_I ||
 187                      mode_info->bios_connector[i].connector_type == CONNECTOR_DVI_D ||
 188                      mode_info->bios_connector[i].connector_type == CONNECTOR_DVI_A)) {
 189                         mode_info->bios_connector[i].connector_type = CONNECTOR_VGA;
 190                 }
 191
 192                 if (crev > 1) {
 193                         ATOM_CONNECTOR_INC_SRC_BITMAP isb = supported_devices->info_2.asIntSrcInfo[i];
 194
 195                         switch(isb.ucIntSrcBitmap) {
 196                         case 0x4:
 197                                 mode_info->bios_connector[i].hpd_mask = 0x1;
 198                                 break;
 199                         case 0xa:
 200                                 mode_info->bios_connector[i].hpd_mask = 0x100;
 201                                 break;
 202                         default:
 203                                 mode_info->bios_connector[i].hpd_mask = 0;
 204                                 break;
 205                         }
 206                 } else {
 207                         mode_info->bios_connector[i].hpd_mask = 0;
 208                 }
 209
 210                 radeon_atom_apply_quirks(dev, i);
 211         }
 212
 213         /* CRTs/DFPs may share a port */
 214         for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
 215                 if (!mode_info->bios_connector[i].valid)
 216                         continue;
 217
 218                 for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) {
 219                         if (mode_info->bios_connector[j].valid && (i != j)) {
 220                                 if (mode_info->bios_connector[i].output_id ==
 221                                     mode_info->bios_connector[j].output_id) {
 222                                         if (((i == ATOM_DEVICE_DFP1_INDEX) ||
 223                                              (i == ATOM_DEVICE_DFP2_INDEX) ||
 224                                              (i == ATOM_DEVICE_DFP3_INDEX)) &&
 225                                             ((j == ATOM_DEVICE_CRT1_INDEX) ||
 226                                              (j == ATOM_DEVICE_CRT2_INDEX))) {
 227                                                 mode_info->bios_connector[i].dac_type = mode_info->bios_connector[j].dac_type;
 228                                                 mode_info->bios_connector[i].devices |= mode_info->bios_connector[j].devices;
 229                                                 mode_info->bios_connector[i].hpd_mask = mode_info->bios_connector[j].hpd_mask;
 230                                                 mode_info->bios_connector[j].valid = false;
 231                                         } else if (((j == ATOM_DEVICE_DFP1_INDEX) ||
 232                                                     (j == ATOM_DEVICE_DFP2_INDEX) ||
 233                                                     (j == ATOM_DEVICE_DFP3_INDEX)) &&
 234                                                    ((i == ATOM_DEVICE_CRT1_INDEX) ||
 235                                                     (i == ATOM_DEVICE_CRT2_INDEX))) {
 236                                                 mode_info->bios_connector[j].dac_type = mode_info->bios_connector[i].dac_type;
 237                                                 mode_info->bios_connector[j].devices |= mode_info->bios_connector[i].devices;
 238                                                 mode_info->bios_connector[j].hpd_mask = mode_info->bios_connector[i].hpd_mask;
 239                                                 mode_info->bios_connector[i].valid = false;
 240                                         }
 241                                 }
 242                         }
 243                 }
 244         }
 245
 246
 247         DRM_DEBUG("BIOS Connector table\n");
 248         for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
 249                 if (!mode_info->bios_connector[i].valid)
 250                         continue;
 251
 252                 DRM_DEBUG("Port %d: ddc_type 0x%x, dac_type %d, tmds_type %d, connector type %d, hpd_mask %d\n",
 253                           i, mode_info->bios_connector[i].ddc_i2c.mask_clk_reg,
 254                           mode_info->bios_connector[i].dac_type,
 255                           mode_info->bios_connector[i].tmds_type,
 256                           mode_info->bios_connector[i].connector_type,
 257                           mode_info->bios_connector[i].hpd_mask);
 258         }
 259         return true;
 260 }
 261
 262 union firmware_info {
 263         ATOM_FIRMWARE_INFO info;
 264         ATOM_FIRMWARE_INFO_V1_2 info_12;
 265         ATOM_FIRMWARE_INFO_V1_3 info_13;
 266         ATOM_FIRMWARE_INFO_V1_4 info_14;
 267 };
 268
 269 bool radeon_atom_get_clock_info(struct drm_device *dev)
 270 {
 271         struct drm_radeon_private *dev_priv = dev->dev_private;
 272         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 273         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 274         union firmware_info *firmware_info;
 275         uint8_t frev, crev;
 276         struct radeon_pll *pll = &mode_info->pll;
 277         uint16_t data_offset;
 278
 279         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
 280
 281         firmware_info = (union firmware_info *)(mode_info->atom_context->bios + data_offset);
 282
 283         pll->reference_freq = le16_to_cpu(firmware_info->info.usReferenceClock);
 284         pll->reference_div = 0;
 285
 286         pll->pll_out_min = le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
 287         pll->pll_out_max = le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
 288
 289         if (pll->pll_out_min == 0) {
 290                 if (radeon_is_avivo(dev_priv))
 291                         pll->pll_out_min = 64800;
 292                 else
 293                         pll->pll_out_min = 20000;
 294         }
 295
 296         pll->pll_in_min = le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
 297         pll->pll_in_max = le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
 298
 299         pll->xclk = le16_to_cpu(firmware_info->info.usMaxPixelClock);
 300
 301         return true;
 302 }
 303
 304 union lvds_info {
 305         struct _ATOM_LVDS_INFO info;
 306         struct _ATOM_LVDS_INFO_V12 info_12;
 307 };
 308
 309 void radeon_get_lvds_info(struct radeon_encoder *encoder)
 310 {
 311         struct drm_device *dev = encoder->base.dev;
 312         struct drm_radeon_private *dev_priv = dev->dev_private;
 313         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 314         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
 315         uint16_t data_offset;
 316         union lvds_info *lvds_info;
 317         uint8_t frev, crev;
 318
 319         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
 320
 321         lvds_info = (union lvds_info *)(mode_info->atom_context->bios + data_offset);
 322
 323         encoder->dotclock = le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
 324         encoder->panel_xres = le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
 325         encoder->panel_yres = le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
 326         encoder->hblank = le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
 327         encoder->hoverplus = le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
 328         encoder->hsync_width = le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
 329
 330         encoder->vblank = le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
 331         encoder->hoverplus = le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
 332         encoder->hsync_width = le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
 333         encoder->panel_pwr_delay = le16_to_cpu(lvds_info->info.usOffDelayInMs);
 334 }
 335
 336 void radeon_atom_dyn_clk_setup(struct drm_device *dev, int enable)
 337 {
 338         struct drm_radeon_private *dev_priv = dev->dev_private;
 339         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 340         struct atom_context *ctx = mode_info->atom_context;
 341         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
 342         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
 343
 344         args.ucEnable = enable;
 345
 346         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
 347 }
 348
 349 void radeon_atom_static_pwrmgt_setup(struct drm_device *dev, int enable)
 350 {
 351         struct drm_radeon_private *dev_priv = dev->dev_private;
 352         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 353         struct atom_context *ctx = mode_info->atom_context;
 354         ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
 355         int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
 356
 357         args.ucEnable = enable;
 358
 359         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
 360 }
 361