/* don't need this yet */
}
-void radeon_restore_crtc_registers(struct drm_device *dev, struct radeon_legacy_state *state)
-{
- struct drm_radeon_private *dev_priv = dev->dev_private;
-
- RADEON_WRITE(RADEON_CRTC_GEN_CNTL, state->crtc_gen_cntl |
- RADEON_CRTC_DISP_REQ_EN_B);
-
- RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, state->crtc_ext_cntl,
- RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_DISPLAY_DIS);
-
- RADEON_WRITE(RADEON_CRTC_H_TOTAL_DISP, state->crtc_h_total_disp);
- RADEON_WRITE(RADEON_CRTC_H_SYNC_STRT_WID, state->crtc_h_sync_strt_wid);
- RADEON_WRITE(RADEON_CRTC_V_TOTAL_DISP, state->crtc_v_total_disp);
- RADEON_WRITE(RADEON_CRTC_V_SYNC_STRT_WID, state->crtc_v_sync_strt_wid);
-
- if (radeon_is_r300(dev_priv))
- RADEON_WRITE(R300_CRTC_TILE_X0_Y0, state->crtc_tile_x0_y0);
-
- RADEON_WRITE(RADEON_CRTC_OFFSET_CNTL, state->crtc_offset_cntl);
- RADEON_WRITE(RADEON_CRTC_OFFSET, state->crtc_offset);
-
- RADEON_WRITE(RADEON_CRTC_PITCH, state->crtc_pitch);
- RADEON_WRITE(RADEON_DISP_MERGE_CNTL, state->disp_merge_cntl);
-
- /* if dell server */
- if (0)
- {
- RADEON_WRITE(RADEON_TV_DAC_CNTL, state->tv_dac_cntl);
- RADEON_WRITE(RADEON_DISP_HW_DEBUG, state->disp_hw_debug);
- RADEON_WRITE(RADEON_DAC_CNTL2, state->dac2_cntl);
- RADEON_WRITE(RADEON_CRTC2_GEN_CNTL, state->crtc2_gen_cntl);
- }
-
- RADEON_WRITE(RADEON_CRTC_GEN_CNTL, state->crtc_gen_cntl);
-}
-
-void radeon_restore_crtc2_registers(struct drm_device *dev, struct radeon_legacy_state *state)
-{
- struct drm_radeon_private *dev_priv = dev->dev_private;
-
- /* We prevent the CRTC from hitting th
- e memory controller until
- * fully programmed
- */
- RADEON_WRITE(RADEON_CRTC2_GEN_CNTL,
- state->crtc2_gen_cntl | RADEON_CRTC2_VSYNC_DIS |
- RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_DIS |
- RADEON_CRTC2_DISP_REQ_EN_B);
-
- RADEON_WRITE(RADEON_CRTC2_H_TOTAL_DISP, state->crtc2_h_total_disp);
- RADEON_WRITE(RADEON_CRTC2_H_SYNC_STRT_WID, state->crtc2_h_sync_strt_wid);
- RADEON_WRITE(RADEON_CRTC2_V_TOTAL_DISP, state->crtc2_v_total_disp);
- RADEON_WRITE(RADEON_CRTC2_V_SYNC_STRT_WID, state->crtc2_v_sync_strt_wid);
-
- RADEON_WRITE(RADEON_FP_H2_SYNC_STRT_WID, state->fp_h2_sync_strt_wid);
- RADEON_WRITE(RADEON_FP_V2_SYNC_STRT_WID, state->fp_v2_sync_strt_wid);
-
- if (radeon_is_r300(dev_priv))
- RADEON_WRITE(R300_CRTC2_TILE_X0_Y0, state->crtc2_tile_x0_y0);
- RADEON_WRITE(RADEON_CRTC2_OFFSET_CNTL, state->crtc2_offset_cntl);
- RADEON_WRITE(RADEON_CRTC2_OFFSET, state->crtc2_offset);
-
- RADEON_WRITE(RADEON_CRTC2_PITCH, state->crtc2_pitch);
- RADEON_WRITE(RADEON_DISP2_MERGE_CNTL, state->disp2_merge_cntl);
-
- RADEON_WRITE(RADEON_CRTC2_GEN_CNTL, state->crtc2_gen_cntl);
-}
-
static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
{
struct drm_radeon_private *dev_priv = dev->dev_private;
struct drm_radeon_private *dev_priv = dev->dev_private;
while (RADEON_READ_PLL(dev_priv, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
-
+
RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_REF_DIV,
RADEON_P2PLL_ATOMIC_UPDATE_W,
~(RADEON_P2PLL_ATOMIC_UPDATE_W));
return 1;
}
-void radeon_restore_pll_registers(struct drm_device *dev, struct radeon_legacy_state *state)
-{
- struct drm_radeon_private *dev_priv = dev->dev_private;
- uint8_t pll_gain;
-
- pll_gain = radeon_compute_pll_gain(dev_priv->mode_info.pll.reference_freq,
- state->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
- state->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK);
-
- if (dev_priv->flags & RADEON_IS_MOBILITY) {
- /* A temporal workaround for the occational blanking on certain laptop panels.
- This appears to related to the PLL divider registers (fail to lock?).
- It occurs even when all dividers are the same with their old settings.
- In this case we really don't need to fiddle with PLL registers.
- By doing this we can avoid the blanking problem with some panels.
- */
- if ((state->ppll_ref_div == (RADEON_READ_PLL(dev_priv, RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
- (state->ppll_div_3 == (RADEON_READ_PLL(dev_priv, RADEON_PPLL_DIV_3) &
- (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
- RADEON_WRITE_P(RADEON_CLOCK_CNTL_INDEX,
- RADEON_PLL_DIV_SEL,
- ~(RADEON_PLL_DIV_SEL));
- radeon_pll_errata_after_index(dev_priv);
- return;
- }
- }
-
- RADEON_WRITE_PLL_P(dev_priv, RADEON_VCLK_ECP_CNTL,
- RADEON_VCLK_SRC_SEL_CPUCLK,
- ~(RADEON_VCLK_SRC_SEL_MASK));
-
- RADEON_WRITE_PLL_P(dev_priv,
- RADEON_PPLL_CNTL,
- RADEON_PPLL_RESET
- | RADEON_PPLL_ATOMIC_UPDATE_EN
- | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
- | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
- ~(RADEON_PPLL_RESET
- | RADEON_PPLL_ATOMIC_UPDATE_EN
- | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
- | RADEON_PPLL_PVG_MASK));
-
- RADEON_WRITE_P(RADEON_CLOCK_CNTL_INDEX,
- RADEON_PLL_DIV_SEL,
- ~(RADEON_PLL_DIV_SEL));
- radeon_pll_errata_after_index(dev_priv);
-
- if (radeon_is_r300(dev_priv) ||
- (dev_priv->chip_family == CHIP_RS300) ||
- (dev_priv->chip_family == CHIP_RS400) ||
- (dev_priv->chip_family == CHIP_RS480)) {
- if (state->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
- /* When restoring console mode, use saved PPLL_REF_DIV
- * setting.
- */
- RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
- state->ppll_ref_div,
- 0);
- } else {
- /* R300 uses ref_div_acc field as real ref divider */
- RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
- (state->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
- ~R300_PPLL_REF_DIV_ACC_MASK);
- }
- } else {
- RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
- state->ppll_ref_div,
- ~RADEON_PPLL_REF_DIV_MASK);
- }
-
- RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_DIV_3,
- state->ppll_div_3,
- ~RADEON_PPLL_FB3_DIV_MASK);
-
- RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_DIV_3,
- state->ppll_div_3,
- ~RADEON_PPLL_POST3_DIV_MASK);
-
- radeon_pll_write_update(dev);
- radeon_pll_wait_for_read_update_complete(dev);
-
- RADEON_WRITE_PLL(dev_priv, RADEON_HTOTAL_CNTL, state->htotal_cntl);
-
- RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_CNTL,
- 0,
- ~(RADEON_PPLL_RESET
- | RADEON_PPLL_SLEEP
- | RADEON_PPLL_ATOMIC_UPDATE_EN
- | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
-
- DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
- state->ppll_ref_div,
- state->ppll_div_3,
- (unsigned)state->htotal_cntl,
- RADEON_READ_PLL(dev_priv, RADEON_PPLL_CNTL));
- DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n",
- state->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
- state->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK,
- (state->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16);
-
- mdelay(50); /* Let the clock to lock */
-
- RADEON_WRITE_PLL_P(dev_priv, RADEON_VCLK_ECP_CNTL,
- RADEON_VCLK_SRC_SEL_PPLLCLK,
- ~(RADEON_VCLK_SRC_SEL_MASK));
-
- /*RADEON_WRITE_PLL(dev_priv, RADEON_VCLK_ECP_CNTL, state->vclk_ecp_cntl);*/
-
-}
-
-void radeon_restore_pll2_registers(struct drm_device *dev, struct radeon_legacy_state *state)
-{
- struct drm_radeon_private *dev_priv = dev->dev_private;
- uint8_t pll_gain;
-
- pll_gain = radeon_compute_pll_gain(dev_priv->mode_info.pll.reference_freq,
- state->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
- state->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK);
-
-
- RADEON_WRITE_PLL_P(dev_priv, RADEON_PIXCLKS_CNTL,
- RADEON_PIX2CLK_SRC_SEL_CPUCLK,
- ~(RADEON_PIX2CLK_SRC_SEL_MASK));
-
- RADEON_WRITE_PLL_P(dev_priv,
- RADEON_P2PLL_CNTL,
- RADEON_P2PLL_RESET
- | RADEON_P2PLL_ATOMIC_UPDATE_EN
- | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
- ~(RADEON_P2PLL_RESET
- | RADEON_P2PLL_ATOMIC_UPDATE_EN
- | RADEON_P2PLL_PVG_MASK));
-
-
- RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_REF_DIV,
- state->p2pll_ref_div,
- ~RADEON_P2PLL_REF_DIV_MASK);
-
- RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_DIV_0,
- state->p2pll_div_0,
- ~RADEON_P2PLL_FB0_DIV_MASK);
-
- RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_DIV_0,
- state->p2pll_div_0,
- ~RADEON_P2PLL_POST0_DIV_MASK);
-
- radeon_pll2_write_update(dev);
- radeon_pll2_wait_for_read_update_complete(dev);
-
- RADEON_WRITE_PLL(dev_priv, RADEON_HTOTAL2_CNTL, state->htotal_cntl2);
-
- RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_CNTL,
- 0,
- ~(RADEON_P2PLL_RESET
- | RADEON_P2PLL_SLEEP
- | RADEON_P2PLL_ATOMIC_UPDATE_EN));
-
- DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
- (unsigned)state->p2pll_ref_div,
- (unsigned)state->p2pll_div_0,
- (unsigned)state->htotal_cntl2,
- RADEON_READ_PLL(dev_priv, RADEON_P2PLL_CNTL));
- DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n",
- (unsigned)state->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
- (unsigned)state->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK,
- (unsigned)((state->p2pll_div_0 &
- RADEON_P2PLL_POST0_DIV_MASK) >>16));
-
- mdelay(50); /* Let the clock to lock */
-
- RADEON_WRITE_PLL_P(dev_priv, RADEON_PIXCLKS_CNTL,
- RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
- ~(RADEON_PIX2CLK_SRC_SEL_MASK));
-
- RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, state->pixclks_cntl);
-
-
-}
-
-
void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
{
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
uint32_t mask;
- mask = radeon_crtc->crtc_id ?
+ mask = radeon_crtc->crtc_id ?
(RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_REQ_EN_B) :
(RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS);
}
break;
}
-
+
if (mode != DRM_MODE_DPMS_OFF) {
radeon_crtc_load_lut(crtc);
}
}
-static bool radeon_init_crtc_base(struct drm_crtc *crtc, struct radeon_legacy_state *state, int x, int y)
+static bool radeon_set_crtc1_base(struct drm_crtc *crtc, int x, int y)
{
- struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+ struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
struct drm_device *dev = crtc->dev;
struct drm_radeon_private *dev_priv = dev->dev_private;
struct radeon_framebuffer *radeon_fb;
struct drm_radeon_gem_object *obj_priv;
uint32_t base;
+ uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
radeon_fb = to_radeon_framebuffer(crtc->fb);
obj_priv = radeon_fb->obj->driver_private;
- state->crtc_offset = obj_priv->bo->offset + dev_priv->fb_location;
+ crtc_offset = obj_priv->bo->offset;
- state->crtc_offset_cntl = 0;
+ crtc_offset_cntl = 0;
/* TODO tiling */
if (0) {
- if (radeon_is_r300(dev_priv)) {
- state->crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
- R300_CRTC_MICRO_TILE_BUFFER_DIS |
- R300_CRTC_MACRO_TILE_EN);
- } else {
- state->crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
- }
+ if (radeon_is_r300(dev_priv))
+ crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
+ R300_CRTC_MICRO_TILE_BUFFER_DIS |
+ R300_CRTC_MACRO_TILE_EN);
+ else
+ crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
} else {
- if (radeon_is_r300(dev_priv)) {
- state->crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
- R300_CRTC_MICRO_TILE_BUFFER_DIS |
- R300_CRTC_MACRO_TILE_EN);
- } else {
- state->crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
- }
+ if (radeon_is_r300(dev_priv))
+ crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
+ R300_CRTC_MICRO_TILE_BUFFER_DIS |
+ R300_CRTC_MACRO_TILE_EN);
+ else
+ crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
}
base = obj_priv->bo->offset;
/* TODO more tiling */
if (0) {
if (radeon_is_r300(dev_priv)) {
- state->crtc_tile_x0_y0 = x | (y << 16);
- base &= ~0x7ff;
- } else {
- int byteshift = crtc->fb->bits_per_pixel >> 4;
- int tile_addr = (((y >> 3) * crtc->fb->width + x) >> (8 - byteshift)) << 11;
- base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
- state->crtc_offset_cntl |= (y % 16);
- }
+ crtc_tile_x0_y0 = x | (y << 16);
+ base &= ~0x7ff;
+ } else {
+ int byteshift = crtc->fb->bits_per_pixel >> 4;
+ int tile_addr = (((y >> 3) * crtc->fb->width + x) >> (8 - byteshift)) << 11;
+ base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
+ crtc_offset_cntl |= (y % 16);
+ }
} else {
int offset = y * crtc->fb->pitch + x;
switch (crtc->fb->bits_per_pixel) {
+ case 15:
+ case 16:
+ offset *= 2;
+ break;
+ case 24:
+ offset *= 3;
+ break;
+ case 32:
+ offset *= 4;
+ break;
+ default:
+ return false;
}
base += offset;
}
/* update sarea TODO */
- state->crtc_offset = base;
+ crtc_offset = base;
+
+ if (radeon_is_r300(dev_priv))
+ RADEON_WRITE(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
+
+ RADEON_WRITE(RADEON_CRTC_OFFSET_CNTL, crtc_offset_cntl);
+ RADEON_WRITE(RADEON_CRTC_OFFSET, crtc_offset);
+
return true;
}
-static bool radeon_init_crtc_registers(struct drm_crtc *crtc, struct radeon_legacy_state *state,
- struct drm_display_mode *mode)
+static bool radeon_set_crtc1_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
{
- struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+ struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
struct drm_device *dev = crtc->dev;
struct drm_radeon_private *dev_priv = dev->dev_private;
int format;
int hsync_start;
int hsync_wid;
int vsync_wid;
+ uint32_t crtc_gen_cntl;
+ uint32_t crtc_ext_cntl;
+ uint32_t crtc_h_total_disp;
+ uint32_t crtc_h_sync_strt_wid;
+ uint32_t crtc_v_total_disp;
+ uint32_t crtc_v_sync_strt_wid;
+ uint32_t crtc_pitch;
+ uint32_t disp_merge_cntl;
switch (crtc->fb->depth) {
- case 15: format = 3; break; /* 555 */
- case 16: format = 4; break; /* 565 */
- case 24: format = 5; break; /* RGB */
- case 32: format = 6; break; /* xRGB */
+ case 15: /* 555 */
+ format = 3;
+ break;
+ case 16: /* 565 */
+ format = 4;
+ break;
+ case 24: /* RGB */
+ format = 5;
+ break;
+ case 32: /* xRGB */
+ format = 6;
+ break;
default:
return false;
}
- state->crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN
- | RADEON_CRTC_EN
- | (format << 8)
- | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
- ? RADEON_CRTC_DBL_SCAN_EN
- : 0)
- | ((mode->flags & DRM_MODE_FLAG_CSYNC)
- ? RADEON_CRTC_CSYNC_EN
- : 0)
- | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
- ? RADEON_CRTC_INTERLACE_EN
- : 0));
-
- state->crtc_ext_cntl |= (RADEON_XCRT_CNT_EN|
- RADEON_CRTC_VSYNC_DIS |
- RADEON_CRTC_HSYNC_DIS |
- RADEON_CRTC_DISPLAY_DIS);
-
- state->disp_merge_cntl = RADEON_READ(RADEON_DISP_MERGE_CNTL);
- state->disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
-
- state->crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
- | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff)
- << 16));
+ crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN
+ | RADEON_CRTC_EN
+ | (format << 8)
+ | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
+ ? RADEON_CRTC_DBL_SCAN_EN
+ : 0)
+ | ((mode->flags & DRM_MODE_FLAG_CSYNC)
+ ? RADEON_CRTC_CSYNC_EN
+ : 0)
+ | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
+ ? RADEON_CRTC_INTERLACE_EN
+ : 0));
+
+ crtc_ext_cntl = RADEON_READ(RADEON_CRTC_EXT_CNTL);
+ crtc_ext_cntl |= (RADEON_XCRT_CNT_EN|
+ RADEON_CRTC_VSYNC_DIS |
+ RADEON_CRTC_HSYNC_DIS |
+ RADEON_CRTC_DISPLAY_DIS);
+
+ disp_merge_cntl = RADEON_READ(RADEON_DISP_MERGE_CNTL);
+ disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
+
+ crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
+ | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
- if (!hsync_wid) hsync_wid = 1;
+ if (!hsync_wid)
+ hsync_wid = 1;
hsync_start = mode->crtc_hsync_start - 8;
- state->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
- | ((hsync_wid & 0x3f) << 16)
- | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
- ? RADEON_CRTC_H_SYNC_POL
- : 0));
+ crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
+ | ((hsync_wid & 0x3f) << 16)
+ | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
+ ? RADEON_CRTC_H_SYNC_POL
+ : 0));
/* This works for double scan mode. */
- state->crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
- | ((mode->crtc_vdisplay - 1) << 16));
+ crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
+ | ((mode->crtc_vdisplay - 1) << 16));
vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
- if (!vsync_wid) vsync_wid = 1;
+ if (!vsync_wid)
+ vsync_wid = 1;
- state->crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
- | ((vsync_wid & 0x1f) << 16)
- | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
- ? RADEON_CRTC_V_SYNC_POL
- : 0));
+ crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
+ | ((vsync_wid & 0x1f) << 16)
+ | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
+ ? RADEON_CRTC_V_SYNC_POL
+ : 0));
- state->crtc_pitch = (((crtc->fb->pitch * crtc->fb->bits_per_pixel) +
- ((crtc->fb->bits_per_pixel * 8) -1)) /
- (crtc->fb->bits_per_pixel * 8));
- state->crtc_pitch |= state->crtc_pitch << 16;
+ crtc_pitch = (((crtc->fb->pitch * crtc->fb->bits_per_pixel) +
+ ((crtc->fb->bits_per_pixel * 8) -1)) /
+ (crtc->fb->bits_per_pixel * 8));
+ crtc_pitch |= crtc_pitch << 16;
/* TODO -> Dell Server */
if (0) {
+ uint32_t disp_hw_debug = RADEON_READ(RADEON_DISP_HW_DEBUG);
+ uint32_t tv_dac_cntl = RADEON_READ(RADEON_TV_DAC_CNTL);
+ uint32_t dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2);
+ uint32_t crtc2_gen_cntl = RADEON_READ(RADEON_CRTC2_GEN_CNTL);
// state->dac2_cntl = info->StatedReg->dac2_cntl;
// state->tv_dac_cntl = info->StatedReg->tv_dac_cntl;
// state->crtc2_gen_cntl = info->StatedReg->crtc2_gen_cntl;
/* For CRT on DAC2, don't turn it on if BIOS didn't
enable it, even it's detected.
*/
- state->disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
- state->tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
- state->tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
+ disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
+ tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
+ tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
+
+ RADEON_WRITE(RADEON_TV_DAC_CNTL, tv_dac_cntl);
+ RADEON_WRITE(RADEON_DISP_HW_DEBUG, disp_hw_debug);
+ RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
+ RADEON_WRITE(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
}
+ RADEON_WRITE(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl |
+ RADEON_CRTC_DISP_REQ_EN_B);
+
+ RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl,
+ RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_DISPLAY_DIS);
+
+ RADEON_WRITE(RADEON_CRTC_H_TOTAL_DISP, crtc_h_total_disp);
+ RADEON_WRITE(RADEON_CRTC_H_SYNC_STRT_WID, crtc_h_sync_strt_wid);
+ RADEON_WRITE(RADEON_CRTC_V_TOTAL_DISP, crtc_v_total_disp);
+ RADEON_WRITE(RADEON_CRTC_V_SYNC_STRT_WID, crtc_v_sync_strt_wid);
+
+ RADEON_WRITE(RADEON_CRTC_PITCH, crtc_pitch);
+ RADEON_WRITE(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
+
+ RADEON_WRITE(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
+
return true;
}
-static void radeon_init_pll_registers(struct drm_crtc *crtc, struct radeon_legacy_state *state,
- struct drm_display_mode *mode, int flags)
+static void radeon_set_pll1(struct drm_crtc *crtc, struct drm_display_mode *mode, int flags)
{
- struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+ struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
struct drm_device *dev = crtc->dev;
struct drm_radeon_private *dev_priv = dev->dev_private;
uint32_t feedback_div = 0;
uint32_t reference_div = 0;
uint32_t post_divider = 0;
uint32_t freq = 0;
+ uint8_t pll_gain;
+ /* PLL registers */
+ uint32_t ppll_ref_div;
+ uint32_t ppll_div_3;
+ uint32_t htotal_cntl;
+ uint32_t vclk_ecp_cntl;
+
struct radeon_pll *pll = &dev_priv->mode_info.pll;
+
struct {
int divider;
int bitvalue;
{ 12, 7 }, /* VCLK_SRC/12 */
{ 0, 0 }
};
-
+
#if 0 // TODO
if ((flags & RADEON_PLL_USE_BIOS_DIVS) && info->UseBiosDividers) {
- state->ppll_ref_div = info->RefDivider;
- state->ppll_div_3 = info->FeedbackDivider | (info->PostDivider << 16);
- state->htotal_cntl = 0;
+ ppll_ref_div = info->RefDivider;
+ ppll_div_3 = info->FeedbackDivider | (info->PostDivider << 16);
+ htotal_cntl = 0;
return;
}
#endif
}
if (!post_div->divider) {
- state->pll_output_freq = freq;
post_div = &post_divs[0];
}
-
- state->dot_clock_freq = freq;
- state->feedback_div = feedback_div;
- state->reference_div = reference_div;
- state->post_div = post_divider;
- DRM_DEBUG("dc=%u, of=%u, fd=%d, rd=%d, pd=%d\n",
- (unsigned)state->dot_clock_freq,
- (unsigned)state->pll_output_freq,
- state->feedback_div,
- state->reference_div,
- state->post_div);
+ DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
+ (unsigned)freq,
+ feedback_div,
+ reference_div,
+ post_divider);
- state->ppll_ref_div = state->reference_div;
+ ppll_ref_div = reference_div;
#if defined(__powerpc__) && (0) /* TODO */
/* apparently programming this otherwise causes a hang??? */
state->ppll_div_3 = 0x000600ad;
else
#endif
- state->ppll_div_3 = (state->feedback_div | (post_div->bitvalue << 16));
-
- state->htotal_cntl = mode->htotal & 0x7;
+ ppll_div_3 = (feedback_div | (post_div->bitvalue << 16));
+
+ htotal_cntl = mode->htotal & 0x7;
+
+ vclk_ecp_cntl = (RADEON_READ_PLL(dev_priv, RADEON_VCLK_ECP_CNTL) &
+ ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK;
+
+ pll_gain = radeon_compute_pll_gain(dev_priv->mode_info.pll.reference_freq,
+ ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
+ ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK);
+
+ if (dev_priv->flags & RADEON_IS_MOBILITY) {
+ /* A temporal workaround for the occational blanking on certain laptop panels.
+ This appears to related to the PLL divider registers (fail to lock?).
+ It occurs even when all dividers are the same with their old settings.
+ In this case we really don't need to fiddle with PLL registers.
+ By doing this we can avoid the blanking problem with some panels.
+ */
+ if ((ppll_ref_div == (RADEON_READ_PLL(dev_priv, RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
+ (ppll_div_3 == (RADEON_READ_PLL(dev_priv, RADEON_PPLL_DIV_3) &
+ (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
+ RADEON_WRITE_P(RADEON_CLOCK_CNTL_INDEX,
+ RADEON_PLL_DIV_SEL,
+ ~(RADEON_PLL_DIV_SEL));
+ radeon_pll_errata_after_index(dev_priv);
+ return;
+ }
+ }
+
+ RADEON_WRITE_PLL_P(dev_priv, RADEON_VCLK_ECP_CNTL,
+ RADEON_VCLK_SRC_SEL_CPUCLK,
+ ~(RADEON_VCLK_SRC_SEL_MASK));
+ RADEON_WRITE_PLL_P(dev_priv,
+ RADEON_PPLL_CNTL,
+ RADEON_PPLL_RESET
+ | RADEON_PPLL_ATOMIC_UPDATE_EN
+ | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
+ | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
+ ~(RADEON_PPLL_RESET
+ | RADEON_PPLL_ATOMIC_UPDATE_EN
+ | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
+ | RADEON_PPLL_PVG_MASK));
+
+ RADEON_WRITE_P(RADEON_CLOCK_CNTL_INDEX,
+ RADEON_PLL_DIV_SEL,
+ ~(RADEON_PLL_DIV_SEL));
+ radeon_pll_errata_after_index(dev_priv);
+
+ if (radeon_is_r300(dev_priv) ||
+ (dev_priv->chip_family == CHIP_RS300) ||
+ (dev_priv->chip_family == CHIP_RS400) ||
+ (dev_priv->chip_family == CHIP_RS480)) {
+ if (ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
+ /* When restoring console mode, use saved PPLL_REF_DIV
+ * setting.
+ */
+ RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
+ ppll_ref_div,
+ 0);
+ } else {
+ /* R300 uses ref_div_acc field as real ref divider */
+ RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
+ (ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
+ ~R300_PPLL_REF_DIV_ACC_MASK);
+ }
+ } else {
+ RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
+ ppll_ref_div,
+ ~RADEON_PPLL_REF_DIV_MASK);
+ }
+
+ RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_DIV_3,
+ ppll_div_3,
+ ~RADEON_PPLL_FB3_DIV_MASK);
+
+ RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_DIV_3,
+ ppll_div_3,
+ ~RADEON_PPLL_POST3_DIV_MASK);
+
+ radeon_pll_write_update(dev);
+ radeon_pll_wait_for_read_update_complete(dev);
+
+ RADEON_WRITE_PLL(dev_priv, RADEON_HTOTAL_CNTL, htotal_cntl);
+
+ RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_CNTL,
+ 0,
+ ~(RADEON_PPLL_RESET
+ | RADEON_PPLL_SLEEP
+ | RADEON_PPLL_ATOMIC_UPDATE_EN
+ | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
+
+ DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
+ ppll_ref_div,
+ ppll_div_3,
+ (unsigned)htotal_cntl,
+ RADEON_READ_PLL(dev_priv, RADEON_PPLL_CNTL));
+ DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n",
+ ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
+ ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK,
+ (ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16);
+
+ mdelay(50); /* Let the clock to lock */
+
+ RADEON_WRITE_PLL_P(dev_priv, RADEON_VCLK_ECP_CNTL,
+ RADEON_VCLK_SRC_SEL_PPLLCLK,
+ ~(RADEON_VCLK_SRC_SEL_MASK));
+
+ /*RADEON_WRITE_PLL(dev_priv, RADEON_VCLK_ECP_CNTL, state->vclk_ecp_cntl);*/
+
+}
+
+static bool radeon_set_crtc2_base(struct drm_crtc *crtc, int x, int y)
+{
+ struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+ struct drm_device *dev = crtc->dev;
+ struct drm_radeon_private *dev_priv = dev->dev_private;
+ struct radeon_framebuffer *radeon_fb;
+ struct drm_radeon_gem_object *obj_priv;
+ uint32_t crtc2_offset, crtc2_offset_cntl, crtc2_tile_x0_y0 = 0;
+ uint32_t base;
+
+ radeon_fb = to_radeon_framebuffer(crtc->fb);
+
+ obj_priv = radeon_fb->obj->driver_private;
+
+ crtc2_offset = obj_priv->bo->offset;
+
+ crtc2_offset_cntl = 0;
+
+ /* TODO tiling */
+ if (0) {
+ if (radeon_is_r300(dev_priv))
+ crtc2_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
+ R300_CRTC_MICRO_TILE_BUFFER_DIS |
+ R300_CRTC_MACRO_TILE_EN);
+ else
+ crtc2_offset_cntl |= RADEON_CRTC_TILE_EN;
+ } else {
+ if (radeon_is_r300(dev_priv))
+ crtc2_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
+ R300_CRTC_MICRO_TILE_BUFFER_DIS |
+ R300_CRTC_MACRO_TILE_EN);
+ else
+ crtc2_offset_cntl &= ~RADEON_CRTC_TILE_EN;
+ }
+
+ base = obj_priv->bo->offset;
+
+ /* TODO more tiling */
+ if (0) {
+ if (radeon_is_r300(dev_priv)) {
+ crtc2_tile_x0_y0 = x | (y << 16);
+ base &= ~0x7ff;
+ } else {
+ int byteshift = crtc->fb->bits_per_pixel >> 4;
+ int tile_addr = (((y >> 3) * crtc->fb->width + x) >> (8 - byteshift)) << 11;
+ base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
+ crtc2_offset_cntl |= (y % 16);
+ }
+ } else {
+ int offset = y * crtc->fb->pitch + x;
+ switch (crtc->fb->bits_per_pixel) {
+ case 15:
+ case 16:
+ offset *= 2;
+ break;
+ case 24:
+ offset *= 3;
+ break;
+ case 32:
+ offset *= 4;
+ break;
+ default:
+ return false;
+ }
+ base += offset;
+ }
+
+ base &= ~7;
+
+ /* update sarea TODO */
+
+ crtc2_offset = base;
+
+ if (radeon_is_r300(dev_priv))
+ RADEON_WRITE(R300_CRTC2_TILE_X0_Y0, crtc2_tile_x0_y0);
+ RADEON_WRITE(RADEON_CRTC2_OFFSET_CNTL, crtc2_offset_cntl);
+ RADEON_WRITE(RADEON_CRTC2_OFFSET, crtc2_offset);
+
+ return true;
+}
+
+static bool radeon_set_crtc2_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
+{
+ struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+ struct drm_device *dev = crtc->dev;
+ struct drm_radeon_private *dev_priv = dev->dev_private;
+ int format;
+ int hsync_start;
+ int hsync_wid;
+ int vsync_wid;
+ uint32_t crtc2_gen_cntl;
+ uint32_t crtc2_h_total_disp;
+ uint32_t crtc2_h_sync_strt_wid;
+ uint32_t crtc2_v_total_disp;
+ uint32_t crtc2_v_sync_strt_wid;
+ uint32_t crtc2_pitch;
+ uint32_t disp2_merge_cntl;
+ uint32_t fp_h2_sync_strt_wid;
+ uint32_t fp_v2_sync_strt_wid;
+
+ switch (crtc->fb->depth) {
+
+ case 15: /* 555 */
+ format = 3;
+ break;
+ case 16: /* 565 */
+ format = 4;
+ break;
+ case 24: /* RGB */
+ format = 5;
+ break;
+ case 32: /* xRGB */
+ format = 6;
+ break;
+ default:
+ return false;
+ }
+
+ crtc2_h_total_disp =
+ ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
+ | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
+
+ hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
+ if (!hsync_wid)
+ hsync_wid = 1;
+ hsync_start = mode->crtc_hsync_start - 8;
+
+ crtc2_h_sync_strt_wid = ((hsync_start & 0x1fff)
+ | ((hsync_wid & 0x3f) << 16)
+ | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
+ ? RADEON_CRTC_H_SYNC_POL
+ : 0));
+
+ /* This works for double scan mode. */
+ crtc2_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
+ | ((mode->crtc_vdisplay - 1) << 16));
+
+ vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
+ if (!vsync_wid)
+ vsync_wid = 1;
+
+ crtc2_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
+ | ((vsync_wid & 0x1f) << 16)
+ | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
+ ? RADEON_CRTC2_V_SYNC_POL
+ : 0));
+
+ crtc2_pitch = (((crtc->fb->pitch * crtc->fb->bits_per_pixel) +
+ ((crtc->fb->bits_per_pixel * 8) -1)) /
+ (crtc->fb->bits_per_pixel * 8));
+ crtc2_pitch |= crtc2_pitch << 16;
+
+ /* check to see if TV DAC is enabled for another crtc and keep it enabled */
+ if (RADEON_READ(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_CRT2_ON)
+ crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON;
+ else
+ crtc2_gen_cntl = 0;
+
+ crtc2_gen_cntl |= (RADEON_CRTC2_EN
+ | (format << 8)
+ | RADEON_CRTC2_VSYNC_DIS
+ | RADEON_CRTC2_HSYNC_DIS
+ | RADEON_CRTC2_DISP_DIS
+ | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
+ ? RADEON_CRTC2_DBL_SCAN_EN
+ : 0)
+ | ((mode->flags & DRM_MODE_FLAG_CSYNC)
+ ? RADEON_CRTC2_CSYNC_EN
+ : 0)
+ | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
+ ? RADEON_CRTC2_INTERLACE_EN
+ : 0));
+
+ disp2_merge_cntl = RADEON_READ(RADEON_DISP2_MERGE_CNTL);
+ disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
+
+ fp_h2_sync_strt_wid = crtc2_h_sync_strt_wid;
+ fp_v2_sync_strt_wid = crtc2_v_sync_strt_wid;
+
+ RADEON_WRITE(RADEON_CRTC2_GEN_CNTL,
+ crtc2_gen_cntl | RADEON_CRTC2_VSYNC_DIS |
+ RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_DIS |
+ RADEON_CRTC2_DISP_REQ_EN_B);
+
+ RADEON_WRITE(RADEON_CRTC2_H_TOTAL_DISP, crtc2_h_total_disp);
+ RADEON_WRITE(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid);
+ RADEON_WRITE(RADEON_CRTC2_V_TOTAL_DISP, crtc2_v_total_disp);
+ RADEON_WRITE(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid);
+
+ RADEON_WRITE(RADEON_FP_H2_SYNC_STRT_WID, fp_h2_sync_strt_wid);
+ RADEON_WRITE(RADEON_FP_V2_SYNC_STRT_WID, fp_v2_sync_strt_wid);
+
+ RADEON_WRITE(RADEON_CRTC2_PITCH, crtc2_pitch);
+ RADEON_WRITE(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
+
+ RADEON_WRITE(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
+
+ return true;
+
+}
+
+static void radeon_set_pll2(struct drm_crtc *crtc, struct drm_display_mode *mode, int flags)
+{
+ struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+ struct drm_device *dev = crtc->dev;
+ struct drm_radeon_private *dev_priv = dev->dev_private;
+ uint32_t feedback_div = 0;
+ uint32_t reference_div = 0;
+ uint32_t post_divider = 0;
+ uint32_t freq = 0;
+ uint8_t pll_gain;
+ /* PLL2 registers */
+ uint32_t p2pll_ref_div;
+ uint32_t p2pll_div_0;
+ uint32_t htotal_cntl2;
+ uint32_t pixclks_cntl;
+
+ struct radeon_pll *pll = &dev_priv->mode_info.pll;
+
+ struct {
+ int divider;
+ int bitvalue;
+ } *post_div, post_divs[] = {
+ /* From RAGE 128 VR/RAGE 128 GL Register
+ * Reference Manual (Technical Reference
+ * Manual P/N RRG-G04100-C Rev. 0.04), page
+ * 3-17 (PLL_DIV_[3:0]).
+ */
+ { 1, 0 }, /* VCLK_SRC */
+ { 2, 1 }, /* VCLK_SRC/2 */
+ { 4, 2 }, /* VCLK_SRC/4 */
+ { 8, 3 }, /* VCLK_SRC/8 */
+ { 3, 4 }, /* VCLK_SRC/3 */
+ { 6, 6 }, /* VCLK_SRC/6 */
+ { 12, 7 }, /* VCLK_SRC/12 */
+ { 0, 0 }
+ };
+
+#if 0
+ if ((flags & RADEON_PLL_USE_BIOS_DIVS) && info->UseBiosDividers) {
+ p2pll_ref_div = info->RefDivider;
+ p2pll_div_0 = info->FeedbackDivider | (info->PostDivider << 16);
+ htotal_cntl2 = 0;
+ return;
+ }
+#endif
- state->vclk_ecp_cntl = (RADEON_READ_PLL(dev_priv, RADEON_VCLK_ECP_CNTL) &
- ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK;
+ radeon_compute_pll(pll, mode->clock, &freq, &feedback_div, &reference_div, &post_divider, flags);
+
+ for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
+ if (post_div->divider == post_divider)
+ break;
+ }
+
+ if (!post_div->divider) {
+ post_div = &post_divs[0];
+ }
+
+ DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
+ (unsigned)freq,
+ feedback_div,
+ reference_div,
+ post_divider);
+
+ p2pll_ref_div = reference_div;
+
+ p2pll_div_0 = (feedback_div | (post_div->bitvalue << 16));
+
+ htotal_cntl2 = mode->htotal & 0x7;
+
+ pixclks_cntl = ((RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL) &
+ ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
+ RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
+
+ pll_gain = radeon_compute_pll_gain(dev_priv->mode_info.pll.reference_freq,
+ p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
+ p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK);
+
+
+ RADEON_WRITE_PLL_P(dev_priv, RADEON_PIXCLKS_CNTL,
+ RADEON_PIX2CLK_SRC_SEL_CPUCLK,
+ ~(RADEON_PIX2CLK_SRC_SEL_MASK));
+
+ RADEON_WRITE_PLL_P(dev_priv,
+ RADEON_P2PLL_CNTL,
+ RADEON_P2PLL_RESET
+ | RADEON_P2PLL_ATOMIC_UPDATE_EN
+ | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
+ ~(RADEON_P2PLL_RESET
+ | RADEON_P2PLL_ATOMIC_UPDATE_EN
+ | RADEON_P2PLL_PVG_MASK));
+
+
+ RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_REF_DIV,
+ p2pll_ref_div,
+ ~RADEON_P2PLL_REF_DIV_MASK);
+
+ RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_DIV_0,
+ p2pll_div_0,
+ ~RADEON_P2PLL_FB0_DIV_MASK);
+
+ RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_DIV_0,
+ p2pll_div_0,
+ ~RADEON_P2PLL_POST0_DIV_MASK);
+
+ radeon_pll2_write_update(dev);
+ radeon_pll2_wait_for_read_update_complete(dev);
+
+ RADEON_WRITE_PLL(dev_priv, RADEON_HTOTAL2_CNTL, htotal_cntl2);
+
+ RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_CNTL,
+ 0,
+ ~(RADEON_P2PLL_RESET
+ | RADEON_P2PLL_SLEEP
+ | RADEON_P2PLL_ATOMIC_UPDATE_EN));
+
+ DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
+ (unsigned)p2pll_ref_div,
+ (unsigned)p2pll_div_0,
+ (unsigned)htotal_cntl2,
+ RADEON_READ_PLL(dev_priv, RADEON_P2PLL_CNTL));
+ DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n",
+ (unsigned)p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
+ (unsigned)p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK,
+ (unsigned)((p2pll_div_0 &
+ RADEON_P2PLL_POST0_DIV_MASK) >>16));
+
+ mdelay(50); /* Let the clock to lock */
+
+ RADEON_WRITE_PLL_P(dev_priv, RADEON_PIXCLKS_CNTL,
+ RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
+ ~(RADEON_PIX2CLK_SRC_SEL_MASK));
+
+ RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, pixclks_cntl);
}
struct drm_display_mode *adjusted_mode,
int x, int y)
{
- struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+ struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
struct drm_device *dev = crtc->dev;
struct drm_radeon_private *dev_priv = dev->dev_private;
struct drm_encoder *encoder;
}
}
+ /* TODO TV */
+
switch(radeon_crtc->crtc_id) {
case 0:
- radeon_init_crtc_registers(crtc, &dev_priv->mode_info.legacy_state, adjusted_mode);
- radeon_init_crtc_base(crtc, &dev_priv->mode_info.legacy_state, crtc->x, crtc->y);
-// dot_clock = adjusted_mode->clock / 1000;
-
- // if (dot_clock)
- radeon_init_pll_registers(crtc, &dev_priv->mode_info.legacy_state, adjusted_mode,
- pll_flags);
+ radeon_set_crtc1_timing(crtc, adjusted_mode);
+ radeon_set_pll1(crtc, adjusted_mode, pll_flags);
break;
case 1:
+ radeon_set_crtc2_timing(crtc, adjusted_mode);
+ radeon_set_pll2(crtc, adjusted_mode, pll_flags);
break;
}
+}
- /* TODO TV */
+void radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y)
+{
+ struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
- switch (radeon_crtc->crtc_id) {
+ switch(radeon_crtc->crtc_id) {
case 0:
- radeon_restore_crtc_registers(dev, &dev_priv->mode_info.legacy_state);
- radeon_restore_pll_registers(dev, &dev_priv->mode_info.legacy_state);
+ radeon_set_crtc1_base(crtc, x, y);
break;
case 1:
- radeon_restore_crtc2_registers(dev, &dev_priv->mode_info.legacy_state);
- radeon_restore_pll2_registers(dev, &dev_priv->mode_info.legacy_state);
+ radeon_set_crtc2_base(crtc, x, y);
break;
- }
-
-}
-void radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y)
-{
+ }
}
static void radeon_crtc_prepare(struct drm_crtc *crtc)
{
+ radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
}
static void radeon_crtc_commit(struct drm_crtc *crtc)
{
+ radeon_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
}
static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
#include "radeon_drv.h"
-void radeon_restore_dac_registers(struct drm_device *dev, struct radeon_legacy_state *state)
-{
- struct drm_radeon_private *dev_priv = dev->dev_private;
-
- if (radeon_is_r300(dev_priv))
- RADEON_WRITE_P(RADEON_GPIOPAD_A, state->gpiopad_a, ~1);
-
- RADEON_WRITE_P(RADEON_DAC_CNTL,
- state->dac_cntl,
- RADEON_DAC_RANGE_CNTL |
- RADEON_DAC_BLANKING);
-
- RADEON_WRITE(RADEON_DAC_CNTL2, state->dac2_cntl);
-
- if ((dev_priv->chip_family != CHIP_R100) &&
- (dev_priv->chip_family != CHIP_R200))
- RADEON_WRITE (RADEON_TV_DAC_CNTL, state->tv_dac_cntl);
-
- RADEON_WRITE(RADEON_DISP_OUTPUT_CNTL, state->disp_output_cntl);
-
- if ((dev_priv->chip_family == CHIP_R200) ||
- radeon_is_r300(dev_priv)) {
- RADEON_WRITE(RADEON_DISP_TV_OUT_CNTL, state->disp_tv_out_cntl);
- } else {
- RADEON_WRITE(RADEON_DISP_HW_DEBUG, state->disp_hw_debug);
- }
-
- RADEON_WRITE(RADEON_DAC_MACRO_CNTL, state->dac_macro_cntl);
-
- /* R200 DAC connected via DVO */
- if (dev_priv->chip_family == CHIP_R200)
- RADEON_WRITE(RADEON_FP2_GEN_CNTL, state->fp2_gen_cntl);
-}
-
-
-/* Write TMDS registers */
-void radeon_restore_fp_registers(struct drm_device *dev, struct radeon_legacy_state *state)
+static void radeon_legacy_rmx_mode_set(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
{
+ struct drm_device *dev = encoder->dev;
struct drm_radeon_private *dev_priv = dev->dev_private;
-
- RADEON_WRITE(RADEON_TMDS_PLL_CNTL, state->tmds_pll_cntl);
- RADEON_WRITE(RADEON_TMDS_TRANSMITTER_CNTL,state->tmds_transmitter_cntl);
- RADEON_WRITE(RADEON_FP_GEN_CNTL, state->fp_gen_cntl);
-
- if ((dev_priv->chip_family == CHIP_RS400) ||
- (dev_priv->chip_family == CHIP_RS480)) {
- RADEON_WRITE(RS400_FP_2ND_GEN_CNTL, state->fp_2nd_gen_cntl);
- /*RADEON_WRITE(RS400_TMDS2_CNTL, state->tmds2_cntl);*/
- RADEON_WRITE(RS400_TMDS2_TRANSMITTER_CNTL, state->tmds2_transmitter_cntl);
+ struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ int xres = mode->hdisplay;
+ int yres = mode->vdisplay;
+ bool hscale = true, vscale = true;
+ int hsync_wid;
+ int vsync_wid;
+ int hsync_start;
+ uint32_t scale, inc;
+ uint32_t fp_horz_stretch, fp_vert_stretch, crtc_more_cntl, fp_horz_vert_active;
+ uint32_t fp_h_sync_strt_wid, fp_v_sync_strt_wid, fp_crtc_h_total_disp, fp_crtc_v_total_disp;
+
+
+ fp_vert_stretch = RADEON_READ(RADEON_FP_VERT_STRETCH) &
+ (RADEON_VERT_STRETCH_RESERVED |
+ RADEON_VERT_AUTO_RATIO_INC);
+ fp_horz_stretch = RADEON_READ(RADEON_FP_HORZ_STRETCH) &
+ (RADEON_HORZ_FP_LOOP_STRETCH |
+ RADEON_HORZ_AUTO_RATIO_INC);
+
+ crtc_more_cntl = 0;
+ if ((dev_priv->chip_family == CHIP_RS100) ||
+ (dev_priv->chip_family == CHIP_RS200)) {
+ /* This is to workaround the asic bug for RMX, some versions
+ of BIOS dosen't have this register initialized correctly. */
+ crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
}
- /* old AIW Radeon has some BIOS initialization problem
- * with display buffer underflow, only occurs to DFP
- */
- if (dev_priv->flags & RADEON_SINGLE_CRTC)
- RADEON_WRITE(RADEON_GRPH_BUFFER_CNTL,
- RADEON_READ(RADEON_GRPH_BUFFER_CNTL) & ~0x7f0000);
-}
+ fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
+ | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
-/* Write FP2 registers */
-void radeon_restore_fp2_registers(struct drm_device *dev, struct radeon_legacy_state *state)
-{
- struct drm_radeon_private *dev_priv = dev->dev_private;
- RADEON_WRITE(RADEON_FP2_GEN_CNTL, state->fp2_gen_cntl);
+ hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
+ if (!hsync_wid)
+ hsync_wid = 1;
+ hsync_start = mode->crtc_hsync_start - 8;
- if ((dev_priv->chip_family == CHIP_RS400) ||
- (dev_priv->chip_family == CHIP_RS480))
- RADEON_WRITE(RS400_FP2_2_GEN_CNTL, state->fp2_2_gen_cntl);
-}
+ fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
+ | ((hsync_wid & 0x3f) << 16)
+ | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
+ ? RADEON_CRTC_H_SYNC_POL
+ : 0));
-/* Write RMX registers */
-void radeon_state_rmx_registers(struct drm_device *dev, struct radeon_legacy_state *state)
-{
- struct drm_radeon_private *dev_priv = dev->dev_private;
- RADEON_WRITE(RADEON_FP_HORZ_STRETCH, state->fp_horz_stretch);
- RADEON_WRITE(RADEON_FP_VERT_STRETCH, state->fp_vert_stretch);
- RADEON_WRITE(RADEON_CRTC_MORE_CNTL, state->crtc_more_cntl);
- RADEON_WRITE(RADEON_FP_HORZ_VERT_ACTIVE, state->fp_horz_vert_active);
- RADEON_WRITE(RADEON_FP_H_SYNC_STRT_WID, state->fp_h_sync_strt_wid);
- RADEON_WRITE(RADEON_FP_V_SYNC_STRT_WID, state->fp_v_sync_strt_wid);
- RADEON_WRITE(RADEON_FP_CRTC_H_TOTAL_DISP, state->fp_crtc_h_total_disp);
- RADEON_WRITE(RADEON_FP_CRTC_V_TOTAL_DISP, state->fp_crtc_v_total_disp);
+ fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
+ | ((mode->crtc_vdisplay - 1) << 16));
-}
+ vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
+ if (!vsync_wid)
+ vsync_wid = 1;
-/* Write LVDS registers */
-void radeon_restore_lvds_registers(struct drm_device *dev, struct radeon_legacy_state *state)
-{
- struct drm_radeon_private *dev_priv = dev->dev_private;
+ fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
+ | ((vsync_wid & 0x1f) << 16)
+ | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
+ ? RADEON_CRTC_V_SYNC_POL
+ : 0));
- if (dev_priv->flags & RADEON_IS_MOBILITY) {
- RADEON_WRITE(RADEON_LVDS_GEN_CNTL, state->lvds_gen_cntl);
- /*RADEON_WRITE(RADEON_LVDS_PLL_CNTL, state->lvds_pll_cntl);*/
+ fp_horz_vert_active = 0;
- if (dev_priv->chip_family == CHIP_RV410) {
- RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, 0);
- }
+ if (radeon_encoder->panel_xres == 0 ||
+ radeon_encoder->panel_yres == 0) {
+ hscale = false;
+ vscale = false;
+ } else {
+ if (xres > radeon_encoder->panel_xres)
+ xres = radeon_encoder->panel_xres;
+ if (yres > radeon_encoder->panel_yres)
+ yres = radeon_encoder->panel_yres;
+
+ if (xres == radeon_encoder->panel_xres)
+ hscale = false;
+ if (yres == radeon_encoder->panel_yres)
+ vscale = false;
}
-}
-
-static void radeon_init_fp_registers(struct drm_encoder *encoder, struct drm_display_mode *mode,
- bool is_primary)
-{
-
-
-}
-
-static void radeon_init_dac_registers(struct drm_encoder *encoder, struct radeon_legacy_state *state,
- struct drm_display_mode *mode, bool is_primary)
-{
- struct drm_device *dev = encoder->dev;
- struct drm_radeon_private *dev_priv = dev->dev_private;
-
- if (is_primary) {
- if (dev_priv->chip_family == CHIP_R200 || radeon_is_r300(dev_priv)) {
- state->disp_output_cntl = RADEON_READ(RADEON_DISP_OUTPUT_CNTL &
- ~RADEON_DISP_DAC_SOURCE_MASK);
- } else {
- state->dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL);
+ if (radeon_encoder->flags & RADEON_USE_RMX) {
+ if (radeon_encoder->rmx_type != RMX_CENTER) {
+ if (!hscale)
+ fp_horz_stretch |= ((xres/8-1) << 16);
+ else {
+ inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
+ scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
+ / radeon_encoder->panel_xres + 1;
+ fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
+ RADEON_HORZ_STRETCH_BLEND |
+ RADEON_HORZ_STRETCH_ENABLE |
+ ((radeon_encoder->panel_xres/8-1) << 16));
+ }
+
+ if (!vscale)
+ fp_vert_stretch |= ((yres-1) << 12);
+ else {
+ inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
+ scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
+ / radeon_encoder->panel_yres + 1;
+ fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
+ RADEON_VERT_STRETCH_ENABLE |
+ RADEON_VERT_STRETCH_BLEND |
+ ((radeon_encoder->panel_yres-1) << 12));
+ }
+ } else if (radeon_encoder->rmx_type == RMX_CENTER) {
+ int blank_width;
+
+ fp_horz_stretch |= ((xres/8-1) << 16);
+ fp_vert_stretch |= ((yres-1) << 12);
+
+ crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
+ RADEON_CRTC_AUTO_VERT_CENTER_EN);
+
+ blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
+ if (blank_width > 110)
+ blank_width = 110;
+
+ fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
+ | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
+
+ hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
+ if (!hsync_wid)
+ hsync_wid = 1;
+
+ fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
+ | ((hsync_wid & 0x3f) << 16)
+ | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
+ ? RADEON_CRTC_H_SYNC_POL
+ : 0));
+
+ fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
+ | ((mode->crtc_vdisplay - 1) << 16));
+
+ vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
+ if (!vsync_wid)
+ vsync_wid = 1;
+
+ fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
+ | ((vsync_wid & 0x1f) << 16)
+ | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
+ ? RADEON_CRTC_V_SYNC_POL
+ : 0)));
+
+ fp_horz_vert_active = (((radeon_encoder->panel_yres) & 0xfff) |
+ (((radeon_encoder->panel_xres / 8) & 0x1ff) << 16));
}
} else {
- if (dev_priv->chip_family == CHIP_R200 || radeon_is_r300(dev_priv)) {
- state->disp_output_cntl = RADEON_READ(RADEON_DISP_OUTPUT_CNTL &
- ~RADEON_DISP_DAC_SOURCE_MASK);
- state->disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
- } else {
- state->dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
- }
+ fp_horz_stretch |= ((xres/8-1) << 16);
+ fp_vert_stretch |= ((yres-1) << 12);
}
- state->dac_cntl = (RADEON_DAC_MASK_ALL |
- RADEON_DAC_VGA_ADR_EN |
- /* TODO 6-bits */
- RADEON_DAC_8BIT_EN);
- state->dac_macro_cntl = RADEON_READ(RADEON_DAC_MACRO_CNTL);
+ RADEON_WRITE(RADEON_FP_HORZ_STRETCH, fp_horz_stretch);
+ RADEON_WRITE(RADEON_FP_VERT_STRETCH, fp_vert_stretch);
+ RADEON_WRITE(RADEON_CRTC_MORE_CNTL, crtc_more_cntl);
+ RADEON_WRITE(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active);
+ RADEON_WRITE(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid);
+ RADEON_WRITE(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid);
+ RADEON_WRITE(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
+ RADEON_WRITE(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
+
}
static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
{
struct drm_device *dev = encoder->dev;
+ struct drm_radeon_private *dev_priv = dev->dev_private;
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
+
+ switch(mode) {
+ case DRM_MODE_DPMS_ON:
+ disp_pwr_man = RADEON_READ(RADEON_DISP_PWR_MAN);
+ disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
+ RADEON_WRITE(RADEON_DISP_PWR_MAN, disp_pwr_man);
+ lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
+ RADEON_WRITE(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
+ udelay(1000);
+ lvds_pll_cntl = RADEON_READ(RADEON_LVDS_PLL_CNTL);
+ lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
+ RADEON_WRITE(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
+ lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
+ lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+ lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
+ udelay(radeon_encoder->panel_pwr_delay * 1000);
+ RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
+ break;
+ case DRM_MODE_DPMS_STANDBY:
+ case DRM_MODE_DPMS_SUSPEND:
+ case DRM_MODE_DPMS_OFF:
+ pixclks_cntl = RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL);
+ RADEON_WRITE_PLL_P(dev_priv, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
+ lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
+ lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
+ lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+ RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
+ RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, pixclks_cntl);
+ break;
+ }
}
static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
}
static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
- struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
{
+ struct drm_device *dev = encoder->dev;
+ struct drm_radeon_private *dev_priv = dev->dev_private;
+ struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ uint32_t lvds_pll_cntl, lvds_gen_cntl;
+
+ if (radeon_crtc->crtc_id == 0)
+ radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
+
+ lvds_pll_cntl = RADEON_READ(RADEON_LVDS_PLL_CNTL);
+ lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
+ lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
+ lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
+ lvds_gen_cntl &= ~(RADEON_LVDS_ON |
+ RADEON_LVDS_BLON |
+ RADEON_LVDS_EN |
+ RADEON_LVDS_RST_FM);
+
+ if (radeon_is_r300(dev_priv))
+ lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
+
+ if (radeon_crtc->crtc_id == 0) {
+ if (radeon_is_r300(dev_priv)) {
+ if (radeon_encoder->flags & RADEON_USE_RMX)
+ lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
+ } else
+ lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
+ } else {
+ if (radeon_is_r300(dev_priv)) {
+ lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
+ } else
+ lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
+ }
+ RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
+ RADEON_WRITE(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
+ if (dev_priv->chip_family == CHIP_RV410)
+ RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, 0);
}
static bool radeon_legacy_lvds_mode_fixup(struct drm_encoder *encoder,
- struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
{
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
if (radeon_encoder->rmx_type != RMX_OFF)
radeon_rmx_mode_fixup(encoder, mode, adjusted_mode);
-
+
return true;
}
static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
{
+ struct drm_device *dev = encoder->dev;
+ struct drm_radeon_private *dev_priv = dev->dev_private;
+ uint32_t crtc_ext_cntl = RADEON_READ(RADEON_CRTC_EXT_CNTL);
+ uint32_t dac_cntl = RADEON_READ(RADEON_DAC_CNTL);
+ uint32_t dac_macro_cntl = RADEON_READ(RADEON_DAC_MACRO_CNTL);
+
+ switch(mode) {
+ case DRM_MODE_DPMS_ON:
+ crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
+ dac_cntl &= ~RADEON_DAC_PDWN;
+ dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
+ RADEON_DAC_PDWN_G |
+ RADEON_DAC_PDWN_B);
+ break;
+ case DRM_MODE_DPMS_STANDBY:
+ case DRM_MODE_DPMS_SUSPEND:
+ case DRM_MODE_DPMS_OFF:
+ crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
+ dac_cntl |= RADEON_DAC_PDWN;
+ dac_macro_cntl |= (RADEON_DAC_PDWN_R |
+ RADEON_DAC_PDWN_G |
+ RADEON_DAC_PDWN_B);
+ break;
+ }
+ RADEON_WRITE(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
+ RADEON_WRITE(RADEON_DAC_CNTL, dac_cntl);
+ RADEON_WRITE(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
}
}
static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
- struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
{
struct drm_device *dev = encoder->dev;
struct drm_radeon_private *dev_priv = dev->dev_private;
struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
- radeon_init_dac_registers(encoder, &dev_priv->mode_info.legacy_state, adjusted_mode,
- (radeon_crtc->crtc_id == 1));
+ uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
+
+ if (radeon_crtc->crtc_id == 0)
+ radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
+
+ if (radeon_crtc->crtc_id == 0) {
+ if (dev_priv->chip_family == CHIP_R200 || radeon_is_r300(dev_priv)) {
+ disp_output_cntl = RADEON_READ(RADEON_DISP_OUTPUT_CNTL) &
+ ~(RADEON_DISP_DAC_SOURCE_MASK);
+ RADEON_WRITE(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
+ } else {
+ dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL);
+ RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
+ }
+ } else {
+ if (dev_priv->chip_family == CHIP_R200 || radeon_is_r300(dev_priv)) {
+ disp_output_cntl = RADEON_READ(RADEON_DISP_OUTPUT_CNTL) &
+ ~(RADEON_DISP_DAC_SOURCE_MASK);
+ disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
+ RADEON_WRITE(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
+ } else {
+ dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
+ RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
+ }
+ }
+
+ dac_cntl = (RADEON_DAC_MASK_ALL |
+ RADEON_DAC_VGA_ADR_EN |
+ /* TODO 6-bits */
+ RADEON_DAC_8BIT_EN);
- radeon_restore_dac_registers(dev, &dev_priv->mode_info.legacy_state);
+ RADEON_WRITE_P(RADEON_DAC_CNTL,
+ dac_cntl,
+ RADEON_DAC_RANGE_CNTL |
+ RADEON_DAC_BLANKING);
+
+ dac_macro_cntl = RADEON_READ(RADEON_DAC_MACRO_CNTL);
+ RADEON_WRITE(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
}
static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
+ /* TODO get the primary dac vals from bios tables */
+ //radeon_combios_get_lvds_info(radeon_encoder);
+
return encoder;
}
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
-
+ return true;
}
static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
{
- /* dfp1 */
+ struct drm_device *dev = encoder->dev;
+ struct drm_radeon_private *dev_priv = dev->dev_private;
+ uint32_t fp_gen_cntl = RADEON_READ(RADEON_FP_GEN_CNTL);
+
+ switch(mode) {
+ case DRM_MODE_DPMS_ON:
+ fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ break;
+ case DRM_MODE_DPMS_STANDBY:
+ case DRM_MODE_DPMS_SUSPEND:
+ case DRM_MODE_DPMS_OFF:
+ fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ break;
+ }
+ RADEON_WRITE(RADEON_FP_GEN_CNTL, fp_gen_cntl);
}
static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
}
static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
- struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
{
-
+ struct drm_device *dev = encoder->dev;
+ struct drm_radeon_private *dev_priv = dev->dev_private;
+ struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
+ int i;
+
+ if (radeon_crtc->crtc_id == 0)
+ radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
+
+ tmp = tmds_pll_cntl = RADEON_READ(RADEON_TMDS_PLL_CNTL);
+ tmp &= 0xfffff;
+ if (dev_priv->chip_family == CHIP_RV280) {
+ /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
+ tmp ^= (1 << 22);
+ tmds_pll_cntl ^= (1 << 22);
+ }
+ for (i = 0; i < 4; i++) {
+ if (radeon_encoder->tmds_pll[i].freq == 0)
+ break;
+ if ((uint32_t)(mode->clock / 10) < radeon_encoder->tmds_pll[i].freq) {
+ tmp = radeon_encoder->tmds_pll[i].value ;
+ break;
+ }
+ }
+
+ if (radeon_is_r300(dev_priv) || (dev_priv->chip_family == CHIP_RV280)) {
+ if (tmp & 0xfff00000)
+ tmds_pll_cntl = tmp;
+ else {
+ tmds_pll_cntl &= 0xfff00000;
+ tmds_pll_cntl |= tmp;
+ }
+ } else
+ tmds_pll_cntl = tmp;
+
+ tmds_transmitter_cntl = RADEON_READ(RADEON_TMDS_TRANSMITTER_CNTL) &
+ ~(RADEON_TMDS_TRANSMITTER_PLLRST);
+
+ if (dev_priv->chip_family == CHIP_R200 ||
+ dev_priv->chip_family == CHIP_R100 ||
+ radeon_is_r300(dev_priv))
+ tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
+ else /* RV chips got this bit reversed */
+ tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
+
+ fp_gen_cntl = (RADEON_READ(RADEON_FP_GEN_CNTL) |
+ (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
+ RADEON_FP_CRTC_DONT_SHADOW_HEND));
+
+ fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+
+ if (1) // FIXME rgbBits == 8
+ fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
+ else
+ fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
+
+ if (radeon_crtc->crtc_id == 0) {
+ if (radeon_is_r300(dev_priv) || dev_priv->chip_family == CHIP_R200) {
+ fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
+ if (radeon_encoder->flags & RADEON_USE_RMX)
+ fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
+ else
+ fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
+ } else
+ fp_gen_cntl |= RADEON_FP_SEL_CRTC1;
+ } else {
+ if (radeon_is_r300(dev_priv) || dev_priv->chip_family == CHIP_R200) {
+ fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
+ fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
+ } else
+ fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
+ }
+
+ RADEON_WRITE(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
+ RADEON_WRITE(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
+ RADEON_WRITE(RADEON_FP_GEN_CNTL, fp_gen_cntl);
}
static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
radeon_combios_get_tmds_info(radeon_encoder);
return encoder;
}
+
+static bool radeon_legacy_tmds_ext_mode_fixup(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ return true;
+}
+
+static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
+{
+ struct drm_device *dev = encoder->dev;
+ struct drm_radeon_private *dev_priv = dev->dev_private;
+ uint32_t fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
+
+ switch(mode) {
+ case DRM_MODE_DPMS_ON:
+ fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
+ fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ break;
+ case DRM_MODE_DPMS_STANDBY:
+ case DRM_MODE_DPMS_SUSPEND:
+ case DRM_MODE_DPMS_OFF:
+ fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
+ fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ break;
+ }
+
+ RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
+}
+
+static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
+{
+ radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
+}
+
+static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
+{
+ radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
+}
+
+static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ struct drm_device *dev = encoder->dev;
+ struct drm_radeon_private *dev_priv = dev->dev_private;
+ struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ uint32_t fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
+
+ if (radeon_crtc->crtc_id == 0)
+ radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
+
+ if (1) // FIXME rgbBits == 8
+ fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
+ else
+ fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
+
+ fp2_gen_cntl &= ~(RADEON_FP2_ON |
+ RADEON_FP2_DVO_EN |
+ RADEON_FP2_DVO_RATE_SEL_SDR);
+
+ /* XXX: these are oem specific */
+ if (radeon_is_r300(dev_priv)) {
+ if ((dev->pdev->device == 0x4850) &&
+ (dev->pdev->subsystem_vendor == 0x1028) &&
+ (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
+ fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
+ else
+ fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
+
+ /*if (mode->clock > 165000)
+ fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
+ }
+
+ if (radeon_crtc->crtc_id == 0) {
+ if ((dev_priv->chip_family == CHIP_R200) || radeon_is_r300(dev_priv)) {
+ fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
+ if (radeon_encoder->flags & RADEON_USE_RMX)
+ fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
+ else
+ fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
+ } else
+ fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
+ } else {
+ if ((dev_priv->chip_family == CHIP_R200) || radeon_is_r300(dev_priv)) {
+ fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
+ fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
+ } else
+ fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
+ }
+
+ RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
+}
+
+static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
+ .dpms = radeon_legacy_tmds_ext_dpms,
+ .mode_fixup = radeon_legacy_tmds_ext_mode_fixup,
+ .prepare = radeon_legacy_tmds_ext_prepare,
+ .mode_set = radeon_legacy_tmds_ext_mode_set,
+ .commit = radeon_legacy_tmds_ext_commit,
+};
+
+
+static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
+ .destroy = radeon_enc_destroy,
+};
+
+struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index)
+{
+ struct drm_radeon_private *dev_priv = dev->dev_private;
+ struct radeon_mode_info *mode_info = &dev_priv->mode_info;
+ struct radeon_encoder *radeon_encoder;
+ struct drm_encoder *encoder;
+ radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
+ if (!radeon_encoder) {
+ return NULL;
+ }
+
+ encoder = &radeon_encoder->base;
+
+ encoder->possible_crtcs = 0x3;
+ encoder->possible_clones = 0;
+ drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs,
+ DRM_MODE_ENCODER_TMDS);
+
+ drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
+
+ //radeon_combios_get_tmds_info(radeon_encoder);
+ return encoder;
+}
+
+static bool radeon_legacy_tv_dac_mode_fixup(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ return true;
+}
+
+static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
+{
+ struct drm_device *dev = encoder->dev;
+ struct drm_radeon_private *dev_priv = dev->dev_private;
+ uint32_t fp2_gen_cntl, crtc2_gen_cntl, tv_master_cntl, tv_dac_cntl;
+
+ if (dev_priv->chip_family == CHIP_R200)
+ fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
+ else {
+ crtc2_gen_cntl = RADEON_READ(RADEON_CRTC2_GEN_CNTL);
+ // FIXME TV
+ //tv_master_cntl = RADEON_READ(RADEON_TV_MASTER_CNTL);
+ tv_dac_cntl = RADEON_READ(RADEON_TV_DAC_CNTL);
+ }
+
+ switch(mode) {
+ case DRM_MODE_DPMS_ON:
+ if (dev_priv->chip_family == CHIP_R200)
+ fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ else {
+ crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
+ //tv_master_cntl |= RADEON_TV_ON;
+ if (dev_priv->chip_family == CHIP_R420 ||
+ dev_priv->chip_family == CHIP_RV410)
+ tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
+ R420_TV_DAC_GDACPD |
+ R420_TV_DAC_BDACPD |
+ RADEON_TV_DAC_BGSLEEP);
+ else
+ tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
+ RADEON_TV_DAC_GDACPD |
+ RADEON_TV_DAC_BDACPD |
+ RADEON_TV_DAC_BGSLEEP);
+ }
+ break;
+ case DRM_MODE_DPMS_STANDBY:
+ case DRM_MODE_DPMS_SUSPEND:
+ case DRM_MODE_DPMS_OFF:
+ if (dev_priv->chip_family == CHIP_R200)
+ fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ else {
+ crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
+ //tv_master_cntl &= ~RADEON_TV_ON;
+ if (dev_priv->chip_family == CHIP_R420 ||
+ dev_priv->chip_family == CHIP_RV410)
+ tv_dac_cntl |= (R420_TV_DAC_RDACPD |
+ R420_TV_DAC_GDACPD |
+ R420_TV_DAC_BDACPD |
+ RADEON_TV_DAC_BGSLEEP);
+ else
+ tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
+ RADEON_TV_DAC_GDACPD |
+ RADEON_TV_DAC_BDACPD |
+ RADEON_TV_DAC_BGSLEEP);
+ }
+ break;
+ }
+
+ if (dev_priv->chip_family == CHIP_R200)
+ RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
+ else {
+ RADEON_WRITE(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
+ //RADEON_WRITE(RADEON_TV_MASTER_CNTL, tv_master_cntl);
+ RADEON_WRITE(RADEON_TV_DAC_CNTL, tv_dac_cntl);
+ }
+
+}
+
+static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
+{
+ radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
+}
+
+static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
+{
+ radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
+}
+
+static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ struct drm_device *dev = encoder->dev;
+ struct drm_radeon_private *dev_priv = dev->dev_private;
+ struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ uint32_t tv_dac_cntl, gpiopad_a, dac2_cntl, disp_output_cntl, fp2_gen_cntl;
+ uint32_t disp_hw_debug;
+
+ if (radeon_crtc->crtc_id == 0)
+ radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
+
+ if (dev_priv->chip_family != CHIP_R200) {
+ tv_dac_cntl = RADEON_READ(RADEON_TV_DAC_CNTL);
+ if (dev_priv->chip_family == CHIP_R420 ||
+ dev_priv->chip_family == CHIP_RV410) {
+ tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
+ RADEON_TV_DAC_BGADJ_MASK |
+ R420_TV_DAC_DACADJ_MASK |
+ R420_TV_DAC_RDACPD |
+ R420_TV_DAC_GDACPD |
+ R420_TV_DAC_GDACPD |
+ R420_TV_DAC_TVENABLE);
+ } else {
+ tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
+ RADEON_TV_DAC_BGADJ_MASK |
+ RADEON_TV_DAC_DACADJ_MASK |
+ RADEON_TV_DAC_RDACPD |
+ RADEON_TV_DAC_GDACPD |
+ RADEON_TV_DAC_GDACPD);
+ }
+
+ // FIXME TV
+ tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
+ RADEON_TV_DAC_NHOLD |
+ RADEON_TV_DAC_STD_PS2 /*|
+ radeon_encoder->ps2_tvdac_adj*/); // fixme, get from bios
+
+ RADEON_WRITE(RADEON_TV_DAC_CNTL, tv_dac_cntl);
+ }
+
+ if (radeon_is_r300(dev_priv)) {
+ gpiopad_a = RADEON_READ(RADEON_GPIOPAD_A) | 1;
+ disp_output_cntl = RADEON_READ(RADEON_DISP_OUTPUT_CNTL);
+ } else if (dev_priv->chip_family == CHIP_R200)
+ fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
+ else
+ disp_hw_debug = RADEON_READ(RADEON_DISP_HW_DEBUG);
+
+ dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
+
+ if (radeon_crtc->crtc_id == 0) {
+ if (radeon_is_r300(dev_priv)) {
+ disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
+ disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
+ } else if (dev_priv->chip_family == CHIP_R200) {
+ fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
+ RADEON_FP2_DVO_RATE_SEL_SDR);
+ } else
+ disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
+ } else {
+ if (radeon_is_r300(dev_priv)) {
+ disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
+ disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
+ } else if (dev_priv->chip_family == CHIP_R200) {
+ fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
+ RADEON_FP2_DVO_RATE_SEL_SDR);
+ fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
+ } else
+ disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
+ }
+
+ RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
+
+ if (radeon_is_r300(dev_priv)) {
+ RADEON_WRITE_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
+ RADEON_WRITE(RADEON_DISP_TV_OUT_CNTL, disp_output_cntl);
+ } else if (dev_priv->chip_family == CHIP_R200)
+ RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
+ else
+ RADEON_WRITE(RADEON_DISP_HW_DEBUG, disp_hw_debug);
+
+}
+
+static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
+ .dpms = radeon_legacy_tv_dac_dpms,
+ .mode_fixup = radeon_legacy_tv_dac_mode_fixup,
+ .prepare = radeon_legacy_tv_dac_prepare,
+ .mode_set = radeon_legacy_tv_dac_mode_set,
+ .commit = radeon_legacy_tv_dac_commit,
+};
+
+
+static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
+ .destroy = radeon_enc_destroy,
+};
+
+struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int has_tv)
+{
+ struct drm_radeon_private *dev_priv = dev->dev_private;
+ struct radeon_mode_info *mode_info = &dev_priv->mode_info;
+ struct radeon_encoder *radeon_encoder;
+ struct drm_encoder *encoder;
+ radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
+ if (!radeon_encoder) {
+ return NULL;
+ }
+
+ encoder = &radeon_encoder->base;
+
+ encoder->possible_crtcs = 0x3;
+ encoder->possible_clones = 0;
+ drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs,
+ DRM_MODE_ENCODER_DAC);
+
+ drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
+
+ /* TODO get the tv dac vals from bios tables */
+ //radeon_combios_get_lvds_info(radeon_encoder);
+
+ return encoder;
+}
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