linux-core/radeon_legacy_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon_drv.h"
  29
  30 #include "drm_crtc_helper.h"
  31
  32 void radeon_restore_common_regs(struct drm_device *dev, struct radeon_legacy_state *state)
  33 {
  34         /* don't need this yet */
  35 }
  36
  37 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
  38 {
  39         struct drm_radeon_private *dev_priv = dev->dev_private;
  40         int i = 0;
  41
  42         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
  43            the cause yet, but this workaround will mask the problem for now.
  44            Other chips usually will pass at the very first test, so the
  45            workaround shouldn't have any effect on them. */
  46         for (i = 0;
  47              (i < 10000 &&
  48               RADEON_READ_PLL(dev_priv, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
  49              i++);
  50 }
  51
  52 static void radeon_pll_write_update(struct drm_device *dev)
  53 {
  54         struct drm_radeon_private *dev_priv = dev->dev_private;
  55
  56         while (RADEON_READ_PLL(dev_priv, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
  57
  58         RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
  59                            RADEON_PPLL_ATOMIC_UPDATE_W,
  60                            ~(RADEON_PPLL_ATOMIC_UPDATE_W));
  61 }
  62
  63 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
  64 {
  65         struct drm_radeon_private *dev_priv = dev->dev_private;
  66         int i = 0;
  67
  68
  69         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
  70            the cause yet, but this workaround will mask the problem for now.
  71            Other chips usually will pass at the very first test, so the
  72            workaround shouldn't have any effect on them. */
  73         for (i = 0;
  74              (i < 10000 &&
  75               RADEON_READ_PLL(dev_priv, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
  76              i++);
  77 }
  78
  79 static void radeon_pll2_write_update(struct drm_device *dev)
  80 {
  81         struct drm_radeon_private *dev_priv = dev->dev_private;
  82
  83         while (RADEON_READ_PLL(dev_priv, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
  84
  85         RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_REF_DIV,
  86                            RADEON_P2PLL_ATOMIC_UPDATE_W,
  87                            ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
  88 }
  89
  90 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
  91                                        uint16_t fb_div)
  92 {
  93         unsigned int vcoFreq;
  94
  95         if (!ref_div)
  96                 return 1;
  97
  98         vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;
  99
 100         /*
 101          * This is horribly crude: the VCO frequency range is divided into
 102          * 3 parts, each part having a fixed PLL gain value.
 103          */
 104         if (vcoFreq >= 30000)
 105                 /*
 106                  * [300..max] MHz : 7
 107                  */
 108                 return 7;
 109         else if (vcoFreq >= 18000)
 110                 /*
 111                  * [180..300) MHz : 4
 112                  */
 113                 return 4;
 114         else
 115                 /*
 116                  * [0..180) MHz : 1
 117                  */
 118                 return 1;
 119 }
 120
 121 void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
 122 {
 123         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 124         struct drm_device *dev = crtc->dev;
 125         struct drm_radeon_private *dev_priv = dev->dev_private;
 126
 127         uint32_t mask;
 128
 129         mask = radeon_crtc->crtc_id ?
 130                 (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_REQ_EN_B) :
 131                 (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS);
 132
 133         switch(mode) {
 134         case DRM_MODE_DPMS_ON:
 135                 if (radeon_crtc->crtc_id) {
 136                         RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, 0, ~mask);
 137                 } else {
 138                         RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
 139                         RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
 140                 }
 141                 break;
 142         case DRM_MODE_DPMS_STANDBY:
 143                 if (radeon_crtc->crtc_id) {
 144                         RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS), ~mask);
 145                 } else {
 146                         RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
 147                         RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS), ~mask);
 148                 }
 149                 break;
 150         case DRM_MODE_DPMS_SUSPEND:
 151                 if (radeon_crtc->crtc_id) {
 152                         RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS), ~mask);
 153                 } else {
 154                         RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
 155                         RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS), ~mask);
 156                 }
 157                 break;
 158         case DRM_MODE_DPMS_OFF:
 159                 if (radeon_crtc->crtc_id) {
 160                         RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask);
 161                 } else {
 162                         RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~RADEON_CRTC_DISP_REQ_EN_B);
 163                         RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
 164                 }
 165                 break;
 166         }
 167
 168         if (mode != DRM_MODE_DPMS_OFF) {
 169                 radeon_crtc_load_lut(crtc);
 170         }
 171 }
 172
 173 static bool radeon_set_crtc1_base(struct drm_crtc *crtc, int x, int y)
 174 {
 175         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 176         struct drm_device *dev = crtc->dev;
 177         struct drm_radeon_private *dev_priv = dev->dev_private;
 178         struct radeon_framebuffer *radeon_fb;
 179         struct drm_radeon_gem_object *obj_priv;
 180         uint32_t base;
 181         uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
 182
 183         radeon_fb = to_radeon_framebuffer(crtc->fb);
 184
 185         obj_priv = radeon_fb->obj->driver_private;
 186
 187         crtc_offset = obj_priv->bo->offset;
 188
 189         crtc_offset_cntl = 0;
 190
 191         /* TODO tiling */
 192         if (0) {
 193                 if (radeon_is_r300(dev_priv))
 194                         crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
 195                                              R300_CRTC_MICRO_TILE_BUFFER_DIS |
 196                                              R300_CRTC_MACRO_TILE_EN);
 197                 else
 198                         crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
 199         } else {
 200                 if (radeon_is_r300(dev_priv))
 201                         crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
 202                                               R300_CRTC_MICRO_TILE_BUFFER_DIS |
 203                                               R300_CRTC_MACRO_TILE_EN);
 204                 else
 205                         crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
 206         }
 207
 208         base = obj_priv->bo->offset;
 209
 210         /* TODO more tiling */
 211         if (0) {
 212                 if (radeon_is_r300(dev_priv)) {
 213                         crtc_tile_x0_y0 = x | (y << 16);
 214                         base &= ~0x7ff;
 215                 } else {
 216                         int byteshift = crtc->fb->bits_per_pixel >> 4;
 217                         int tile_addr = (((y >> 3) * crtc->fb->width + x) >> (8 - byteshift)) << 11;
 218                         base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
 219                         crtc_offset_cntl |= (y % 16);
 220                 }
 221         } else {
 222                 int offset = y * crtc->fb->pitch + x;
 223                 switch (crtc->fb->bits_per_pixel) {
 224                 case 15:
 225                 case 16:
 226                         offset *= 2;
 227                         break;
 228                 case 24:
 229                         offset *= 3;
 230                         break;
 231                 case 32:
 232                         offset *= 4;
 233                         break;
 234                 default:
 235                         return false;
 236                 }
 237                 base += offset;
 238         }
 239
 240         base &= ~7;
 241
 242         /* update sarea TODO */
 243
 244         crtc_offset = base;
 245
 246         if (radeon_is_r300(dev_priv))
 247                 RADEON_WRITE(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
 248
 249         RADEON_WRITE(RADEON_CRTC_OFFSET_CNTL, crtc_offset_cntl);
 250         RADEON_WRITE(RADEON_CRTC_OFFSET, crtc_offset);
 251
 252         return true;
 253 }
 254
 255 static bool radeon_set_crtc1_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
 256 {
 257         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 258         struct drm_device *dev = crtc->dev;
 259         struct drm_radeon_private *dev_priv = dev->dev_private;
 260         int format;
 261         int hsync_start;
 262         int hsync_wid;
 263         int vsync_wid;
 264         uint32_t crtc_gen_cntl;
 265         uint32_t crtc_ext_cntl;
 266         uint32_t crtc_h_total_disp;
 267         uint32_t crtc_h_sync_strt_wid;
 268         uint32_t crtc_v_total_disp;
 269         uint32_t crtc_v_sync_strt_wid;
 270         uint32_t crtc_pitch;
 271         uint32_t disp_merge_cntl;
 272
 273         switch (crtc->fb->depth) {
 274
 275         case 15:      /*  555 */
 276                 format = 3;
 277                 break;
 278         case 16:      /*  565 */
 279                 format = 4;
 280                 break;
 281         case 24:      /*  RGB */
 282                 format = 5;
 283                 break;
 284         case 32:      /* xRGB */
 285                 format = 6;
 286                 break;
 287         default:
 288                 return false;
 289         }
 290
 291         crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN
 292                          | RADEON_CRTC_EN
 293                          | (format << 8)
 294                          | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 295                             ? RADEON_CRTC_DBL_SCAN_EN
 296                             : 0)
 297                          | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 298                             ? RADEON_CRTC_CSYNC_EN
 299                             : 0)
 300                          | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 301                             ? RADEON_CRTC_INTERLACE_EN
 302                             : 0));
 303
 304         crtc_ext_cntl = RADEON_READ(RADEON_CRTC_EXT_CNTL);
 305         crtc_ext_cntl |= (RADEON_XCRT_CNT_EN|
 306                           RADEON_CRTC_VSYNC_DIS |
 307                           RADEON_CRTC_HSYNC_DIS |
 308                           RADEON_CRTC_DISPLAY_DIS);
 309
 310         disp_merge_cntl = RADEON_READ(RADEON_DISP_MERGE_CNTL);
 311         disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
 312
 313         crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
 314                              | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 315
 316         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 317         if (!hsync_wid)
 318                 hsync_wid = 1;
 319         hsync_start = mode->crtc_hsync_start - 8;
 320
 321         crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
 322                                 | ((hsync_wid & 0x3f) << 16)
 323                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 324                                    ? RADEON_CRTC_H_SYNC_POL
 325                                    : 0));
 326
 327         /* This works for double scan mode. */
 328         crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
 329                              | ((mode->crtc_vdisplay - 1) << 16));
 330
 331         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 332         if (!vsync_wid)
 333                 vsync_wid = 1;
 334
 335         crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 336                                 | ((vsync_wid & 0x1f) << 16)
 337                                 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 338                                    ? RADEON_CRTC_V_SYNC_POL
 339                                    : 0));
 340
 341         crtc_pitch  = (((crtc->fb->pitch * crtc->fb->bits_per_pixel) +
 342                         ((crtc->fb->bits_per_pixel * 8) -1)) /
 343                        (crtc->fb->bits_per_pixel * 8));
 344         crtc_pitch |= crtc_pitch << 16;
 345
 346         /* TODO -> Dell Server */
 347         if (0) {
 348                 uint32_t disp_hw_debug = RADEON_READ(RADEON_DISP_HW_DEBUG);
 349                 uint32_t tv_dac_cntl = RADEON_READ(RADEON_TV_DAC_CNTL);
 350                 uint32_t dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2);
 351                 uint32_t crtc2_gen_cntl = RADEON_READ(RADEON_CRTC2_GEN_CNTL);
 352 //              state->dac2_cntl = info->StatedReg->dac2_cntl;
 353 //              state->tv_dac_cntl = info->StatedReg->tv_dac_cntl;
 354 //              state->crtc2_gen_cntl = info->StatedReg->crtc2_gen_cntl;
 355 //              state->disp_hw_debug = info->StatedReg->disp_hw_debug;
 356
 357 //              state->dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
 358 //              state->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
 359
 360                 /* For CRT on DAC2, don't turn it on if BIOS didn't
 361                    enable it, even it's detected.
 362                 */
 363                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
 364                 tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
 365                 tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
 366
 367                 RADEON_WRITE(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 368                 RADEON_WRITE(RADEON_DISP_HW_DEBUG, disp_hw_debug);
 369                 RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
 370                 RADEON_WRITE(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 371         }
 372
 373         RADEON_WRITE(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl |
 374                      RADEON_CRTC_DISP_REQ_EN_B);
 375
 376         RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl,
 377                        RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_DISPLAY_DIS);
 378
 379         RADEON_WRITE(RADEON_CRTC_H_TOTAL_DISP, crtc_h_total_disp);
 380         RADEON_WRITE(RADEON_CRTC_H_SYNC_STRT_WID, crtc_h_sync_strt_wid);
 381         RADEON_WRITE(RADEON_CRTC_V_TOTAL_DISP, crtc_v_total_disp);
 382         RADEON_WRITE(RADEON_CRTC_V_SYNC_STRT_WID, crtc_v_sync_strt_wid);
 383
 384         RADEON_WRITE(RADEON_CRTC_PITCH, crtc_pitch);
 385         RADEON_WRITE(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
 386
 387         RADEON_WRITE(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 388
 389         return true;
 390 }
 391
 392 static void radeon_set_pll1(struct drm_crtc *crtc, struct drm_display_mode *mode, int flags)
 393 {
 394         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 395         struct drm_device *dev = crtc->dev;
 396         struct drm_radeon_private *dev_priv = dev->dev_private;
 397         uint32_t feedback_div = 0;
 398         uint32_t reference_div = 0;
 399         uint32_t post_divider = 0;
 400         uint32_t freq = 0;
 401         uint8_t pll_gain;
 402         /* PLL registers */
 403         uint32_t ppll_ref_div;
 404         uint32_t ppll_div_3;
 405         uint32_t htotal_cntl;
 406         uint32_t vclk_ecp_cntl;
 407
 408         struct radeon_pll *pll = &dev_priv->mode_info.pll;
 409
 410         struct {
 411                 int divider;
 412                 int bitvalue;
 413         } *post_div, post_divs[]   = {
 414                 /* From RAGE 128 VR/RAGE 128 GL Register
 415                  * Reference Manual (Technical Reference
 416                  * Manual P/N RRG-G04100-C Rev. 0.04), page
 417                  * 3-17 (PLL_DIV_[3:0]).
 418                  */
 419                 {  1, 0 },              /* VCLK_SRC                 */
 420                 {  2, 1 },              /* VCLK_SRC/2               */
 421                 {  4, 2 },              /* VCLK_SRC/4               */
 422                 {  8, 3 },              /* VCLK_SRC/8               */
 423                 {  3, 4 },              /* VCLK_SRC/3               */
 424                 { 16, 5 },              /* VCLK_SRC/16              */
 425                 {  6, 6 },              /* VCLK_SRC/6               */
 426                 { 12, 7 },              /* VCLK_SRC/12              */
 427                 {  0, 0 }
 428         };
 429
 430 #if 0 // TODO
 431         if ((flags & RADEON_PLL_USE_BIOS_DIVS) && info->UseBiosDividers) {
 432                 ppll_ref_div = info->RefDivider;
 433                 ppll_div_3   = info->FeedbackDivider | (info->PostDivider << 16);
 434                 htotal_cntl  = 0;
 435                 return;
 436         }
 437 #endif
 438
 439         DRM_DEBUG("\n");
 440         radeon_compute_pll(pll, mode->clock, &freq, &feedback_div, &reference_div, &post_divider, flags);
 441
 442         for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
 443                 if (post_div->divider == post_divider)
 444                         break;
 445         }
 446
 447         if (!post_div->divider) {
 448                 post_div = &post_divs[0];
 449         }
 450
 451         DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
 452                   (unsigned)freq,
 453                   feedback_div,
 454                   reference_div,
 455                   post_divider);
 456
 457         ppll_ref_div   = reference_div;
 458
 459 #if defined(__powerpc__) && (0) /* TODO */
 460         /* apparently programming this otherwise causes a hang??? */
 461         if (info->MacModel == RADEON_MAC_IBOOK)
 462                 state->ppll_div_3 = 0x000600ad;
 463         else
 464 #endif
 465                 ppll_div_3     = (feedback_div | (post_div->bitvalue << 16));
 466
 467         htotal_cntl    = mode->htotal & 0x7;
 468
 469         vclk_ecp_cntl = (RADEON_READ_PLL(dev_priv, RADEON_VCLK_ECP_CNTL) &
 470                          ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK;
 471
 472         pll_gain = radeon_compute_pll_gain(dev_priv->mode_info.pll.reference_freq,
 473                                            ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
 474                                            ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK);
 475
 476         if (dev_priv->flags & RADEON_IS_MOBILITY) {
 477                 /* A temporal workaround for the occational blanking on certain laptop panels.
 478                    This appears to related to the PLL divider registers (fail to lock?).
 479                    It occurs even when all dividers are the same with their old settings.
 480                    In this case we really don't need to fiddle with PLL registers.
 481                    By doing this we can avoid the blanking problem with some panels.
 482                 */
 483                 if ((ppll_ref_div == (RADEON_READ_PLL(dev_priv, RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
 484                     (ppll_div_3 == (RADEON_READ_PLL(dev_priv, RADEON_PPLL_DIV_3) &
 485                                            (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
 486                         RADEON_WRITE_P(RADEON_CLOCK_CNTL_INDEX,
 487                                        RADEON_PLL_DIV_SEL,
 488                                        ~(RADEON_PLL_DIV_SEL));
 489                         radeon_pll_errata_after_index(dev_priv);
 490                         return;
 491                 }
 492         }
 493
 494         RADEON_WRITE_PLL_P(dev_priv, RADEON_VCLK_ECP_CNTL,
 495                            RADEON_VCLK_SRC_SEL_CPUCLK,
 496                            ~(RADEON_VCLK_SRC_SEL_MASK));
 497         RADEON_WRITE_PLL_P(dev_priv,
 498                            RADEON_PPLL_CNTL,
 499                            RADEON_PPLL_RESET
 500                            | RADEON_PPLL_ATOMIC_UPDATE_EN
 501                            | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 502                            | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
 503                            ~(RADEON_PPLL_RESET
 504                              | RADEON_PPLL_ATOMIC_UPDATE_EN
 505                              | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 506                              | RADEON_PPLL_PVG_MASK));
 507
 508         RADEON_WRITE_P(RADEON_CLOCK_CNTL_INDEX,
 509                        RADEON_PLL_DIV_SEL,
 510                        ~(RADEON_PLL_DIV_SEL));
 511         radeon_pll_errata_after_index(dev_priv);
 512
 513         if (radeon_is_r300(dev_priv) ||
 514             (dev_priv->chip_family == CHIP_RS300) ||
 515             (dev_priv->chip_family == CHIP_RS400) ||
 516             (dev_priv->chip_family == CHIP_RS480)) {
 517                 if (ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
 518                         /* When restoring console mode, use saved PPLL_REF_DIV
 519                          * setting.
 520                          */
 521                         RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
 522                                            ppll_ref_div,
 523                                            0);
 524                 } else {
 525                         /* R300 uses ref_div_acc field as real ref divider */
 526                         RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
 527                                            (ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
 528                                            ~R300_PPLL_REF_DIV_ACC_MASK);
 529                 }
 530         } else {
 531                 RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
 532                                    ppll_ref_div,
 533                                    ~RADEON_PPLL_REF_DIV_MASK);
 534         }
 535
 536         RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_DIV_3,
 537                            ppll_div_3,
 538                            ~RADEON_PPLL_FB3_DIV_MASK);
 539
 540         RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_DIV_3,
 541                            ppll_div_3,
 542                            ~RADEON_PPLL_POST3_DIV_MASK);
 543
 544         radeon_pll_write_update(dev);
 545         radeon_pll_wait_for_read_update_complete(dev);
 546
 547         RADEON_WRITE_PLL(dev_priv, RADEON_HTOTAL_CNTL, htotal_cntl);
 548
 549         RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_CNTL,
 550                            0,
 551                            ~(RADEON_PPLL_RESET
 552                              | RADEON_PPLL_SLEEP
 553                              | RADEON_PPLL_ATOMIC_UPDATE_EN
 554                              | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
 555
 556         DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 557                   ppll_ref_div,
 558                   ppll_div_3,
 559                   (unsigned)htotal_cntl,
 560                   RADEON_READ_PLL(dev_priv, RADEON_PPLL_CNTL));
 561         DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n",
 562                   ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
 563                   ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK,
 564                   (ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16);
 565
 566         mdelay(50); /* Let the clock to lock */
 567
 568         RADEON_WRITE_PLL_P(dev_priv, RADEON_VCLK_ECP_CNTL,
 569                            RADEON_VCLK_SRC_SEL_PPLLCLK,
 570                            ~(RADEON_VCLK_SRC_SEL_MASK));
 571
 572         /*RADEON_WRITE_PLL(dev_priv, RADEON_VCLK_ECP_CNTL, state->vclk_ecp_cntl);*/
 573
 574 }
 575
 576 static bool radeon_set_crtc2_base(struct drm_crtc *crtc, int x, int y)
 577 {
 578         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 579         struct drm_device *dev = crtc->dev;
 580         struct drm_radeon_private *dev_priv = dev->dev_private;
 581         struct radeon_framebuffer *radeon_fb;
 582         struct drm_radeon_gem_object *obj_priv;
 583         uint32_t crtc2_offset, crtc2_offset_cntl, crtc2_tile_x0_y0 = 0;
 584         uint32_t base;
 585
 586         radeon_fb = to_radeon_framebuffer(crtc->fb);
 587
 588         obj_priv = radeon_fb->obj->driver_private;
 589
 590         crtc2_offset = obj_priv->bo->offset;
 591
 592         crtc2_offset_cntl = 0;
 593
 594         /* TODO tiling */
 595         if (0) {
 596                 if (radeon_is_r300(dev_priv))
 597                         crtc2_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
 598                                               R300_CRTC_MICRO_TILE_BUFFER_DIS |
 599                                               R300_CRTC_MACRO_TILE_EN);
 600                 else
 601                         crtc2_offset_cntl |= RADEON_CRTC_TILE_EN;
 602         } else {
 603                 if (radeon_is_r300(dev_priv))
 604                         crtc2_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
 605                                                R300_CRTC_MICRO_TILE_BUFFER_DIS |
 606                                                R300_CRTC_MACRO_TILE_EN);
 607                 else
 608                         crtc2_offset_cntl &= ~RADEON_CRTC_TILE_EN;
 609         }
 610
 611         base = obj_priv->bo->offset;
 612
 613         /* TODO more tiling */
 614         if (0) {
 615                 if (radeon_is_r300(dev_priv)) {
 616                         crtc2_tile_x0_y0 = x | (y << 16);
 617                         base &= ~0x7ff;
 618                 } else {
 619                         int byteshift = crtc->fb->bits_per_pixel >> 4;
 620                         int tile_addr = (((y >> 3) * crtc->fb->width + x) >> (8 - byteshift)) << 11;
 621                         base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
 622                         crtc2_offset_cntl |= (y % 16);
 623                 }
 624         } else {
 625                 int offset = y * crtc->fb->pitch + x;
 626                 switch (crtc->fb->bits_per_pixel) {
 627                 case 15:
 628                 case 16:
 629                         offset *= 2;
 630                         break;
 631                 case 24:
 632                         offset *= 3;
 633                         break;
 634                 case 32:
 635                         offset *= 4;
 636                         break;
 637                 default:
 638                         return false;
 639                 }
 640                 base += offset;
 641         }
 642
 643         base &= ~7;
 644
 645         /* update sarea TODO */
 646
 647         crtc2_offset = base;
 648
 649         if (radeon_is_r300(dev_priv))
 650                 RADEON_WRITE(R300_CRTC2_TILE_X0_Y0, crtc2_tile_x0_y0);
 651         RADEON_WRITE(RADEON_CRTC2_OFFSET_CNTL, crtc2_offset_cntl);
 652         RADEON_WRITE(RADEON_CRTC2_OFFSET, crtc2_offset);
 653
 654         return true;
 655 }
 656
 657 static bool radeon_set_crtc2_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
 658 {
 659         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 660         struct drm_device *dev = crtc->dev;
 661         struct drm_radeon_private *dev_priv = dev->dev_private;
 662         int format;
 663         int hsync_start;
 664         int hsync_wid;
 665         int vsync_wid;
 666         uint32_t crtc2_gen_cntl;
 667         uint32_t crtc2_h_total_disp;
 668         uint32_t crtc2_h_sync_strt_wid;
 669         uint32_t crtc2_v_total_disp;
 670         uint32_t crtc2_v_sync_strt_wid;
 671         uint32_t crtc2_pitch;
 672         uint32_t disp2_merge_cntl;
 673         uint32_t fp_h2_sync_strt_wid;
 674         uint32_t fp_v2_sync_strt_wid;
 675
 676         switch (crtc->fb->depth) {
 677
 678         case 15:      /*  555 */
 679                 format = 3;
 680                 break;
 681         case 16:      /*  565 */
 682                 format = 4;
 683                 break;
 684         case 24:      /*  RGB */
 685                 format = 5;
 686                 break;
 687         case 32:      /* xRGB */
 688                 format = 6;
 689                 break;
 690         default:
 691                 return false;
 692         }
 693
 694         crtc2_h_total_disp =
 695                 ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
 696                  | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 697
 698         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 699         if (!hsync_wid)
 700                 hsync_wid = 1;
 701         hsync_start = mode->crtc_hsync_start - 8;
 702
 703         crtc2_h_sync_strt_wid = ((hsync_start & 0x1fff)
 704                                  | ((hsync_wid & 0x3f) << 16)
 705                                  | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 706                                     ? RADEON_CRTC_H_SYNC_POL
 707                                     : 0));
 708
 709         /* This works for double scan mode. */
 710         crtc2_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
 711                               | ((mode->crtc_vdisplay - 1) << 16));
 712
 713         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 714         if (!vsync_wid)
 715                 vsync_wid = 1;
 716
 717         crtc2_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 718                                  | ((vsync_wid & 0x1f) << 16)
 719                                  | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 720                                     ? RADEON_CRTC2_V_SYNC_POL
 721                                     : 0));
 722
 723         crtc2_pitch  = (((crtc->fb->pitch * crtc->fb->bits_per_pixel) +
 724                         ((crtc->fb->bits_per_pixel * 8) -1)) /
 725                        (crtc->fb->bits_per_pixel * 8));
 726         crtc2_pitch |= crtc2_pitch << 16;
 727
 728         /* check to see if TV DAC is enabled for another crtc and keep it enabled */
 729         if (RADEON_READ(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_CRT2_ON)
 730                 crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON;
 731         else
 732                 crtc2_gen_cntl = 0;
 733
 734         crtc2_gen_cntl |= (RADEON_CRTC2_EN
 735                            | (format << 8)
 736                            | RADEON_CRTC2_VSYNC_DIS
 737                            | RADEON_CRTC2_HSYNC_DIS
 738                            | RADEON_CRTC2_DISP_DIS
 739                            | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 740                               ? RADEON_CRTC2_DBL_SCAN_EN
 741                               : 0)
 742                            | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 743                               ? RADEON_CRTC2_CSYNC_EN
 744                               : 0)
 745                            | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 746                               ? RADEON_CRTC2_INTERLACE_EN
 747                               : 0));
 748
 749         disp2_merge_cntl = RADEON_READ(RADEON_DISP2_MERGE_CNTL);
 750         disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
 751
 752         fp_h2_sync_strt_wid = crtc2_h_sync_strt_wid;
 753         fp_v2_sync_strt_wid = crtc2_v_sync_strt_wid;
 754
 755         RADEON_WRITE(RADEON_CRTC2_GEN_CNTL,
 756                      crtc2_gen_cntl | RADEON_CRTC2_VSYNC_DIS |
 757                      RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_DIS |
 758                      RADEON_CRTC2_DISP_REQ_EN_B);
 759
 760         RADEON_WRITE(RADEON_CRTC2_H_TOTAL_DISP,    crtc2_h_total_disp);
 761         RADEON_WRITE(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid);
 762         RADEON_WRITE(RADEON_CRTC2_V_TOTAL_DISP,    crtc2_v_total_disp);
 763         RADEON_WRITE(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid);
 764
 765         RADEON_WRITE(RADEON_FP_H2_SYNC_STRT_WID,   fp_h2_sync_strt_wid);
 766         RADEON_WRITE(RADEON_FP_V2_SYNC_STRT_WID,   fp_v2_sync_strt_wid);
 767
 768         RADEON_WRITE(RADEON_CRTC2_PITCH,           crtc2_pitch);
 769         RADEON_WRITE(RADEON_DISP2_MERGE_CNTL,      disp2_merge_cntl);
 770
 771         RADEON_WRITE(RADEON_CRTC2_GEN_CNTL,        crtc2_gen_cntl);
 772
 773         return true;
 774
 775 }
 776
 777 static void radeon_set_pll2(struct drm_crtc *crtc, struct drm_display_mode *mode, int flags)
 778 {
 779         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 780         struct drm_device *dev = crtc->dev;
 781         struct drm_radeon_private *dev_priv = dev->dev_private;
 782         uint32_t feedback_div = 0;
 783         uint32_t reference_div = 0;
 784         uint32_t post_divider = 0;
 785         uint32_t freq = 0;
 786         uint8_t pll_gain;
 787         /* PLL2 registers */
 788         uint32_t p2pll_ref_div;
 789         uint32_t p2pll_div_0;
 790         uint32_t htotal_cntl2;
 791         uint32_t pixclks_cntl;
 792
 793         struct radeon_pll *pll = &dev_priv->mode_info.pll;
 794
 795         struct {
 796                 int divider;
 797                 int bitvalue;
 798         } *post_div, post_divs[]   = {
 799                 /* From RAGE 128 VR/RAGE 128 GL Register
 800                  * Reference Manual (Technical Reference
 801                  * Manual P/N RRG-G04100-C Rev. 0.04), page
 802                  * 3-17 (PLL_DIV_[3:0]).
 803                  */
 804                 {  1, 0 },              /* VCLK_SRC                 */
 805                 {  2, 1 },              /* VCLK_SRC/2               */
 806                 {  4, 2 },              /* VCLK_SRC/4               */
 807                 {  8, 3 },              /* VCLK_SRC/8               */
 808                 {  3, 4 },              /* VCLK_SRC/3               */
 809                 {  6, 6 },              /* VCLK_SRC/6               */
 810                 { 12, 7 },              /* VCLK_SRC/12              */
 811                 {  0, 0 }
 812         };
 813
 814 #if 0
 815         if ((flags & RADEON_PLL_USE_BIOS_DIVS) && info->UseBiosDividers) {
 816                 p2pll_ref_div = info->RefDivider;
 817                 p2pll_div_0   = info->FeedbackDivider | (info->PostDivider << 16);
 818                 htotal_cntl2  = 0;
 819                 return;
 820         }
 821 #endif
 822
 823         radeon_compute_pll(pll, mode->clock, &freq, &feedback_div, &reference_div, &post_divider, flags);
 824
 825         for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
 826                 if (post_div->divider == post_divider)
 827                         break;
 828         }
 829
 830         if (!post_div->divider) {
 831                 post_div = &post_divs[0];
 832         }
 833
 834         DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
 835                   (unsigned)freq,
 836                   feedback_div,
 837                   reference_div,
 838                   post_divider);
 839
 840         p2pll_ref_div    = reference_div;
 841
 842         p2pll_div_0      = (feedback_div | (post_div->bitvalue << 16));
 843
 844         htotal_cntl2     = mode->htotal & 0x7;
 845
 846         pixclks_cntl     = ((RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL) &
 847                              ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
 848                             RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
 849
 850         pll_gain = radeon_compute_pll_gain(dev_priv->mode_info.pll.reference_freq,
 851                                            p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
 852                                            p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK);
 853
 854
 855         RADEON_WRITE_PLL_P(dev_priv, RADEON_PIXCLKS_CNTL,
 856                            RADEON_PIX2CLK_SRC_SEL_CPUCLK,
 857                            ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 858
 859         RADEON_WRITE_PLL_P(dev_priv,
 860                            RADEON_P2PLL_CNTL,
 861                            RADEON_P2PLL_RESET
 862                            | RADEON_P2PLL_ATOMIC_UPDATE_EN
 863                            | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
 864                            ~(RADEON_P2PLL_RESET
 865                              | RADEON_P2PLL_ATOMIC_UPDATE_EN
 866                              | RADEON_P2PLL_PVG_MASK));
 867
 868
 869         RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_REF_DIV,
 870                            p2pll_ref_div,
 871                            ~RADEON_P2PLL_REF_DIV_MASK);
 872
 873         RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_DIV_0,
 874                            p2pll_div_0,
 875                            ~RADEON_P2PLL_FB0_DIV_MASK);
 876
 877         RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_DIV_0,
 878                            p2pll_div_0,
 879                            ~RADEON_P2PLL_POST0_DIV_MASK);
 880
 881         radeon_pll2_write_update(dev);
 882         radeon_pll2_wait_for_read_update_complete(dev);
 883
 884         RADEON_WRITE_PLL(dev_priv, RADEON_HTOTAL2_CNTL, htotal_cntl2);
 885
 886         RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_CNTL,
 887                            0,
 888                            ~(RADEON_P2PLL_RESET
 889                              | RADEON_P2PLL_SLEEP
 890                              | RADEON_P2PLL_ATOMIC_UPDATE_EN));
 891
 892         DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 893                   (unsigned)p2pll_ref_div,
 894                   (unsigned)p2pll_div_0,
 895                   (unsigned)htotal_cntl2,
 896                   RADEON_READ_PLL(dev_priv, RADEON_P2PLL_CNTL));
 897         DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n",
 898                   (unsigned)p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
 899                   (unsigned)p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK,
 900                   (unsigned)((p2pll_div_0 &
 901                               RADEON_P2PLL_POST0_DIV_MASK) >>16));
 902
 903         mdelay(50); /* Let the clock to lock */
 904
 905         RADEON_WRITE_PLL_P(dev_priv, RADEON_PIXCLKS_CNTL,
 906                            RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
 907                            ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 908
 909         RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, pixclks_cntl);
 910
 911 }
 912
 913 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
 914                                    struct drm_display_mode *mode,
 915                                    struct drm_display_mode *adjusted_mode)
 916 {
 917         return true;
 918 }
 919
 920 static void radeon_crtc_mode_set(struct drm_crtc *crtc,
 921                                  struct drm_display_mode *mode,
 922                                  struct drm_display_mode *adjusted_mode,
 923                                  int x, int y)
 924 {
 925         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 926         struct drm_device *dev = crtc->dev;
 927         struct drm_radeon_private *dev_priv = dev->dev_private;
 928         struct drm_encoder *encoder;
 929         int pll_flags = RADEON_PLL_LEGACY | RADEON_PLL_PREFER_LOW_REF_DIV;
 930         int i;
 931
 932         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 933                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 934
 935                 if (encoder->crtc == crtc) {
 936                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 937                                 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
 938                         if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
 939                                 pll_flags |= RADEON_PLL_USE_BIOS_DIVS | RADEON_PLL_USE_REF_DIV;
 940                 }
 941         }
 942
 943         /* TODO TV */
 944
 945         switch(radeon_crtc->crtc_id) {
 946         case 0:
 947                 radeon_set_crtc1_timing(crtc, adjusted_mode);
 948                 radeon_set_pll1(crtc, adjusted_mode, pll_flags);
 949                 break;
 950         case 1:
 951                 radeon_set_crtc2_timing(crtc, adjusted_mode);
 952                 radeon_set_pll2(crtc, adjusted_mode, pll_flags);
 953                 break;
 954
 955         }
 956 }
 957
 958 void radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y)
 959 {
 960         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 961
 962         switch(radeon_crtc->crtc_id) {
 963         case 0:
 964                 radeon_set_crtc1_base(crtc, x, y);
 965                 break;
 966         case 1:
 967                 radeon_set_crtc2_base(crtc, x, y);
 968                 break;
 969
 970         }
 971 }
 972
 973 static void radeon_crtc_prepare(struct drm_crtc *crtc)
 974 {
 975         radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 976 }
 977
 978 static void radeon_crtc_commit(struct drm_crtc *crtc)
 979 {
 980         radeon_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 981 }
 982
 983 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
 984         .dpms = radeon_crtc_dpms,
 985         .mode_fixup = radeon_crtc_mode_fixup,
 986         .mode_set = radeon_crtc_mode_set,
 987         .mode_set_base = radeon_crtc_set_base,
 988         .prepare = radeon_crtc_prepare,
 989         .commit = radeon_crtc_commit,
 990 };
 991
 992
 993 void radeon_legacy_init_crtc(struct drm_device *dev,
 994                                struct radeon_crtc *radeon_crtc)
 995 {
 996         drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
 997 }