1 2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
4 * i386-opc.tbl: Add Disp32S to 64bit call.
5 * i386-tbl.h: Regenerated.
7 2011-07-24 Chao-ying Fu <fu@mips.com>
8 Maciej W. Rozycki <macro@codesourcery.com>
10 * micromips-opc.c: New file.
11 * mips-dis.c (micromips_to_32_reg_b_map): New array.
12 (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
13 (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
14 (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
15 (micromips_to_32_reg_q_map): Likewise.
16 (micromips_imm_b_map, micromips_imm_c_map): Likewise.
17 (micromips_ase): New variable.
18 (is_micromips): New function.
19 (set_default_mips_dis_options): Handle microMIPS ASE.
20 (print_insn_micromips): New function.
21 (is_compressed_mode_p): Likewise.
22 (_print_insn_mips): Handle microMIPS instructions.
23 * Makefile.am (CFILES): Add micromips-opc.c.
24 * configure.in (bfd_mips_arch): Add micromips-opc.lo.
25 * Makefile.in: Regenerate.
26 * configure: Regenerate.
28 * mips-dis.c (micromips_to_32_reg_h_map): New variable.
29 (micromips_to_32_reg_i_map): Likewise.
30 (micromips_to_32_reg_m_map): Likewise.
31 (micromips_to_32_reg_n_map): New macro.
33 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
35 * mips-opc.c (NODS): New macro.
36 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
38 (mips_builtin_opcodes): Add NODS annotation to "deret" and
39 "eret". Replace INSN_SYNC with NODS throughout. Use NODS in
40 place of TRAP for "wait", "waiti" and "yield".
41 * mips16-opc.c (NODS): New macro.
42 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
43 (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
46 2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
48 * configure.in: Handle bfd_k1om_arch.
49 * configure: Regenerated.
51 * disassemble.c (disassembler): Handle bfd_k1om_arch.
53 * i386-dis.c (print_insn): Handle bfd_mach_k1om and
54 bfd_mach_k1om_intel_syntax.
56 * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
57 ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
58 (cpu_flags): Add CpuK1OM.
60 * i386-opc.h (CpuK1OM): New.
61 (i386_cpu_flags): Add cpuk1om.
63 * i386-init.h: Regenerated.
64 * i386-tbl.h: Likewise.
66 2011-07-12 Nick Clifton <nickc@redhat.com>
68 * arm-dis.c (print_insn_arm): Revert previous, undocumented,
71 2011-07-01 Nick Clifton <nickc@redhat.com>
74 * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
75 insns using post-increment addressing.
77 2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
79 * i386-dis.c (vex_len_table): Update rorxS.
81 2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
83 AVX Programming Reference (June, 2011)
84 * i386-dis.c (vex_len_table): Correct rorxS.
86 * i386-opc.tbl: Correct rorx.
87 * i386-tbl.h: Regenerated.
89 2011-06-29 H.J. Lu <hongjiu.lu@intel.com>
91 * tilegx-opc.c (find_opcode): Replace "index" with "i".
92 * tilepro-opc.c (find_opcode): Likewise.
94 2011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
96 * mips16-opc.c (jalrc, jrc): Move earlier in file.
98 2011-06-21 H.J. Lu <hongjiu.lu@intel.com>
100 * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
103 2011-06-17 Andreas Schwab <schwab@redhat.com>
105 * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
106 (MOSTLYCLEANFILES): ... here.
107 * Makefile.in: Regenerate.
109 2011-06-14 Alan Modra <amodra@gmail.com>
111 * Makefile.in: Regenerate.
113 2011-06-13 Walter Lee <walt@tilera.com>
115 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
116 tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
117 * Makefile.in: Regenerate.
118 * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
119 * configure: Regenerate.
120 * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
121 * po/POTFILES.in: Regenerate.
122 * tilegx-dis.c: New file.
123 * tilegx-opc.c: New file.
124 * tilepro-dis.c: New file.
125 * tilepro-opc.c: New file.
127 2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
129 AVX Programming Reference (June, 2011)
130 * i386-dis.c (XMGatherQ): New.
131 * i386-dis.c (EXxmm_mb): New.
132 (EXxmm_mb): Likewise.
133 (EXxmm_mw): Likewise.
134 (EXxmm_md): Likewise.
135 (EXxmm_mq): Likewise.
138 (VexGatherQ): Likewise.
139 (MVexVSIBDWpX): Likewise.
140 (MVexVSIBQWpX): Likewise.
141 (xmm_mb_mode): Likewise.
142 (xmm_mw_mode): Likewise.
143 (xmm_md_mode): Likewise.
144 (xmm_mq_mode): Likewise.
145 (xmmdw_mode): Likewise.
146 (xmmqd_mode): Likewise.
147 (ymmxmm_mode): Likewise.
148 (vex_vsib_d_w_dq_mode): Likewise.
149 (vex_vsib_q_w_dq_mode): Likewise.
150 (MOD_VEX_0F385A_PREFIX_2): Likewise.
151 (MOD_VEX_0F388C_PREFIX_2): Likewise.
152 (MOD_VEX_0F388E_PREFIX_2): Likewise.
153 (PREFIX_0F3882): Likewise.
154 (PREFIX_VEX_0F3816): Likewise.
155 (PREFIX_VEX_0F3836): Likewise.
156 (PREFIX_VEX_0F3845): Likewise.
157 (PREFIX_VEX_0F3846): Likewise.
158 (PREFIX_VEX_0F3847): Likewise.
159 (PREFIX_VEX_0F3858): Likewise.
160 (PREFIX_VEX_0F3859): Likewise.
161 (PREFIX_VEX_0F385A): Likewise.
162 (PREFIX_VEX_0F3878): Likewise.
163 (PREFIX_VEX_0F3879): Likewise.
164 (PREFIX_VEX_0F388C): Likewise.
165 (PREFIX_VEX_0F388E): Likewise.
166 (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
167 (PREFIX_VEX_0F38F5): Likewise.
168 (PREFIX_VEX_0F38F6): Likewise.
169 (PREFIX_VEX_0F3A00): Likewise.
170 (PREFIX_VEX_0F3A01): Likewise.
171 (PREFIX_VEX_0F3A02): Likewise.
172 (PREFIX_VEX_0F3A38): Likewise.
173 (PREFIX_VEX_0F3A39): Likewise.
174 (PREFIX_VEX_0F3A46): Likewise.
175 (PREFIX_VEX_0F3AF0): Likewise.
176 (VEX_LEN_0F3816_P_2): Likewise.
177 (VEX_LEN_0F3819_P_2): Likewise.
178 (VEX_LEN_0F3836_P_2): Likewise.
179 (VEX_LEN_0F385A_P_2_M_0): Likewise.
180 (VEX_LEN_0F38F5_P_0): Likewise.
181 (VEX_LEN_0F38F5_P_1): Likewise.
182 (VEX_LEN_0F38F5_P_3): Likewise.
183 (VEX_LEN_0F38F6_P_3): Likewise.
184 (VEX_LEN_0F38F7_P_1): Likewise.
185 (VEX_LEN_0F38F7_P_2): Likewise.
186 (VEX_LEN_0F38F7_P_3): Likewise.
187 (VEX_LEN_0F3A00_P_2): Likewise.
188 (VEX_LEN_0F3A01_P_2): Likewise.
189 (VEX_LEN_0F3A38_P_2): Likewise.
190 (VEX_LEN_0F3A39_P_2): Likewise.
191 (VEX_LEN_0F3A46_P_2): Likewise.
192 (VEX_LEN_0F3AF0_P_3): Likewise.
193 (VEX_W_0F3816_P_2): Likewise.
194 (VEX_W_0F3818_P_2): Likewise.
195 (VEX_W_0F3819_P_2): Likewise.
196 (VEX_W_0F3836_P_2): Likewise.
197 (VEX_W_0F3846_P_2): Likewise.
198 (VEX_W_0F3858_P_2): Likewise.
199 (VEX_W_0F3859_P_2): Likewise.
200 (VEX_W_0F385A_P_2_M_0): Likewise.
201 (VEX_W_0F3878_P_2): Likewise.
202 (VEX_W_0F3879_P_2): Likewise.
203 (VEX_W_0F3A00_P_2): Likewise.
204 (VEX_W_0F3A01_P_2): Likewise.
205 (VEX_W_0F3A02_P_2): Likewise.
206 (VEX_W_0F3A38_P_2): Likewise.
207 (VEX_W_0F3A39_P_2): Likewise.
208 (VEX_W_0F3A46_P_2): Likewise.
209 (MOD_VEX_0F3818_PREFIX_2): Removed.
210 (MOD_VEX_0F3819_PREFIX_2): Likewise.
211 (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
212 (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
213 (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
214 (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
215 (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
216 (VEX_LEN_0F3A0E_P_2): Likewise.
217 (VEX_LEN_0F3A0F_P_2): Likewise.
218 (VEX_LEN_0F3A42_P_2): Likewise.
219 (VEX_LEN_0F3A4C_P_2): Likewise.
220 (VEX_W_0F3818_P_2_M_0): Likewise.
221 (VEX_W_0F3819_P_2_M_0): Likewise.
222 (prefix_table): Updated.
223 (three_byte_table): Likewise.
224 (vex_table): Likewise.
225 (vex_len_table): Likewise.
226 (vex_w_table): Likewise.
227 (mod_table): Likewise.
228 (putop): Handle "LW".
229 (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
230 xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
231 vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
233 (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
234 vex_vsib_q_w_dq_mode.
235 (OP_XMM): Handle vex_vsib_q_w_dq_mode.
238 * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
239 and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
240 CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
241 (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
242 (opcode_modifiers): Add VecSIB.
244 * i386-opc.h (CpuAVX2): New.
246 (CpuLZCNT): Likewise.
247 (CpuINVPCID): Likewise.
248 (VecSIB128): Likewise.
249 (VecSIB256): Likewise.
251 (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
252 (i386_opcode_modifier): Add vecsib.
254 * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
255 * i386-init.h: Regenerated.
256 * i386-tbl.h: Likewise.
258 2011-06-03 Quentin Neill <quentin.neill@amd.com>
260 * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
261 * i386-init.h: Regenerated.
263 2011-06-03 Nick Clifton <nickc@redhat.com>
266 * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
267 computing address offsets.
268 (print_arm_address): Likewise.
269 (print_insn_arm): Likewise.
270 (print_insn_thumb16): Likewise.
271 (print_insn_thumb32): Likewise.
273 2011-06-02 Jie Zhang <jie@codesourcery.com>
274 Nathan Sidwell <nathan@codesourcery.com>
275 Maciej Rozycki <macro@codesourcery.com>
277 * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
279 (print_arm_address): Likewise. Elide positive #0 appropriately.
280 (print_insn_arm): Likewise.
282 2011-06-02 Nick Clifton <nickc@redhat.com>
285 * arm-dis.c (print_insn_thumb32): Do not sign extend addresses
286 passed to print_address_func.
288 2011-06-02 Nick Clifton <nickc@redhat.com>
290 * arm-dis.c: Fix spelling mistakes.
291 * op/opcodes.pot: Regenerate.
293 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
295 * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
296 S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
297 * s390-opc.txt: Fix cxr instruction type.
299 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
301 * s390-opc.c: Add new instruction types marking register pair
303 * s390-opc.txt: Match instructions having register pair operands
304 to the new instruction types.
306 2011-05-19 Nick Clifton <nickc@redhat.com>
308 * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
311 2011-05-10 Quentin Neill <quentin.neill@amd.com>
313 * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
314 * i386-init.h: Regenerated.
316 2011-04-27 Nick Clifton <nickc@redhat.com>
318 * po/da.po: Updated Danish translation.
320 2011-04-26 Anton Blanchard <anton@samba.org>
322 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
324 2011-04-21 DJ Delorie <dj@redhat.com>
326 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
327 * rx-decode.c: Regenerate.
329 2011-04-20 H.J. Lu <hongjiu.lu@intel.com>
331 * i386-init.h: Regenerated.
333 2011-04-19 Quentin Neill <quentin.neill@amd.com>
335 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
338 2011-04-13 Nick Clifton <nickc@redhat.com>
340 * v850-dis.c (disassemble): Always print a closing square brace if
341 an opening square brace was printed.
343 2011-04-12 Nick Clifton <nickc@redhat.com>
346 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
348 (print_insn_thumb32): Handle %L.
350 2011-04-11 Julian Brown <julian@codesourcery.com>
352 * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
353 (print_insn_thumb32): Add APSR bitmask support.
355 2011-04-07 Paul Carroll<pcarroll@codesourcery.com>
357 * arm-dis.c (print_insn): init vars moved into private_data structure.
359 2011-03-24 Mike Frysinger <vapier@gentoo.org>
361 * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
363 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
365 * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
366 post-increment to support LPM Z+ instruction. Add support for 'E'
367 constraint for DES instruction.
368 (print_insn_avr): Adjust calls to avr_operand. Rename variable.
370 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
372 * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
374 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
376 * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
377 Use branch types instead.
378 (print_insn): Likewise.
380 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
382 * mips-opc.c (mips_builtin_opcodes): Correct register use
383 annotation of "alnv.ps".
385 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
387 * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
389 2011-02-22 Mike Frysinger <vapier@gentoo.org>
391 * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
393 2011-02-22 Mike Frysinger <vapier@gentoo.org>
395 * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
397 2011-02-19 Mike Frysinger <vapier@gentoo.org>
399 * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
400 a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
401 av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
402 exception, end_of_registers, msize, memory, bfd_mach.
403 (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
404 LB0REG, LC1REG, LT1REG, LB1REG): Delete
405 (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
406 (get_allreg): Change to new defines. Fallback to abort().
408 2011-02-14 Mike Frysinger <vapier@gentoo.org>
410 * bfin-dis.c: Add whitespace/parenthesis where needed.
412 2011-02-14 Mike Frysinger <vapier@gentoo.org>
414 * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
417 2011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
419 * configure: Regenerate.
421 2011-02-13 Mike Frysinger <vapier@gentoo.org>
423 * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
425 2011-02-13 Mike Frysinger <vapier@gentoo.org>
427 * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
428 dregs only when P is set, and dregs_lo otherwise.
430 2011-02-13 Mike Frysinger <vapier@gentoo.org>
432 * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
434 2011-02-12 Mike Frysinger <vapier@gentoo.org>
436 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
438 2011-02-12 Mike Frysinger <vapier@gentoo.org>
440 * bfin-dis.c (machine_registers): Delete REG_GP.
441 (reg_names): Delete "GP".
442 (decode_allregs): Change REG_GP to REG_LASTREG.
444 2011-02-12 Mike Frysinger <vapier@gentoo.org>
446 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
449 2011-02-11 Mike Frysinger <vapier@gentoo.org>
451 * bfin-dis.c (reg_names): Add const.
452 (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
453 decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
454 decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
455 decode_counters, decode_allregs): Likewise.
457 2011-02-09 Michael Snyder <msnyder@vmware.com>
459 * i386-dis.c (OP_J): Parenthesize expression to prevent
461 (print_insn): Fix indentation off-by-one.
463 2011-02-01 Nick Clifton <nickc@redhat.com>
465 * po/da.po: Updated Danish translation.
467 2011-01-21 Dave Murphy <davem@devkitpro.org>
469 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
471 2011-01-18 H.J. Lu <hongjiu.lu@intel.com>
473 * i386-dis.c (sIbT): New.
474 (b_T_mode): Likewise.
475 (dis386): Replace sIb with sIbT on "pushT".
476 (x86_64_table): Replace sIb with Ib on "aam" and "aad".
477 (OP_sI): Handle b_T_mode. Properly sign-extend byte.
479 2011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
481 * i386-init.h: Regenerated.
482 * i386-tbl.h: Regenerated
484 2011-01-17 Quentin Neill <quentin.neill@amd.com>
486 * i386-dis.c (REG_XOP_TBM_01): New.
487 (REG_XOP_TBM_02): New.
488 (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
489 (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
490 entries, and add bextr instruction.
492 * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
493 (cpu_flags): Add CpuTBM.
495 * i386-opc.h (CpuTBM) New.
496 (i386_cpu_flags): Add bit cputbm.
498 * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
499 blcs, blsfill, blsic, t1mskc, and tzmsk.
501 2011-01-12 DJ Delorie <dj@redhat.com>
503 * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
505 2011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
507 * mips-dis.c (print_insn_args): Adjust the value to print the real
508 offset for "+c" argument.
510 2011-01-10 Nick Clifton <nickc@redhat.com>
512 * po/da.po: Updated Danish translation.
514 2011-01-05 Nathan Sidwell <nathan@codesourcery.com>
516 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
518 2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
520 * i386-dis.c (REG_VEX_38F3): New.
521 (PREFIX_0FBC): Likewise.
522 (PREFIX_VEX_38F2): Likewise.
523 (PREFIX_VEX_38F3_REG_1): Likewise.
524 (PREFIX_VEX_38F3_REG_2): Likewise.
525 (PREFIX_VEX_38F3_REG_3): Likewise.
526 (PREFIX_VEX_38F7): Likewise.
527 (VEX_LEN_38F2_P_0): Likewise.
528 (VEX_LEN_38F3_R_1_P_0): Likewise.
529 (VEX_LEN_38F3_R_2_P_0): Likewise.
530 (VEX_LEN_38F3_R_3_P_0): Likewise.
531 (VEX_LEN_38F7_P_0): Likewise.
532 (dis386_twobyte): Use PREFIX_0FBC.
533 (reg_table): Add REG_VEX_38F3.
534 (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
535 PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
536 PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
537 (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
539 (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
540 VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
543 * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
544 (cpu_flags): Add CpuBMI.
546 * i386-opc.h (CpuBMI): New.
547 (i386_cpu_flags): Add cpubmi.
549 * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
550 * i386-init.h: Regenerated.
551 * i386-tbl.h: Likewise.
553 2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
555 * i386-dis.c (VexGdq): New.
556 (OP_VEX): Handle dq_mode.
558 2011-01-01 H.J. Lu <hongjiu.lu@intel.com>
560 * i386-gen.c (process_copyright): Update copyright to 2011.
562 For older changes see ChangeLog-2010
568 version-control: never