Add Disp32S to 64bit call.

gas/testsuite/

2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/13046
	* gas/i386/x86-64-branch.s: Add tests for direct branch.
	* gas/i386/x86-64-branch.d: Updated.
	* gas/i386/ilp32/x86-64-branch.d: Likewise.

opcodes/

2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/13046
	* i386-opc.tbl: Add Disp32S to 64bit call.
	* i386-tbl.h: Regenerated.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index eb5ce65..063f899 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR gas/13046
+       * gas/i386/x86-64-branch.s: Add tests for direct branch.
+       * gas/i386/x86-64-branch.d: Updated.
+       * gas/i386/ilp32/x86-64-branch.d: Likewise. 
+
 2011-07-29  Nick Clifton  <nickc@redhat.com>
 
        * gas/elf/warn-2.s: Add other types of NOP insn.

diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-branch.d b/gas/testsuite/gas/i386/ilp32/x86-64-branch.d
index cb33840..9118db1 100644 (file)
--- a/gas/testsuite/gas/i386/ilp32/x86-64-branch.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-branch.d
@@ -18,6 +18,8 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    66 ff e0                jmpw   \*%ax
 [      ]*[a-f0-9]+:    66 ff e0                jmpw   \*%ax
 [      ]*[a-f0-9]+:    66 ff 20                jmpw   \*\(%rax\)
+[      ]*[a-f0-9]+:    e8 00 00 00 00          callq  0x1f     1b: R_X86_64_PC32       \*ABS\*\+0x10003c
+[      ]*[a-f0-9]+:    e9 00 00 00 00          jmpq   0x24     20: R_X86_64_PC32       \*ABS\*\+0x10003c
 [      ]*[a-f0-9]+:    ff d0                   callq  \*%rax
 [      ]*[a-f0-9]+:    ff d0                   callq  \*%rax
 [      ]*[a-f0-9]+:    66 ff d0                callw  \*%ax
@@ -28,4 +30,6 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    66 ff e0                jmpw   \*%ax
 [      ]*[a-f0-9]+:    66 ff e0                jmpw   \*%ax
 [      ]*[a-f0-9]+:    66 ff 20                jmpw   \*\(%rax\)
+[      ]*[a-f0-9]+:    e8 00 00 00 00          callq  0x43     3f: R_X86_64_PC32       \*ABS\*\+0x10003c
+[      ]*[a-f0-9]+:    e9 00 00 00 00          jmpq   0x48     44: R_X86_64_PC32       \*ABS\*\+0x10003c
 #pass

diff --git a/gas/testsuite/gas/i386/x86-64-branch.d b/gas/testsuite/gas/i386/x86-64-branch.d
index cc3d3a9..428ce5b 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-branch.d
+++ b/gas/testsuite/gas/i386/x86-64-branch.d
@@ -17,6 +17,8 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    66 ff e0                jmpw   \*%ax
 [      ]*[a-f0-9]+:    66 ff e0                jmpw   \*%ax
 [      ]*[a-f0-9]+:    66 ff 20                jmpw   \*\(%rax\)
+[      ]*[a-f0-9]+:    e8 00 00 00 00          callq  0x1f     1b: R_X86_64_PC32       \*ABS\*\+0x10003c
+[      ]*[a-f0-9]+:    e9 00 00 00 00          jmpq   0x24     20: R_X86_64_PC32       \*ABS\*\+0x10003c
 [      ]*[a-f0-9]+:    ff d0                   callq  \*%rax
 [      ]*[a-f0-9]+:    ff d0                   callq  \*%rax
 [      ]*[a-f0-9]+:    66 ff d0                callw  \*%ax
@@ -27,4 +29,6 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    66 ff e0                jmpw   \*%ax
 [      ]*[a-f0-9]+:    66 ff e0                jmpw   \*%ax
 [      ]*[a-f0-9]+:    66 ff 20                jmpw   \*\(%rax\)
+[      ]*[a-f0-9]+:    e8 00 00 00 00          callq  0x43     3f: R_X86_64_PC32       \*ABS\*\+0x10003c
+[      ]*[a-f0-9]+:    e9 00 00 00 00          jmpq   0x48     44: R_X86_64_PC32       \*ABS\*\+0x10003c
 #pass

diff --git a/gas/testsuite/gas/i386/x86-64-branch.s b/gas/testsuite/gas/i386/x86-64-branch.s
index 10fdd81..4c1861f 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-branch.s
+++ b/gas/testsuite/gas/i386/x86-64-branch.s
@@ -9,6 +9,8 @@
        jmp     *%ax
        jmpw    *%ax
        jmpw    *(%rax)
+       call    0x100040
+       jmp     0x100040
 
        .intel_syntax noprefix
        call    rax
@@ -21,3 +23,5 @@
        jmp     ax
        jmpw    ax
        jmpw    [rax]
+       call    0x100040
+       jmp     0x100040

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 9b5494e..4e39050 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR gas/13046
+       * i386-opc.tbl: Add Disp32S to 64bit call.
+       * i386-tbl.h: Regenerated.
+
 2011-07-24  Chao-ying Fu  <fu@mips.com>
             Maciej W. Rozycki  <macro@codesourcery.com>
 

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 4c29ab7..eb7dae9 100644 (file)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -320,7 +320,7 @@ shrd, 2, 0xfad, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, {
 
 // Control transfer instructions.
 call, 1, 0xe8, None, 1, CpuNo64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp16|Disp32 }
-call, 1, 0xe8, None, 1, Cpu64, JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Disp16|Disp32 }
+call, 1, 0xe8, None, 1, Cpu64, JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Disp16|Disp32|Disp32S }
 call, 1, 0xff, 0x2, 1, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|JumpAbsolute }
 call, 1, 0xff, 0x2, 1, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute }
 // Intel Syntax

diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index f133b80..795f71d 100644 (file)
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -2558,7 +2558,7 @@ const insn_template i386_optab[] =
       1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+         0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0 } } } },
   { "call", 1, 0xff, 0x2, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,