2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.conv_std_logic_vector;
4 use ieee.std_logic_unsigned.conv_integer;
7 generic (dsize : integer := 8);
8 port ( set_clk : in std_logic;
9 trig_clk : in std_logic;
14 instruction : in std_logic_vector (dsize - 1 downto 0);
15 exec_cycle : in std_logic_vector (5 downto 0);
16 next_cycle : out std_logic_vector (5 downto 0);
17 status_reg : inout std_logic_vector (dsize - 1 downto 0);
18 inst_we_n : out std_logic;
19 ad_oe_n : out std_logic;
20 dbuf_int_oe_n : out std_logic;
21 dl_al_we_n : out std_logic;
22 dl_ah_we_n : out std_logic;
23 dl_al_oe_n : out std_logic;
24 dl_ah_oe_n : out std_logic;
25 dl_dh_oe_n : out std_logic;
26 pcl_inc_n : out std_logic;
27 pch_inc_n : out std_logic;
28 pcl_cmd : out std_logic_vector(3 downto 0);
29 pch_cmd : out std_logic_vector(3 downto 0);
30 sp_cmd : out std_logic_vector(3 downto 0);
31 sp_oe_n : out std_logic;
32 sp_push_n : out std_logic;
33 sp_pop_n : out std_logic;
34 acc_cmd : out std_logic_vector(3 downto 0);
35 x_cmd : out std_logic_vector(3 downto 0);
36 y_cmd : out std_logic_vector(3 downto 0);
37 abs_xy_n : out std_logic;
38 ea_carry : in std_logic;
39 pg_next_n : out std_logic;
41 zp_xy_n : out std_logic;
42 rel_calc_n : out std_logic;
43 indir_n : out std_logic;
44 indir_x_n : out std_logic;
45 indir_y_n : out std_logic;
46 arith_en_n : out std_logic;
47 stat_dec_oe_n : out std_logic;
48 stat_bus_oe_n : out std_logic;
49 stat_set_flg_n : out std_logic;
50 stat_flg : out std_logic;
51 stat_bus_all_n : out std_logic;
52 stat_bus_nz_n : out std_logic;
53 stat_alu_we_n : out std_logic;
54 r_vec_oe_n : out std_logic;
55 n_vec_oe_n : out std_logic;
56 i_vec_oe_n : out std_logic;
58 ;---for parameter check purpose!!!
59 check_bit : out std_logic_vector(1 to 5)
63 architecture rtl of decoder is
65 component d_flip_flop_bit
76 procedure d_print(msg : string) is
78 use ieee.std_logic_textio.all;
79 variable out_l : line;
82 writeline(output, out_l);
85 ---ival : 0x0000 - 0xffff
86 function conv_hex8(ival : integer) return string is
87 variable tmp1, tmp2 : integer;
88 variable hex_chr: string (1 to 16) := "0123456789abcdef";
90 tmp2 := (ival mod 16 ** 2) / 16 ** 1;
91 tmp1 := ival mod 16 ** 1;
92 return hex_chr(tmp2 + 1) & hex_chr(tmp1 + 1);
96 -- bit 5 : pcl increment carry flag
97 -- bit 4,3 : cycle type: 00 normal, 01 reset , 10 nmi, 11 irq
100 --00xxx : exec cycle : T0 > T1 > T2 > T3 > T4 > T5 > T6 > T0
101 constant T0 : std_logic_vector (5 downto 0) := "000000";
102 constant T1 : std_logic_vector (5 downto 0) := "000001";
103 constant T2 : std_logic_vector (5 downto 0) := "000010";
104 constant T3 : std_logic_vector (5 downto 0) := "000011";
105 constant T4 : std_logic_vector (5 downto 0) := "000100";
106 constant T5 : std_logic_vector (5 downto 0) := "000101";
107 constant T6 : std_logic_vector (5 downto 0) := "000110";
109 --01xxx : reset cycle : R0 > R1 > R2 > R3 > R4 > R5 > T0
110 constant R0 : std_logic_vector (5 downto 0) := "001000";
111 constant R1 : std_logic_vector (5 downto 0) := "001001";
112 constant R2 : std_logic_vector (5 downto 0) := "001010";
113 constant R3 : std_logic_vector (5 downto 0) := "001011";
114 constant R4 : std_logic_vector (5 downto 0) := "001100";
115 constant R5 : std_logic_vector (5 downto 0) := "001101";
117 --10xxx : nmi cycle : T0 > N1 > N2 > N3 > N4 > N5 > T0
118 constant N1 : std_logic_vector (5 downto 0) := "010001";
119 constant N2 : std_logic_vector (5 downto 0) := "010010";
120 constant N3 : std_logic_vector (5 downto 0) := "010011";
121 constant N4 : std_logic_vector (5 downto 0) := "010100";
122 constant N5 : std_logic_vector (5 downto 0) := "010101";
124 --11xxx : irq cycle : T0 > I1 > I2 > I3 > I4 > I5 > T0
125 constant I1 : std_logic_vector (5 downto 0) := "011001";
126 constant I2 : std_logic_vector (5 downto 0) := "011010";
127 constant I3 : std_logic_vector (5 downto 0) := "011011";
128 constant I4 : std_logic_vector (5 downto 0) := "011100";
129 constant I5 : std_logic_vector (5 downto 0) := "011101";
131 constant ERROR_CYCLE : std_logic_vector (5 downto 0) := "111111";
133 -- SR Flags (bit 7 to bit 0):
138 -- 3 D .... Decimal (use BCD for arithmetics)
139 -- 2 I .... Interrupt (IRQ disable)
142 constant st_N : integer := 7;
143 constant st_V : integer := 6;
144 constant st_B : integer := 4;
145 constant st_D : integer := 3;
146 constant st_I : integer := 2;
147 constant st_Z : integer := 1;
148 constant st_C : integer := 0;
151 signal pch_inc_input : std_logic;
154 signal nmi_handled_n : std_logic;
156 -- page boundary handling
157 signal a2_abs_xy_next_cycle : std_logic_vector (5 downto 0);
158 signal a2_indir_y_next_cycle : std_logic_vector (5 downto 0);
159 signal wait_a2_abs_xy_next : std_logic;
160 signal wait_a2_indir_y_next : std_logic;
164 ---pc page next is connected to top bit of exec_cycle
165 pch_inc_input <= not exec_cycle(5);
166 pch_inc_reg : d_flip_flop_bit
167 port map(set_clk, '1', '1', '0', pch_inc_input, pch_inc_n);
169 a2_abs_xy_next_cycle <= T4 when ea_carry = '1' else
171 a2_indir_y_next_cycle <= T5 when ea_carry = '1' else
174 main_p : process (set_clk, res_n, nmi_n, a2_abs_xy_next_cycle, a2_indir_y_next_cycle)
176 -------------------------------------------------------------
177 -------------------------------------------------------------
178 ----------------------- comon routines ----------------------
179 -------------------------------------------------------------
180 -------------------------------------------------------------
182 ----------gate_cmd format
183 ------3 : front port oe_n
184 ------2 : front port we_n
185 ------1 : back port oe_n
186 ------0 : back port we_n
187 procedure front_oe (signal cmd : out std_logic_vector(3 downto 0);
188 val : in std_logic) is
192 procedure front_we (signal cmd : out std_logic_vector(3 downto 0);
193 val : in std_logic) is
197 procedure back_oe (signal cmd : out std_logic_vector(3 downto 0);
198 val : in std_logic) is
202 procedure back_we (signal cmd : out std_logic_vector(3 downto 0);
203 val : in std_logic) is
208 procedure fetch_next is
211 back_oe(pcl_cmd, '0');
212 back_oe(pch_cmd, '0');
213 back_we(pcl_cmd, '0');
214 back_we(pch_cmd, '1');
217 procedure fetch_stop is
220 back_oe(pcl_cmd, '1');
221 back_oe(pch_cmd, '1');
222 back_we(pcl_cmd, '1');
225 procedure read_status is
227 status_reg <= (others => 'Z');
228 stat_dec_oe_n <= '0';
231 procedure disable_pins is
233 --disable the last opration pins.
234 dbuf_int_oe_n <= '1';
258 stat_bus_oe_n <= '1';
259 stat_set_flg_n <= '1';
261 stat_bus_all_n <= '1';
262 stat_bus_nz_n <= '1';
263 stat_alu_we_n <= '1';
269 wait_a2_abs_xy_next <= '0';
270 wait_a2_indir_y_next <= '0';
273 procedure fetch_inst (inc_pcl : in std_logic) is
275 if instruction = conv_std_logic_vector(16#4c#, dsize) then
276 --if prior cycle is jump instruction,
277 --fetch opcode from where the latch is pointing to.
283 --fetch opcode and pcl increment.
291 pcl_inc_n <= inc_pcl;
294 d_print(string'("fetch 1"));
298 ---(along with the page boundary condition, the last
299 ---cycle is bypassed and slided to T0.)
300 procedure t0_cycle is
303 if (nmi_n = '0' and nmi_handled_n = '1') then
304 --start nmi handling...
313 ---common routine for single byte instruction.
314 procedure single_inst is
320 procedure fetch_imm is
322 d_print("immediate");
324 --send data from data bus buffer.
325 --receiver is instruction dependent.
326 dbuf_int_oe_n <= '0';
330 procedure set_nz_from_bus is
332 --status register n/z bit update.
333 stat_bus_nz_n <= '0';
336 procedure set_zc_from_alu is
338 --status register n/z bit update.
339 stat_alu_we_n <= '0';
340 stat_dec_oe_n <= '1';
341 status_reg <= "00000011";
344 procedure set_nz_from_alu is
346 --status register n/z/c bit update.
347 stat_alu_we_n <= '0';
348 stat_dec_oe_n <= '1';
349 status_reg <= "10000010";
352 procedure set_nzc_from_alu is
354 --status register n/z/c bit update.
355 stat_alu_we_n <= '0';
356 stat_dec_oe_n <= '1';
357 status_reg <= "10000011";
360 procedure set_nvz_from_alu is
362 --status register n/z/v bit update.
363 stat_alu_we_n <= '0';
364 stat_dec_oe_n <= '1';
365 status_reg <= "11000010";
368 procedure set_nvzc_from_alu is
370 stat_alu_we_n <= '0';
371 stat_dec_oe_n <= '1';
372 status_reg <= "11000011";
375 --flag on/off instruction
376 procedure set_flag (int_flg : in integer; val : in std_logic) is
378 stat_dec_oe_n <= '1';
379 stat_set_flg_n <= '0';
380 --specify which to set.
381 status_reg(7 downto int_flg + 1)
383 status_reg(int_flg - 1 downto 0)
385 status_reg(int_flg) <= '1';
390 procedure set_flag0 (val : in std_logic) is
392 stat_dec_oe_n <= '1';
393 stat_set_flg_n <= '0';
394 status_reg <= "00000001";
398 procedure fetch_low is
400 d_print("fetch low 2");
401 --fetch next opcode (abs low).
403 --latch abs low data.
404 dbuf_int_oe_n <= '0';
409 procedure abs_fetch_high is
411 d_print("abs (xy) 3");
416 dbuf_int_oe_n <= '0';
421 procedure abs_latch_out is
432 procedure ea_x_out is
434 -----calucurate and output effective addr
439 procedure ea_y_out is
445 --A.2. internal execution on memory data
449 if exec_cycle = T1 then
451 elsif exec_cycle = T2 then
453 dbuf_int_oe_n <= '0';
465 if exec_cycle = T1 then
467 elsif exec_cycle = T2 then
469 elsif exec_cycle = T3 then
471 dbuf_int_oe_n <= '0';
476 procedure a2_page_next is
478 --close open gate if page boundary crossed.
479 back_we(acc_cmd, '1');
480 front_we(acc_cmd, '1');
481 front_we(x_cmd, '1');
482 front_we(y_cmd, '1');
483 stat_alu_we_n <= '1';
486 procedure a2_abs_xy (is_x : in boolean) is
488 if exec_cycle = T1 then
490 elsif exec_cycle = T2 then
492 elsif exec_cycle = T3 then
496 if (is_x = true) then
501 dbuf_int_oe_n <= '0';
503 wait_a2_abs_xy_next <= '1';
504 next_cycle <= a2_abs_xy_next_cycle;
505 d_print("absx step 1");
506 elsif exec_cycle = T4 then
507 --case page boundary crossed.
509 d_print("absx 5 (page boudary crossed.)");
511 pg_next_n <= not ea_carry;
516 procedure a2_zp_xy (is_x : in boolean) is
518 if exec_cycle = T1 then
520 elsif exec_cycle = T2 then
523 dbuf_int_oe_n <= '0';
530 elsif exec_cycle = T3 then
533 if (is_x = true) then
542 procedure a2_indir_y is
544 if exec_cycle = T1 then
549 elsif exec_cycle = T2 then
557 dbuf_int_oe_n <= '0';
560 elsif exec_cycle = T3 then
564 dbuf_int_oe_n <= '0';
567 elsif exec_cycle = T4 then
569 dbuf_int_oe_n <= '1';
575 dbuf_int_oe_n <= '0';
577 wait_a2_indir_y_next <= '1';
578 next_cycle <= a2_indir_y_next_cycle;
579 elsif exec_cycle = T5 then
580 --case page boundary crossed.
582 d_print("(indir), y (page boudary crossed.)");
584 pg_next_n <= not ea_carry;
589 --A.3. store operation.
593 if exec_cycle = T1 then
595 elsif exec_cycle = T2 then
597 dbuf_int_oe_n <= '1';
610 if exec_cycle = T1 then
612 elsif exec_cycle = T2 then
614 elsif exec_cycle = T3 then
616 dbuf_int_oe_n <= '1';
622 procedure a3_abs_xy (is_x : in boolean) is
624 if exec_cycle = T1 then
626 elsif exec_cycle = T2 then
628 elsif exec_cycle = T3 then
632 dbuf_int_oe_n <= '1';
633 if (is_x = true) then
639 elsif exec_cycle = T4 then
640 pg_next_n <= not ea_carry;
642 if (is_x = true) then
653 procedure a3_indir_y is
655 if exec_cycle = T1 then
660 elsif exec_cycle = T2 then
668 dbuf_int_oe_n <= '0';
671 elsif exec_cycle = T3 then
675 dbuf_int_oe_n <= '0';
678 elsif exec_cycle = T4 then
680 dbuf_int_oe_n <= '1';
688 elsif exec_cycle = T5 then
692 pg_next_n <= not ea_carry;
699 ---A.4. read-modify-write operation
703 if exec_cycle = T1 then
705 elsif exec_cycle = T2 then
707 dbuf_int_oe_n <= '1';
714 elsif exec_cycle = T3 then
717 --keep data in the alu reg.
719 dbuf_int_oe_n <= '0';
721 elsif exec_cycle = T4 then
722 dbuf_int_oe_n <= '1';
724 --t5 cycle writes modified value.
736 if exec_cycle = T1 then
738 elsif exec_cycle = T2 then
740 elsif exec_cycle = T3 then
741 --T3 cycle do nothing.
744 elsif exec_cycle = T4 then
747 --t4 cycle save data in the alu register only.
748 --hardware maunual says write original data,
749 --but this implementation doesn't write because bus shortage....
752 elsif exec_cycle = T5 then
753 dbuf_int_oe_n <= '1';
755 --t5 cycle writes modified value.
762 procedure a4_abs_x is
764 if exec_cycle = T1 then
766 elsif exec_cycle = T2 then
768 elsif exec_cycle = T3 then
769 --T3 cycle discarded.
773 dbuf_int_oe_n <= '0';
776 elsif exec_cycle = T4 then
777 --t4 cycle fetch only.
780 pg_next_n <= not ea_carry;
783 elsif exec_cycle = T5 then
784 --t4 cycle redo fetch and save data in the alu register only.
788 elsif exec_cycle = T6 then
789 --t5 cycle writes modified value.
792 dbuf_int_oe_n <= '1';
800 procedure a51_push is
802 if exec_cycle = T1 then
805 elsif exec_cycle = T2 then
806 back_oe(sp_cmd, '0');
807 back_we(sp_cmd, '0');
816 procedure a52_pull is
818 if exec_cycle = T1 then
822 elsif exec_cycle = T2 then
823 --stack decrement first.
824 back_oe(sp_cmd, '0');
825 back_we(sp_cmd, '0');
830 elsif exec_cycle = T3 then
832 back_we(sp_cmd, '1');
834 ---pop data from stack.
835 back_oe(sp_cmd, '0');
837 dbuf_int_oe_n <= '0';
843 -- A.5.8 branch operations
845 procedure a58_branch (int_flg : in integer; br_cond : in std_logic) is
847 if exec_cycle = T1 then
849 if status_reg(int_flg) = br_cond then
853 dbuf_int_oe_n <= '0';
857 d_print("no branch");
860 elsif exec_cycle = T2 then
863 dbuf_int_oe_n <= '1';
866 --calc relative addr.
870 back_oe(pcl_cmd, '0');
871 back_oe(pch_cmd, '0');
872 back_we(pcl_cmd, '0');
875 elsif exec_cycle = T3 then
876 if ea_carry = '1' then
877 d_print("page crossed.");
878 --page crossed. adh calc.
879 back_we(pcl_cmd, '1');
880 back_oe(pcl_cmd, '0');
881 back_oe(pch_cmd, '0');
882 back_we(pch_cmd, '0');
886 pg_next_n <= not ea_carry;
890 --fetch cycle is done.
896 -------------------------------------------------------------
897 -------------------------------------------------------------
898 ---------------- main state machine start.... ---------------
899 -------------------------------------------------------------
900 -------------------------------------------------------------
903 if (res_n = '0') then
904 --pc l/h is reset vector.
908 elsif (res_n'event and res_n = '1') then
913 if (nmi_n'event and nmi_n = '1') then
914 --reset nmi handle status
915 nmi_handled_n <= '1';
919 if (a2_abs_xy_next_cycle'event) then
920 if (wait_a2_abs_xy_next = '1') then
921 d_print("absx step 2");
922 next_cycle <= a2_abs_xy_next_cycle;
923 if (ea_carry = '1') then
929 if (a2_indir_y_next_cycle'event) then
930 if (wait_a2_indir_y_next = '1') then
931 next_cycle <= a2_indir_y_next_cycle;
932 if (ea_carry = '1') then
938 if (set_clk'event and set_clk = '1' and res_n = '1') then
939 d_print(string'("-"));
941 if exec_cycle = T0 then
945 elsif exec_cycle = T1 or exec_cycle = T2 or exec_cycle = T3 or
946 exec_cycle = T4 or exec_cycle = T5 or exec_cycle = T6 then
949 ---asyncronous page change might happen.
950 back_we(pch_cmd, '1');
952 if exec_cycle = T1 then
953 d_print("decode and execute inst: "
954 & conv_hex8(conv_integer(instruction)));
955 --disable pin for jmp instruction
957 back_we(pcl_cmd, '1');
958 front_we(pch_cmd, '1');
960 --grab instruction register data.
964 --imelementation is wriiten in the order of hardware manual
967 ----------------------------------------
968 --A.1. Single byte instruction.
969 ----------------------------------------
970 if instruction = conv_std_logic_vector(16#0a#, dsize) then
974 back_oe(acc_cmd, '0');
975 front_we(acc_cmd, '0');
979 elsif instruction = conv_std_logic_vector(16#18#, dsize) then
984 elsif instruction = conv_std_logic_vector(16#d8#, dsize) then
986 set_flag (st_D, '0');
989 elsif instruction = conv_std_logic_vector(16#58#, dsize) then
991 set_flag (st_I, '0');
994 elsif instruction = conv_std_logic_vector(16#b8#, dsize) then
996 set_flag (st_V, '0');
999 elsif instruction = conv_std_logic_vector(16#ca#, dsize) then
1002 back_oe(x_cmd, '0');
1003 front_we(x_cmd, '0');
1008 elsif instruction = conv_std_logic_vector(16#88#, dsize) then
1011 back_oe(y_cmd, '0');
1012 front_we(y_cmd, '0');
1017 elsif instruction = conv_std_logic_vector(16#e8#, dsize) then
1020 back_oe(x_cmd, '0');
1021 front_we(x_cmd, '0');
1026 elsif instruction = conv_std_logic_vector(16#c8#, dsize) then
1029 back_oe(y_cmd, '0');
1030 front_we(y_cmd, '0');
1034 elsif instruction = conv_std_logic_vector(16#4a#, dsize) then
1038 back_oe(acc_cmd, '0');
1039 front_we(acc_cmd, '0');
1043 elsif instruction = conv_std_logic_vector(16#ea#, dsize) then
1047 elsif instruction = conv_std_logic_vector(16#2a#, dsize) then
1051 back_oe(acc_cmd, '0');
1052 front_we(acc_cmd, '0');
1056 elsif instruction = conv_std_logic_vector(16#6a#, dsize) then
1060 back_oe(acc_cmd, '0');
1061 front_we(acc_cmd, '0');
1065 elsif instruction = conv_std_logic_vector(16#38#, dsize) then
1070 elsif instruction = conv_std_logic_vector(16#f8#, dsize) then
1072 set_flag (st_D, '1');
1075 elsif instruction = conv_std_logic_vector(16#78#, dsize) then
1077 set_flag (st_I, '1');
1080 elsif instruction = conv_std_logic_vector(16#aa#, dsize) then
1084 front_oe(acc_cmd, '0');
1085 front_we(x_cmd, '0');
1087 elsif instruction = conv_std_logic_vector(16#a8#, dsize) then
1091 front_oe(acc_cmd, '0');
1092 front_we(y_cmd, '0');
1094 elsif instruction = conv_std_logic_vector(16#ba#, dsize) then
1098 elsif instruction = conv_std_logic_vector(16#8a#, dsize) then
1102 front_oe(x_cmd, '0');
1103 front_we(acc_cmd, '0');
1105 elsif instruction = conv_std_logic_vector(16#9a#, dsize) then
1109 front_oe(x_cmd, '0');
1110 front_we(sp_cmd, '0');
1112 elsif instruction = conv_std_logic_vector(16#98#, dsize) then
1116 front_oe(y_cmd, '0');
1117 front_we(acc_cmd, '0');
1121 ----------------------------------------
1122 --A.2. internal execution on memory data
1123 ----------------------------------------
1124 elsif instruction = conv_std_logic_vector(16#69#, dsize) then
1129 back_oe(acc_cmd, '0');
1130 back_we(acc_cmd, '0');
1133 elsif instruction = conv_std_logic_vector(16#65#, dsize) then
1137 if exec_cycle = T2 then
1139 back_oe(acc_cmd, '0');
1140 back_we(acc_cmd, '0');
1144 elsif instruction = conv_std_logic_vector(16#75#, dsize) then
1148 if exec_cycle = T3 then
1150 back_oe(acc_cmd, '0');
1151 back_we(acc_cmd, '0');
1155 elsif instruction = conv_std_logic_vector(16#6d#, dsize) then
1159 if exec_cycle = T3 then
1161 back_oe(acc_cmd, '0');
1162 back_we(acc_cmd, '0');
1166 elsif instruction = conv_std_logic_vector(16#7d#, dsize) then
1170 if exec_cycle = T3 or exec_cycle = T4 then
1172 back_oe(acc_cmd, '0');
1173 back_we(acc_cmd, '0');
1177 elsif instruction = conv_std_logic_vector(16#79#, dsize) then
1181 if exec_cycle = T3 or exec_cycle = T4 then
1183 back_oe(acc_cmd, '0');
1184 back_we(acc_cmd, '0');
1188 elsif instruction = conv_std_logic_vector(16#61#, dsize) then
1192 elsif instruction = conv_std_logic_vector(16#71#, dsize) then
1196 if exec_cycle = T4 or exec_cycle = T5 then
1198 back_oe(acc_cmd, '0');
1199 back_we(acc_cmd, '0');
1203 elsif instruction = conv_std_logic_vector(16#29#, dsize) then
1208 back_oe(acc_cmd, '0');
1209 back_we(acc_cmd, '0');
1212 elsif instruction = conv_std_logic_vector(16#25#, dsize) then
1216 if exec_cycle = T2 then
1218 back_oe(acc_cmd, '0');
1219 back_we(acc_cmd, '0');
1223 elsif instruction = conv_std_logic_vector(16#35#, dsize) then
1227 if exec_cycle = T3 then
1229 back_oe(acc_cmd, '0');
1230 back_we(acc_cmd, '0');
1234 elsif instruction = conv_std_logic_vector(16#2d#, dsize) then
1238 if exec_cycle = T3 then
1240 back_oe(acc_cmd, '0');
1241 back_we(acc_cmd, '0');
1245 elsif instruction = conv_std_logic_vector(16#3d#, dsize) then
1249 if exec_cycle = T3 or exec_cycle = T4 then
1251 back_oe(acc_cmd, '0');
1252 back_we(acc_cmd, '0');
1256 elsif instruction = conv_std_logic_vector(16#39#, dsize) then
1260 if exec_cycle = T3 or exec_cycle = T4 then
1262 back_oe(acc_cmd, '0');
1263 back_we(acc_cmd, '0');
1267 elsif instruction = conv_std_logic_vector(16#21#, dsize) then
1271 elsif instruction = conv_std_logic_vector(16#31#, dsize) then
1275 if exec_cycle = T4 or exec_cycle = T5 then
1277 back_oe(acc_cmd, '0');
1278 back_we(acc_cmd, '0');
1282 elsif instruction = conv_std_logic_vector(16#24#, dsize) then
1286 if exec_cycle = T2 then
1288 back_oe(acc_cmd, '0');
1292 elsif instruction = conv_std_logic_vector(16#2c#, dsize) then
1296 if exec_cycle = T3 then
1298 back_oe(acc_cmd, '0');
1302 elsif instruction = conv_std_logic_vector(16#c9#, dsize) then
1307 back_oe(acc_cmd, '0');
1310 elsif instruction = conv_std_logic_vector(16#c5#, dsize) then
1314 if exec_cycle = T2 then
1316 back_oe(acc_cmd, '0');
1320 elsif instruction = conv_std_logic_vector(16#d5#, dsize) then
1324 if exec_cycle = T3 then
1326 back_oe(acc_cmd, '0');
1330 elsif instruction = conv_std_logic_vector(16#cd#, dsize) then
1334 if exec_cycle = T3 then
1336 back_oe(acc_cmd, '0');
1340 elsif instruction = conv_std_logic_vector(16#dd#, dsize) then
1344 if exec_cycle = T3 or exec_cycle = T4 then
1346 back_oe(acc_cmd, '0');
1350 elsif instruction = conv_std_logic_vector(16#d9#, dsize) then
1354 if exec_cycle = T3 or exec_cycle = T4 then
1356 back_oe(acc_cmd, '0');
1360 elsif instruction = conv_std_logic_vector(16#c1#, dsize) then
1364 elsif instruction = conv_std_logic_vector(16#d1#, dsize) then
1368 if exec_cycle = T4 or exec_cycle = T5 then
1370 back_oe(acc_cmd, '0');
1374 elsif instruction = conv_std_logic_vector(16#e0#, dsize) then
1379 back_oe(x_cmd, '0');
1382 elsif instruction = conv_std_logic_vector(16#e4#, dsize) then
1386 if exec_cycle = T2 then
1388 back_oe(x_cmd, '0');
1392 elsif instruction = conv_std_logic_vector(16#ec#, dsize) then
1396 elsif instruction = conv_std_logic_vector(16#c0#, dsize) then
1401 back_oe(y_cmd, '0');
1404 elsif instruction = conv_std_logic_vector(16#c4#, dsize) then
1408 elsif instruction = conv_std_logic_vector(16#cc#, dsize) then
1412 elsif instruction = conv_std_logic_vector(16#49#, dsize) then
1417 back_oe(acc_cmd, '0');
1418 back_we(acc_cmd, '0');
1421 elsif instruction = conv_std_logic_vector(16#45#, dsize) then
1425 if exec_cycle = T2 then
1427 back_oe(acc_cmd, '0');
1428 back_we(acc_cmd, '0');
1432 elsif instruction = conv_std_logic_vector(16#55#, dsize) then
1436 elsif instruction = conv_std_logic_vector(16#4d#, dsize) then
1440 elsif instruction = conv_std_logic_vector(16#5d#, dsize) then
1444 elsif instruction = conv_std_logic_vector(16#59#, dsize) then
1448 elsif instruction = conv_std_logic_vector(16#41#, dsize) then
1452 elsif instruction = conv_std_logic_vector(16#51#, dsize) then
1456 elsif instruction = conv_std_logic_vector(16#a9#, dsize) then
1460 front_we(acc_cmd, '0');
1463 elsif instruction = conv_std_logic_vector(16#a5#, dsize) then
1467 if exec_cycle = T2 then
1468 front_we(acc_cmd, '0');
1472 elsif instruction = conv_std_logic_vector(16#b5#, dsize) then
1476 if exec_cycle = T3 then
1477 front_we(acc_cmd, '0');
1481 elsif instruction = conv_std_logic_vector(16#ad#, dsize) then
1485 if exec_cycle = T3 then
1487 front_we(acc_cmd, '0');
1490 elsif instruction = conv_std_logic_vector(16#bd#, dsize) then
1494 if exec_cycle = T3 or exec_cycle = T4 then
1496 front_we(acc_cmd, '0');
1500 elsif instruction = conv_std_logic_vector(16#b9#, dsize) then
1504 if exec_cycle = T3 or exec_cycle = T4 then
1506 front_we(acc_cmd, '0');
1510 elsif instruction = conv_std_logic_vector(16#a1#, dsize) then
1514 elsif instruction = conv_std_logic_vector(16#b1#, dsize) then
1518 if exec_cycle = T4 or exec_cycle = T5 then
1520 front_we(acc_cmd, '0');
1524 elsif instruction = conv_std_logic_vector(16#a2#, dsize) then
1529 front_we(x_cmd, '0');
1531 elsif instruction = conv_std_logic_vector(16#a6#, dsize) then
1535 if exec_cycle = T2 then
1536 front_we(x_cmd, '0');
1540 elsif instruction = conv_std_logic_vector(16#b6#, dsize) then
1544 elsif instruction = conv_std_logic_vector(16#ae#, dsize) then
1548 if exec_cycle = T3 then
1550 front_we(x_cmd, '0');
1553 elsif instruction = conv_std_logic_vector(16#be#, dsize) then
1557 if exec_cycle = T3 or exec_cycle = T4 then
1558 front_we(x_cmd, '0');
1562 elsif instruction = conv_std_logic_vector(16#a0#, dsize) then
1567 front_we(y_cmd, '0');
1569 elsif instruction = conv_std_logic_vector(16#a4#, dsize) then
1573 if exec_cycle = T2 then
1574 front_we(y_cmd, '0');
1578 elsif instruction = conv_std_logic_vector(16#b4#, dsize) then
1582 if exec_cycle = T3 then
1583 front_we(y_cmd, '0');
1587 elsif instruction = conv_std_logic_vector(16#ac#, dsize) then
1591 if exec_cycle = T3 then
1593 front_we(y_cmd, '0');
1596 elsif instruction = conv_std_logic_vector(16#bc#, dsize) then
1600 elsif instruction = conv_std_logic_vector(16#09#, dsize) then
1605 back_oe(acc_cmd, '0');
1606 back_we(acc_cmd, '0');
1609 elsif instruction = conv_std_logic_vector(16#05#, dsize) then
1613 if exec_cycle = T2 then
1615 back_oe(acc_cmd, '0');
1616 back_we(acc_cmd, '0');
1620 elsif instruction = conv_std_logic_vector(16#15#, dsize) then
1624 elsif instruction = conv_std_logic_vector(16#0d#, dsize) then
1628 elsif instruction = conv_std_logic_vector(16#1d#, dsize) then
1632 elsif instruction = conv_std_logic_vector(16#19#, dsize) then
1636 elsif instruction = conv_std_logic_vector(16#01#, dsize) then
1640 elsif instruction = conv_std_logic_vector(16#11#, dsize) then
1644 elsif instruction = conv_std_logic_vector(16#e9#, dsize) then
1649 back_oe(acc_cmd, '0');
1650 back_we(acc_cmd, '0');
1653 elsif instruction = conv_std_logic_vector(16#e5#, dsize) then
1657 elsif instruction = conv_std_logic_vector(16#f5#, dsize) then
1661 elsif instruction = conv_std_logic_vector(16#ed#, dsize) then
1665 elsif instruction = conv_std_logic_vector(16#fd#, dsize) then
1669 elsif instruction = conv_std_logic_vector(16#f9#, dsize) then
1673 if exec_cycle = T3 or exec_cycle = T4 then
1675 back_oe(acc_cmd, '0');
1676 back_we(acc_cmd, '0');
1680 elsif instruction = conv_std_logic_vector(16#e1#, dsize) then
1684 elsif instruction = conv_std_logic_vector(16#f1#, dsize) then
1690 ----------------------------------------
1691 ---A.3. store operation.
1692 ----------------------------------------
1693 elsif instruction = conv_std_logic_vector(16#85#, dsize) then
1697 if exec_cycle = T2 then
1698 front_oe(acc_cmd, '0');
1701 elsif instruction = conv_std_logic_vector(16#95#, dsize) then
1705 elsif instruction = conv_std_logic_vector(16#8d#, dsize) then
1709 if exec_cycle = T3 then
1710 front_oe(acc_cmd, '0');
1713 elsif instruction = conv_std_logic_vector(16#9d#, dsize) then
1717 if exec_cycle = T4 then
1718 front_oe(acc_cmd, '0');
1721 elsif instruction = conv_std_logic_vector(16#99#, dsize) then
1725 if exec_cycle = T4 then
1726 front_oe(acc_cmd, '0');
1729 elsif instruction = conv_std_logic_vector(16#81#, dsize) then
1733 elsif instruction = conv_std_logic_vector(16#91#, dsize) then
1737 if exec_cycle = T5 then
1738 front_oe(acc_cmd, '0');
1741 elsif instruction = conv_std_logic_vector(16#86#, dsize) then
1745 if exec_cycle = T2 then
1746 front_oe(x_cmd, '0');
1749 elsif instruction = conv_std_logic_vector(16#96#, dsize) then
1753 elsif instruction = conv_std_logic_vector(16#8e#, dsize) then
1757 if exec_cycle = T3 then
1758 front_oe(x_cmd, '0');
1761 elsif instruction = conv_std_logic_vector(16#84#, dsize) then
1765 if exec_cycle = T2 then
1766 front_oe(y_cmd, '0');
1769 elsif instruction = conv_std_logic_vector(16#94#, dsize) then
1773 elsif instruction = conv_std_logic_vector(16#8c#, dsize) then
1777 if exec_cycle = T3 then
1778 front_oe(y_cmd, '0');
1782 ----------------------------------------
1783 ---A.4. read-modify-write operation
1784 ----------------------------------------
1785 elsif instruction = conv_std_logic_vector(16#06#, dsize) then
1789 elsif instruction = conv_std_logic_vector(16#16#, dsize) then
1793 elsif instruction = conv_std_logic_vector(16#0e#, dsize) then
1797 elsif instruction = conv_std_logic_vector(16#1e#, dsize) then
1801 elsif instruction = conv_std_logic_vector(16#c6#, dsize) then
1805 if exec_cycle = T4 then
1809 elsif instruction = conv_std_logic_vector(16#d6#, dsize) then
1813 elsif instruction = conv_std_logic_vector(16#ce#, dsize) then
1817 if exec_cycle = T5 then
1821 elsif instruction = conv_std_logic_vector(16#de#, dsize) then
1825 elsif instruction = conv_std_logic_vector(16#e6#, dsize) then
1829 if exec_cycle = T4 then
1833 elsif instruction = conv_std_logic_vector(16#f6#, dsize) then
1837 elsif instruction = conv_std_logic_vector(16#ee#, dsize) then
1841 if exec_cycle = T5 then
1845 elsif instruction = conv_std_logic_vector(16#fe#, dsize) then
1849 elsif instruction = conv_std_logic_vector(16#46#, dsize) then
1853 elsif instruction = conv_std_logic_vector(16#56#, dsize) then
1857 elsif instruction = conv_std_logic_vector(16#4e#, dsize) then
1861 elsif instruction = conv_std_logic_vector(16#5e#, dsize) then
1865 elsif instruction = conv_std_logic_vector(16#26#, dsize) then
1869 elsif instruction = conv_std_logic_vector(16#36#, dsize) then
1873 elsif instruction = conv_std_logic_vector(16#2e#, dsize) then
1877 elsif instruction = conv_std_logic_vector(16#3e#, dsize) then
1881 elsif instruction = conv_std_logic_vector(16#66#, dsize) then
1885 -- if exec_cycle = T4 then
1886 -- set_nzc_from_alu;
1889 elsif instruction = conv_std_logic_vector(16#76#, dsize) then
1893 elsif instruction = conv_std_logic_vector(16#6e#, dsize) then
1897 elsif instruction = conv_std_logic_vector(16#7e#, dsize) then
1901 if exec_cycle = T6 then
1906 ----------------------------------------
1907 --A.5. miscellaneous oprations.
1908 ----------------------------------------
1911 elsif instruction = conv_std_logic_vector(16#08#, dsize) then
1914 elsif instruction = conv_std_logic_vector(16#48#, dsize) then
1917 if exec_cycle = T2 then
1918 front_oe(acc_cmd, '0');
1921 elsif instruction = conv_std_logic_vector(16#28#, dsize) then
1924 elsif instruction = conv_std_logic_vector(16#68#, dsize) then
1927 if exec_cycle = T3 then
1928 front_we(acc_cmd, '0');
1932 ----------------------------------------
1934 ----------------------------------------
1935 elsif instruction = conv_std_logic_vector(16#20#, dsize) then
1936 if exec_cycle = T1 then
1937 d_print("jsr abs 2");
1940 dbuf_int_oe_n <= '0';
1944 elsif exec_cycle = T2 then
1947 dbuf_int_oe_n <= '1';
1950 --push return addr high into stack.
1953 front_oe(pch_cmd, '0');
1954 back_oe(sp_cmd, '0');
1955 back_we(sp_cmd, '0');
1958 elsif exec_cycle = T3 then
1960 front_oe(pch_cmd, '1');
1962 --push return addr low into stack.
1965 front_oe(pcl_cmd, '0');
1966 back_oe(sp_cmd, '0');
1967 back_we(sp_cmd, '0');
1971 elsif exec_cycle = T4 then
1975 front_oe(pcl_cmd, '1');
1976 back_oe(sp_cmd, '1');
1977 back_we(sp_cmd, '1');
1981 back_oe(pch_cmd, '0');
1982 back_oe(pcl_cmd, '0');
1983 dbuf_int_oe_n <= '0';
1987 elsif exec_cycle = T5 then
1990 back_oe(pch_cmd, '1');
1991 back_oe(pcl_cmd, '1');
1992 dbuf_int_oe_n <= '1';
1998 front_we(pch_cmd, '0');
2002 back_we(pcl_cmd, '0');
2005 end if; --if exec_cycle = T1 then
2008 elsif instruction = conv_std_logic_vector(16#00#, dsize) then
2010 ----------------------------------------
2011 -- A.5.5 return from interrupt
2012 ----------------------------------------
2013 elsif instruction = conv_std_logic_vector(16#40#, dsize) then
2014 if exec_cycle = T1 then
2018 --pop stack (decrement only)
2019 back_oe(sp_cmd, '0');
2020 back_we(sp_cmd, '0');
2025 elsif exec_cycle = T2 then
2029 back_oe(sp_cmd, '0');
2030 back_we(sp_cmd, '0');
2035 stat_dec_oe_n <= '1';
2036 dbuf_int_oe_n <= '0';
2037 stat_bus_all_n <= '0';
2040 elsif exec_cycle = T3 then
2042 stat_bus_all_n <= '1';
2045 back_oe(sp_cmd, '0');
2046 back_we(sp_cmd, '0');
2051 dbuf_int_oe_n <= '0';
2052 front_we(pcl_cmd, '0');
2055 elsif exec_cycle = T4 then
2057 --stack decrement stop.
2058 back_we(sp_cmd, '1');
2060 front_we(pcl_cmd, '1');
2063 back_oe(sp_cmd, '0');
2066 dbuf_int_oe_n <= '0';
2067 front_we(pch_cmd, '0');
2070 elsif exec_cycle = T5 then
2072 back_oe(sp_cmd, '1');
2075 dbuf_int_oe_n <= '1';
2076 front_we(pch_cmd, '1');
2080 end if; --if exec_cycle = T1 then
2082 ----------------------------------------
2084 ----------------------------------------
2085 elsif instruction = conv_std_logic_vector(16#4c#, dsize) then
2087 if exec_cycle = T1 then
2089 --fetch next opcode (abs low).
2092 --latch abs low data.
2093 dbuf_int_oe_n <= '0';
2096 elsif exec_cycle = T2 then
2104 dbuf_int_oe_n <= '0';
2107 front_we(pch_cmd, '0');
2112 elsif instruction = conv_std_logic_vector(16#6c#, dsize) then
2114 if exec_cycle = T1 then
2116 --fetch next opcode (abs low).
2119 --latch abs low data.
2120 dbuf_int_oe_n <= '0';
2123 elsif exec_cycle = T2 then
2131 dbuf_int_oe_n <= '0';
2135 elsif exec_cycle = T3 then
2142 front_we(pcl_cmd, '0');
2145 elsif exec_cycle = T4 then
2148 front_we(pcl_cmd, '1');
2151 front_we(pch_cmd, '0');
2159 ----------------------------------------
2160 -- A.5.7 return from soubroutine
2161 ----------------------------------------
2162 elsif instruction = conv_std_logic_vector(16#60#, dsize) then
2163 if exec_cycle = T1 then
2167 --pop stack (decrement only)
2168 back_oe(sp_cmd, '0');
2169 back_we(sp_cmd, '0');
2174 elsif exec_cycle = T2 then
2178 back_oe(sp_cmd, '0');
2179 back_we(sp_cmd, '0');
2184 dbuf_int_oe_n <= '0';
2185 front_we(pcl_cmd, '0');
2188 elsif exec_cycle = T3 then
2190 --stack decrement stop.
2191 back_we(sp_cmd, '1');
2193 front_we(pcl_cmd, '1');
2196 back_oe(sp_cmd, '0');
2199 dbuf_int_oe_n <= '0';
2200 front_we(pch_cmd, '0');
2203 elsif exec_cycle = T4 then
2205 back_oe(sp_cmd, '1');
2208 dbuf_int_oe_n <= '1';
2209 front_we(pch_cmd, '1');
2211 --complying h/w manual...
2213 elsif exec_cycle = T5 then
2219 end if; --if exec_cycle = T1 then
2221 ----------------------------------------
2222 -- A.5.8 branch operations
2223 ----------------------------------------
2224 elsif instruction = conv_std_logic_vector(16#90#, dsize) then
2226 a58_branch (st_C, '0');
2228 elsif instruction = conv_std_logic_vector(16#b0#, dsize) then
2230 a58_branch (st_C, '1');
2232 elsif instruction = conv_std_logic_vector(16#f0#, dsize) then
2234 a58_branch (st_Z, '1');
2236 elsif instruction = conv_std_logic_vector(16#30#, dsize) then
2238 a58_branch (st_N, '1');
2240 elsif instruction = conv_std_logic_vector(16#d0#, dsize) then
2242 a58_branch (st_Z, '0');
2244 elsif instruction = conv_std_logic_vector(16#10#, dsize) then
2246 a58_branch (st_N, '0');
2248 elsif instruction = conv_std_logic_vector(16#50#, dsize) then
2250 elsif instruction = conv_std_logic_vector(16#70#, dsize) then
2254 ---unknown instruction!!!!
2256 report "======== unknow instruction "
2257 & conv_hex8(conv_integer(instruction))
2259 end if; --if instruction = conv_std_logic_vector(16#0a#, dsize)
2261 elsif exec_cycle = R0 then
2262 d_print(string'("reset"));
2264 front_we(pch_cmd, '1');
2265 back_we(pcl_cmd, '1');
2267 --initialize port...
2270 dbuf_int_oe_n <= '1';
2297 stat_dec_oe_n <= '1';
2298 stat_bus_oe_n <= '1';
2299 stat_set_flg_n <= '1';
2301 stat_bus_all_n <= '1';
2302 stat_bus_nz_n <= '1';
2303 stat_alu_we_n <= '1';
2308 nmi_handled_n <= '1';
2312 elsif exec_cycle = R1 or exec_cycle = N1 then
2324 --front_oe(pch_cmd, '0');
2325 back_oe(sp_cmd, '0');
2326 back_we(sp_cmd, '0');
2329 if exec_cycle = R1 then
2331 elsif exec_cycle = N1 then
2335 elsif exec_cycle = R2 or exec_cycle = N2 then
2336 front_oe(pch_cmd, '1');
2341 front_oe(pcl_cmd, '0');
2342 back_oe(sp_cmd, '0');
2343 back_we(sp_cmd, '0');
2346 if exec_cycle = R2 then
2348 elsif exec_cycle = N2 then
2352 elsif exec_cycle = R3 or exec_cycle = N3 then
2353 front_oe(pcl_cmd, '1');
2358 stat_bus_oe_n <= '0';
2359 back_oe(sp_cmd, '0');
2360 back_we(sp_cmd, '0');
2363 if exec_cycle = R3 then
2365 elsif exec_cycle = N3 then
2369 elsif exec_cycle = R4 or exec_cycle = N4 then
2370 stat_bus_oe_n <= '1';
2373 front_oe(pcl_cmd, '1');
2374 back_oe(sp_cmd, '1');
2375 back_we(sp_cmd, '1');
2377 --fetch reset vector low
2379 dbuf_int_oe_n <= '0';
2380 front_we(pcl_cmd, '0');
2382 if exec_cycle = R4 then
2385 elsif exec_cycle = N4 then
2390 elsif exec_cycle = R5 or exec_cycle = N5 then
2391 front_we(pcl_cmd, '1');
2393 --fetch reset vector hi
2394 front_we(pch_cmd, '0');
2397 if exec_cycle = N5 then
2398 nmi_handled_n <= '0';
2400 --start execute cycle.
2403 elsif exec_cycle(5) = '1' then
2404 ---pc increment and next page.
2405 d_print(string'("pch next page..."));
2406 --pcl stop increment
2408 back_we(pcl_cmd, '1');
2410 back_we(pch_cmd, '0');
2411 back_oe(pch_cmd, '0');
2413 if ('0' & exec_cycle(4 downto 0) = T0) then
2414 --do the t0 identical routine.
2419 elsif ('0' & exec_cycle(4 downto 0) = T1) then
2420 --if fetch cycle, preserve instrution register
2423 --TODO: must handle for jmp case???
2424 elsif ('0' & exec_cycle(4 downto 0) = T2) then
2425 --disable previous we_n gate.
2426 --t1 cycle is fetch low oprand.
2428 elsif ('0' & exec_cycle(4 downto 0) = T3) then
2429 --t2 cycle is fetch high oprand.
2433 end if; --if exec_cycle = T0 then
2435 end if; --if (set_clk'event and set_clk = '1')