simulation/cpu/decoder.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_arith.conv_std_logic_vector;
   4 use ieee.std_logic_unsigned.conv_integer;
   5
   6 entity decoder is
   7     generic (dsize : integer := 8);
   8     port (  set_clk         : in std_logic;
   9             trig_clk        : in std_logic;
  10             res_n           : in std_logic;
  11             irq_n           : in std_logic;
  12             nmi_n           : in std_logic;
  13             rdy             : in std_logic;
  14             instruction     : in std_logic_vector (dsize - 1 downto 0);
  15             exec_cycle      : in std_logic_vector (5 downto 0);
  16             next_cycle      : out std_logic_vector (5 downto 0);
  17             status_reg      : inout std_logic_vector (dsize - 1 downto 0);
  18             inst_we_n       : out std_logic;
  19             ad_oe_n         : out std_logic;
  20             dbuf_int_oe_n   : out std_logic;
  21             dl_al_we_n      : out std_logic;
  22             dl_ah_we_n      : out std_logic;
  23             dl_al_oe_n      : out std_logic;
  24             dl_ah_oe_n      : out std_logic;
  25             dl_dh_oe_n      : out std_logic;
  26             pcl_inc_n       : out std_logic;
  27             pch_inc_n       : out std_logic;
  28             pcl_cmd         : out std_logic_vector(3 downto 0);
  29             pch_cmd         : out std_logic_vector(3 downto 0);
  30             sp_cmd          : out std_logic_vector(3 downto 0);
  31             sp_oe_n         : out std_logic;
  32             sp_push_n       : out std_logic;
  33             sp_pop_n        : out std_logic;
  34             acc_cmd         : out std_logic_vector(3 downto 0);
  35             x_cmd           : out std_logic_vector(3 downto 0);
  36             y_cmd           : out std_logic_vector(3 downto 0);
  37             abs_xy_n        : out std_logic;
  38             ea_carry        : in  std_logic;
  39             pg_next_n       : out std_logic;
  40             zp_n            : out std_logic;
  41             zp_xy_n         : out std_logic;
  42             rel_calc_n      : out std_logic;
  43             indir_n         : out std_logic;
  44             indir_x_n       : out std_logic;
  45             indir_y_n       : out std_logic;
  46             arith_en_n      : out std_logic;
  47             stat_dec_oe_n   : out std_logic;
  48             stat_bus_oe_n   : out std_logic;
  49             stat_set_flg_n  : out std_logic;
  50             stat_flg        : out std_logic;
  51             stat_bus_all_n  : out std_logic;
  52             stat_bus_nz_n   : out std_logic;
  53             stat_alu_we_n   : out std_logic;
  54             r_vec_oe_n      : out std_logic;
  55             n_vec_oe_n      : out std_logic;
  56             i_vec_oe_n      : out std_logic;
  57             r_nw            : out std_logic
  58             ;---for parameter check purpose!!!
  59             check_bit     : out std_logic_vector(1 to 5)
  60         );
  61 end decoder;
  62
  63 architecture rtl of decoder is
  64
  65 component d_flip_flop_bit
  66     port (
  67             clk     : in std_logic;
  68             res_n   : in std_logic;
  69             set_n   : in std_logic;
  70             we_n    : in std_logic;
  71             d       : in std_logic;
  72             q       : out std_logic
  73         );
  74 end component;
  75
  76 procedure d_print(msg : string) is
  77 use std.textio.all;
  78 use ieee.std_logic_textio.all;
  79 variable out_l : line;
  80 begin
  81     write(out_l, msg);
  82     writeline(output, out_l);
  83 end  procedure;
  84
  85 ---ival : 0x0000 - 0xffff
  86 function conv_hex8(ival : integer) return string is
  87 variable tmp1, tmp2 : integer;
  88 variable hex_chr: string (1 to 16) := "0123456789abcdef";
  89 begin
  90     tmp2 := (ival mod 16 ** 2) / 16 ** 1;
  91     tmp1 := ival mod 16 ** 1;
  92     return hex_chr(tmp2 + 1) & hex_chr(tmp1 + 1);
  93 end;
  94
  95 --cycle bit format
  96 -- bit 5    : pcl increment carry flag
  97 -- bit 4,3  : cycle type: 00 normal, 01 reset , 10 nmi, 11 irq
  98 -- bit 2-0  : cycle
  99
 100 --00xxx : exec cycle : T0 > T1 > T2 > T3 > T4 > T5 > T6 > T0
 101 constant T0 : std_logic_vector (5 downto 0) := "000000";
 102 constant T1 : std_logic_vector (5 downto 0) := "000001";
 103 constant T2 : std_logic_vector (5 downto 0) := "000010";
 104 constant T3 : std_logic_vector (5 downto 0) := "000011";
 105 constant T4 : std_logic_vector (5 downto 0) := "000100";
 106 constant T5 : std_logic_vector (5 downto 0) := "000101";
 107 constant T6 : std_logic_vector (5 downto 0) := "000110";
 108
 109 --01xxx : reset cycle : R0 > R1 > R2 > R3 > R4 > R5 > T0
 110 constant R0 : std_logic_vector (5 downto 0) := "001000";
 111 constant R1 : std_logic_vector (5 downto 0) := "001001";
 112 constant R2 : std_logic_vector (5 downto 0) := "001010";
 113 constant R3 : std_logic_vector (5 downto 0) := "001011";
 114 constant R4 : std_logic_vector (5 downto 0) := "001100";
 115 constant R5 : std_logic_vector (5 downto 0) := "001101";
 116
 117 --10xxx : nmi cycle : T0 > N1 > N2 > N3 > N4 > N5 > T0
 118 constant N1 : std_logic_vector (5 downto 0) := "010001";
 119 constant N2 : std_logic_vector (5 downto 0) := "010010";
 120 constant N3 : std_logic_vector (5 downto 0) := "010011";
 121 constant N4 : std_logic_vector (5 downto 0) := "010100";
 122 constant N5 : std_logic_vector (5 downto 0) := "010101";
 123
 124 --11xxx : irq cycle : T0 > I1 > I2 > I3 > I4 > I5 > T0
 125 constant I1 : std_logic_vector (5 downto 0) := "011001";
 126 constant I2 : std_logic_vector (5 downto 0) := "011010";
 127 constant I3 : std_logic_vector (5 downto 0) := "011011";
 128 constant I4 : std_logic_vector (5 downto 0) := "011100";
 129 constant I5 : std_logic_vector (5 downto 0) := "011101";
 130
 131 constant ERROR_CYCLE : std_logic_vector (5 downto 0) := "111111";
 132
 133 -- SR Flags (bit 7 to bit 0):
 134 --  7   N   ....    Negative
 135 --  6   V   ....    Overflow
 136 --  5   -   ....    ignored
 137 --  4   B   ....    Break
 138 --  3   D   ....    Decimal (use BCD for arithmetics)
 139 --  2   I   ....    Interrupt (IRQ disable)
 140 --  1   Z   ....    Zero
 141 --  0   C   ....    Carry
 142 constant st_N : integer := 7;
 143 constant st_V : integer := 6;
 144 constant st_B : integer := 4;
 145 constant st_D : integer := 3;
 146 constant st_I : integer := 2;
 147 constant st_Z : integer := 1;
 148 constant st_C : integer := 0;
 149
 150 ---for pch_inc_n.
 151 signal pch_inc_input : std_logic;
 152
 153 ---for nmi handling
 154 signal nmi_handled_n : std_logic;
 155
 156 -- page boundary handling
 157 signal a2_abs_xy_next_cycle     : std_logic_vector (5 downto 0);
 158 signal a2_indir_y_next_cycle    : std_logic_vector (5 downto 0);
 159 signal wait_a2_abs_xy_next      : std_logic;
 160 signal wait_a2_indir_y_next     : std_logic;
 161
 162 begin
 163
 164     ---pc page next is connected to top bit of exec_cycle
 165     pch_inc_input <= not exec_cycle(5);
 166     pch_inc_reg : d_flip_flop_bit
 167             port map(set_clk, '1', '1', '0', pch_inc_input, pch_inc_n);
 168
 169     a2_abs_xy_next_cycle <= T4 when ea_carry = '1' else
 170                     T0;
 171     a2_indir_y_next_cycle <= T5 when ea_carry = '1' else
 172                     T0;
 173
 174     main_p : process (set_clk, res_n, nmi_n, a2_abs_xy_next_cycle, a2_indir_y_next_cycle)
 175
 176 -------------------------------------------------------------
 177 -------------------------------------------------------------
 178 ----------------------- comon routines ----------------------
 179 -------------------------------------------------------------
 180 -------------------------------------------------------------
 181
 182 ----------gate_cmd format
 183 ------3 : front port oe_n
 184 ------2 : front port we_n
 185 ------1 : back port oe_n
 186 ------0 : back port we_n
 187 procedure front_oe (signal cmd : out std_logic_vector(3 downto 0);
 188     val : in std_logic) is
 189 begin
 190     cmd(3) <= val;
 191 end;
 192 procedure front_we (signal cmd : out std_logic_vector(3 downto 0);
 193     val : in std_logic) is
 194 begin
 195     cmd(2) <= val;
 196 end;
 197 procedure back_oe (signal cmd : out std_logic_vector(3 downto 0);
 198     val : in std_logic) is
 199 begin
 200     cmd(1) <= val;
 201 end;
 202 procedure back_we (signal cmd : out std_logic_vector(3 downto 0);
 203     val : in std_logic) is
 204 begin
 205     cmd(0) <= val;
 206 end;
 207
 208 procedure fetch_next is
 209 begin
 210     pcl_inc_n <= '0';
 211     back_oe(pcl_cmd, '0');
 212     back_oe(pch_cmd, '0');
 213     back_we(pcl_cmd, '0');
 214     back_we(pch_cmd, '1');
 215 end procedure;
 216
 217 procedure fetch_stop is
 218 begin
 219     pcl_inc_n <= '1';
 220     back_oe(pcl_cmd, '1');
 221     back_oe(pch_cmd, '1');
 222     back_we(pcl_cmd, '1');
 223 end procedure;
 224
 225 procedure read_status is
 226 begin
 227     status_reg <= (others => 'Z');
 228     stat_dec_oe_n <= '0';
 229 end  procedure;
 230
 231 procedure disable_pins is
 232 begin
 233     --disable the last opration pins.
 234     dbuf_int_oe_n <= '1';
 235     dl_al_we_n <= '1';
 236     dl_ah_we_n <= '1';
 237     dl_ah_oe_n <= '1';
 238     dl_dh_oe_n <= '1';
 239     sp_cmd <= "1111";
 240     sp_oe_n <= '1';
 241     sp_push_n <= '1';
 242     sp_pop_n <= '1';
 243     acc_cmd <= "1111";
 244     x_cmd <= "1111";
 245     y_cmd <= "1111";
 246
 247     abs_xy_n <= '1';
 248     pg_next_n <= '1';
 249     zp_n <= '1';
 250     zp_xy_n <= '1';
 251     rel_calc_n <= '1';
 252     indir_n <= '1';
 253     indir_x_n <= '1';
 254     indir_y_n <= '1';
 255     arith_en_n <= '1';
 256
 257     read_status;
 258     stat_bus_oe_n <= '1';
 259     stat_set_flg_n <= '1';
 260     stat_flg <= '1';
 261     stat_bus_all_n <= '1';
 262     stat_bus_nz_n <= '1';
 263     stat_alu_we_n <= '1';
 264
 265     r_vec_oe_n <= '1';
 266     n_vec_oe_n <= '1';
 267     i_vec_oe_n <= '1';
 268
 269     wait_a2_abs_xy_next <= '0';
 270     wait_a2_indir_y_next <= '0';
 271 end  procedure;
 272
 273 procedure fetch_inst (inc_pcl : in std_logic) is
 274 begin
 275     if instruction = conv_std_logic_vector(16#4c#, dsize) then
 276         --if prior cycle is jump instruction,
 277         --fetch opcode from where the latch is pointing to.
 278
 279         --latch > al.
 280         dl_al_oe_n <= '0';
 281         pcl_cmd <= "1110";
 282     else
 283         --fetch opcode and pcl increment.
 284         pcl_cmd <= "1100";
 285         dl_al_oe_n <= '1';
 286     end if;
 287
 288     ad_oe_n <= '0';
 289     pch_cmd <= "1101";
 290     inst_we_n <= '0';
 291     pcl_inc_n <= inc_pcl;
 292     r_nw <= '1';
 293
 294     d_print(string'("fetch 1"));
 295 end  procedure;
 296
 297 ---T0 cycle routine
 298 ---(along with the page boundary condition, the last
 299 ---cycle is bypassed and slided to T0.)
 300 procedure t0_cycle is
 301 begin
 302     disable_pins;
 303     if (nmi_n = '0' and nmi_handled_n = '1') then
 304         --start nmi handling...
 305         fetch_inst('1');
 306         next_cycle <= N1;
 307     else
 308         fetch_inst('0');
 309         next_cycle <= T1;
 310     end if;
 311 end  procedure;
 312
 313 ---common routine for single byte instruction.
 314 procedure single_inst is
 315 begin
 316     fetch_stop;
 317     next_cycle <= T0;
 318 end  procedure;
 319
 320 procedure fetch_imm is
 321 begin
 322     d_print("immediate");
 323     fetch_next;
 324     --send data from data bus buffer.
 325     --receiver is instruction dependent.
 326     dbuf_int_oe_n <= '0';
 327     next_cycle <= T0;
 328 end  procedure;
 329
 330 procedure set_nz_from_bus is
 331 begin
 332     --status register n/z bit update.
 333     stat_bus_nz_n <= '0';
 334 end  procedure;
 335
 336 procedure set_zc_from_alu is
 337 begin
 338     --status register n/z bit update.
 339     stat_alu_we_n <= '0';
 340     stat_dec_oe_n <= '1';
 341     status_reg <= "00000011";
 342 end  procedure;
 343
 344 procedure set_nz_from_alu is
 345 begin
 346     --status register n/z/c bit update.
 347     stat_alu_we_n <= '0';
 348     stat_dec_oe_n <= '1';
 349     status_reg <= "10000010";
 350 end  procedure;
 351
 352 procedure set_nzc_from_alu is
 353 begin
 354     --status register n/z/c bit update.
 355     stat_alu_we_n <= '0';
 356     stat_dec_oe_n <= '1';
 357     status_reg <= "10000011";
 358 end  procedure;
 359
 360 procedure set_nvz_from_alu is
 361 begin
 362     --status register n/z/v bit update.
 363     stat_alu_we_n <= '0';
 364     stat_dec_oe_n <= '1';
 365     status_reg <= "11000010";
 366 end  procedure;
 367
 368 procedure set_nvzc_from_alu is
 369 begin
 370     stat_alu_we_n <= '0';
 371     stat_dec_oe_n <= '1';
 372     status_reg <= "11000011";
 373 end  procedure;
 374
 375 --flag on/off instruction
 376 procedure set_flag (int_flg : in integer; val : in std_logic) is
 377 begin
 378     stat_dec_oe_n <= '1';
 379     stat_set_flg_n <= '0';
 380     --specify which to set.
 381     status_reg(7 downto int_flg + 1)
 382         <= (others =>'0');
 383     status_reg(int_flg - 1 downto 0)
 384         <= (others =>'0');
 385     status_reg(int_flg) <= '1';
 386     stat_flg <= val;
 387 end  procedure;
 388
 389 --for sec/clc
 390 procedure set_flag0 (val : in std_logic) is
 391 begin
 392     stat_dec_oe_n <= '1';
 393     stat_set_flg_n <= '0';
 394     status_reg <= "00000001";
 395     stat_flg <= val;
 396 end  procedure;
 397
 398 procedure fetch_low is
 399 begin
 400     d_print("fetch low 2");
 401     --fetch next opcode (abs low).
 402     fetch_next;
 403     --latch abs low data.
 404     dbuf_int_oe_n <= '0';
 405     dl_al_we_n <= '0';
 406     next_cycle <= T2;
 407 end  procedure;
 408
 409 procedure abs_fetch_high is
 410 begin
 411     d_print("abs (xy) 3");
 412     dl_al_we_n <= '1';
 413
 414     --latch abs hi data.
 415     fetch_next;
 416     dbuf_int_oe_n <= '0';
 417     dl_ah_we_n <= '0';
 418     next_cycle <= T3;
 419 end  procedure;
 420
 421 procedure abs_latch_out is
 422 begin
 423     --d_print("abs 4");
 424     fetch_stop;
 425     dl_ah_we_n <= '1';
 426
 427     --latch > al/ah.
 428     dl_al_oe_n <= '0';
 429     dl_ah_oe_n <= '0';
 430 end  procedure;
 431
 432 procedure ea_x_out is
 433 begin
 434     -----calucurate and output effective addr
 435     back_oe(x_cmd, '0');
 436     abs_xy_n <= '0';
 437 end  procedure;
 438
 439 procedure ea_y_out is
 440 begin
 441     back_oe(y_cmd, '0');
 442     abs_xy_n <= '0';
 443 end  procedure;
 444
 445 --A.2. internal execution on memory data
 446
 447 procedure a2_zp is
 448 begin
 449     if exec_cycle = T1 then
 450         fetch_low;
 451     elsif exec_cycle = T2 then
 452         fetch_stop;
 453         dbuf_int_oe_n <= '0';
 454         dl_al_we_n <= '1';
 455
 456         --calc zp.
 457         dl_al_oe_n <= '0';
 458         zp_n <= '0';
 459         next_cycle <= T0;
 460     end if;
 461 end  procedure;
 462
 463 procedure a2_abs is
 464 begin
 465     if exec_cycle = T1 then
 466         fetch_low;
 467     elsif exec_cycle = T2 then
 468         abs_fetch_high;
 469     elsif exec_cycle = T3 then
 470         abs_latch_out;
 471         dbuf_int_oe_n <= '0';
 472         next_cycle <= T0;
 473     end if;
 474 end  procedure;
 475
 476 procedure a2_page_next is
 477 begin
 478     --close open gate if page boundary crossed.
 479     back_we(acc_cmd, '1');
 480     front_we(acc_cmd, '1');
 481     front_we(x_cmd, '1');
 482     front_we(y_cmd, '1');
 483     stat_alu_we_n <= '1';
 484 end  procedure;
 485
 486 procedure a2_abs_xy (is_x : in boolean) is
 487 begin
 488     if exec_cycle = T1 then
 489         fetch_low;
 490     elsif exec_cycle = T2 then
 491         abs_fetch_high;
 492     elsif exec_cycle = T3 then
 493         --ea calc & lda
 494         pg_next_n <= '1';
 495         abs_latch_out;
 496         if (is_x = true) then
 497             ea_x_out;
 498         else
 499             ea_y_out;
 500         end if;
 501         dbuf_int_oe_n <= '0';
 502
 503         wait_a2_abs_xy_next <= '1';
 504         next_cycle <= a2_abs_xy_next_cycle;
 505         d_print("absx step 1");
 506     elsif exec_cycle = T4 then
 507         --case page boundary crossed.
 508         --redo inst.
 509         d_print("absx 5 (page boudary crossed.)");
 510         --next page.
 511         pg_next_n <= not ea_carry;
 512         next_cycle <= T0;
 513     end if;
 514 end  procedure;
 515
 516 procedure a2_zp_xy (is_x : in boolean) is
 517 begin
 518     if exec_cycle = T1 then
 519         fetch_low;
 520     elsif exec_cycle = T2 then
 521         fetch_stop;
 522         --output BAL only
 523         dbuf_int_oe_n <= '0';
 524         dl_al_we_n <= '1';
 525
 526         --calc zp.
 527         dl_al_oe_n <= '0';
 528         zp_n <= '0';
 529         next_cycle <= T3;
 530     elsif exec_cycle = T3 then
 531         --t3 zp, xy
 532         zp_xy_n <= '0';
 533         if (is_x = true) then
 534             back_oe(x_cmd, '0');
 535         else
 536             back_oe(y_cmd, '0');
 537         end if;
 538         next_cycle <= T0;
 539     end if;
 540 end  procedure;
 541
 542 procedure a2_indir_y is
 543 begin
 544     if exec_cycle = T1 then
 545         fetch_low;
 546         --get IAL
 547         dl_al_we_n <= '0';
 548
 549     elsif exec_cycle = T2 then
 550         fetch_stop;
 551         dl_al_we_n <= '1';
 552
 553         ---address is 00:IAL
 554         --output BAL @IAL
 555         indir_y_n <= '0';
 556         dl_al_oe_n <= '0';
 557         dbuf_int_oe_n <= '0';
 558         next_cycle <= T3;
 559
 560     elsif exec_cycle = T3 then
 561         indir_y_n <= '0';
 562         dl_al_oe_n <= '0';
 563         --output BAH @IAL+1
 564         dbuf_int_oe_n <= '0';
 565         next_cycle <= T4;
 566
 567     elsif exec_cycle = T4 then
 568         dl_al_oe_n <= '1';
 569         dbuf_int_oe_n <= '1';
 570
 571         --add index y.
 572         pg_next_n <= '1';
 573         back_oe(y_cmd, '0');
 574         indir_y_n <= '0';
 575         dbuf_int_oe_n <= '0';
 576
 577         wait_a2_indir_y_next <= '1';
 578         next_cycle <= a2_indir_y_next_cycle;
 579     elsif exec_cycle = T5 then
 580         --case page boundary crossed.
 581         --redo inst.
 582         d_print("(indir), y (page boudary crossed.)");
 583         --next page.
 584         pg_next_n <= not ea_carry;
 585         next_cycle <= T0;
 586     end if;
 587 end  procedure;
 588
 589 --A.3. store operation.
 590
 591 procedure a3_zp is
 592 begin
 593     if exec_cycle = T1 then
 594         fetch_low;
 595     elsif exec_cycle = T2 then
 596         fetch_stop;
 597         dbuf_int_oe_n <= '1';
 598         dl_al_we_n <= '1';
 599
 600         --calc zp.
 601         dl_al_oe_n <= '0';
 602         zp_n <= '0';
 603         r_nw <= '0';
 604         next_cycle <= T0;
 605     end if;
 606 end  procedure;
 607
 608 procedure a3_abs is
 609 begin
 610     if exec_cycle = T1 then
 611         fetch_low;
 612     elsif exec_cycle = T2 then
 613         abs_fetch_high;
 614     elsif exec_cycle = T3 then
 615         abs_latch_out;
 616         dbuf_int_oe_n <= '1';
 617         r_nw <= '0';
 618         next_cycle <= T0;
 619     end if;
 620 end  procedure;
 621
 622 procedure a3_abs_xy (is_x : in boolean) is
 623 begin
 624     if exec_cycle = T1 then
 625         fetch_low;
 626     elsif exec_cycle = T2 then
 627         abs_fetch_high;
 628     elsif exec_cycle = T3 then
 629         --ea calc & lda
 630         pg_next_n <= '1';
 631         abs_latch_out;
 632         dbuf_int_oe_n <= '1';
 633         if (is_x = true) then
 634             ea_x_out;
 635         else
 636             ea_y_out;
 637         end if;
 638         next_cycle <= T4;
 639     elsif exec_cycle = T4 then
 640         pg_next_n <= not ea_carry;
 641         abs_latch_out;
 642         if (is_x = true) then
 643             ea_x_out;
 644         else
 645             ea_y_out;
 646         end if;
 647         r_nw <= '0';
 648         next_cycle <= T0;
 649     end if;
 650 end  procedure;
 651
 652
 653 procedure a3_indir_y is
 654 begin
 655     if exec_cycle = T1 then
 656         fetch_low;
 657         --get IAL
 658         dl_al_we_n <= '0';
 659
 660     elsif exec_cycle = T2 then
 661         fetch_stop;
 662         dl_al_we_n <= '1';
 663
 664         ---address is 00:IAL
 665         --output BAL @IAL
 666         indir_y_n <= '0';
 667         dl_al_oe_n <= '0';
 668         dbuf_int_oe_n <= '0';
 669         next_cycle <= T3;
 670
 671     elsif exec_cycle = T3 then
 672         indir_y_n <= '0';
 673         dl_al_oe_n <= '0';
 674         --output BAH @IAL+1
 675         dbuf_int_oe_n <= '0';
 676         next_cycle <= T4;
 677
 678     elsif exec_cycle = T4 then
 679         dl_al_oe_n <= '1';
 680         dbuf_int_oe_n <= '1';
 681
 682         --add index y.
 683         pg_next_n <= '1';
 684         back_oe(y_cmd, '0');
 685         indir_y_n <= '0';
 686         next_cycle <= T5;
 687
 688     elsif exec_cycle = T5 then
 689         --page handling.
 690         back_oe(y_cmd, '1');
 691         indir_y_n <= '0';
 692         pg_next_n <= not ea_carry;
 693         r_nw <= '0';
 694         next_cycle <= T0;
 695     end if;
 696 end  procedure;
 697
 698
 699 ---A.4. read-modify-write operation
 700
 701 procedure a4_zp is
 702 begin
 703     if exec_cycle = T1 then
 704         fetch_low;
 705     elsif exec_cycle = T2 then
 706         fetch_stop;
 707         dbuf_int_oe_n <= '1';
 708         dl_al_we_n <= '1';
 709
 710         --t2 cycle only read
 711         dl_al_oe_n <= '0';
 712         zp_n <= '0';
 713         next_cycle <= T3;
 714     elsif exec_cycle = T3 then
 715         dl_al_oe_n <= '0';
 716         zp_n <= '0';
 717         --keep data in the alu reg.
 718         arith_en_n <= '0';
 719         dbuf_int_oe_n <= '0';
 720         next_cycle <= T4;
 721     elsif exec_cycle = T4 then
 722         dbuf_int_oe_n <= '1';
 723
 724         --t5 cycle writes modified value.
 725         dl_al_oe_n <= '0';
 726         zp_n <= '0';
 727         r_nw <= '0';
 728         arith_en_n <= '0';
 729         next_cycle <= T0;
 730     end if;
 731 end  procedure;
 732
 733
 734 procedure a4_abs is
 735 begin
 736     if exec_cycle = T1 then
 737         fetch_low;
 738     elsif exec_cycle = T2 then
 739         abs_fetch_high;
 740     elsif exec_cycle = T3 then
 741         --T3 cycle do nothing.
 742         abs_latch_out;
 743         next_cycle <= T4;
 744     elsif exec_cycle = T4 then
 745         abs_latch_out;
 746
 747         --t4 cycle save data in the alu register only.
 748         --hardware maunual says write original data,
 749         --but this implementation doesn't write because bus shortage....
 750         arith_en_n <= '0';
 751         next_cycle <= T5;
 752     elsif exec_cycle = T5 then
 753         dbuf_int_oe_n <= '1';
 754
 755         --t5 cycle writes modified value.
 756         r_nw <= '0';
 757         arith_en_n <= '0';
 758         next_cycle <= T0;
 759     end if;
 760 end  procedure;
 761
 762 procedure a4_abs_x is
 763 begin
 764     if exec_cycle = T1 then
 765         fetch_low;
 766     elsif exec_cycle = T2 then
 767         abs_fetch_high;
 768     elsif exec_cycle = T3 then
 769         --T3 cycle discarded.
 770         pg_next_n <= '1';
 771         abs_latch_out;
 772         ea_x_out;
 773         dbuf_int_oe_n <= '0';
 774         next_cycle <= T4;
 775
 776     elsif exec_cycle = T4 then
 777         --t4 cycle fetch only.
 778         abs_latch_out;
 779         ea_x_out;
 780         pg_next_n <= not ea_carry;
 781         next_cycle <= T5;
 782
 783     elsif exec_cycle = T5 then
 784         --t4 cycle redo fetch and save data in the alu register only.
 785         arith_en_n <= '0';
 786         next_cycle <= T6;
 787
 788     elsif exec_cycle = T6 then
 789         --t5 cycle writes modified value.
 790         r_nw <= '0';
 791         arith_en_n <= '0';
 792         dbuf_int_oe_n <= '1';
 793         next_cycle <= T0;
 794
 795     end if;
 796 end  procedure;
 797
 798
 799 -- A.5.1 push stack
 800 procedure a51_push is
 801 begin
 802     if exec_cycle = T1 then
 803         fetch_stop;
 804         next_cycle <= T2;
 805     elsif exec_cycle = T2 then
 806         back_oe(sp_cmd, '0');
 807         back_we(sp_cmd, '0');
 808         sp_push_n <= '0';
 809         sp_oe_n <= '0';
 810         r_nw <= '0';
 811         next_cycle <= T0;
 812     end if;
 813 end procedure;
 814
 815 -- A.5.2 pull stack
 816 procedure a52_pull is
 817 begin
 818     if exec_cycle = T1 then
 819         fetch_stop;
 820         next_cycle <= T2;
 821
 822     elsif exec_cycle = T2 then
 823         --stack decrement first.
 824         back_oe(sp_cmd, '0');
 825         back_we(sp_cmd, '0');
 826         sp_pop_n <= '0';
 827         sp_oe_n <= '0';
 828         next_cycle <= T3;
 829
 830     elsif exec_cycle = T3 then
 831         sp_pop_n <= '1';
 832         back_we(sp_cmd, '1');
 833
 834         ---pop data from stack.
 835         back_oe(sp_cmd, '0');
 836         sp_oe_n <= '0';
 837         dbuf_int_oe_n <= '0';
 838         next_cycle <= T0;
 839     end if;
 840 end procedure;
 841
 842
 843 -- A.5.8 branch operations
 844
 845 procedure a58_branch (int_flg : in integer; br_cond : in std_logic) is
 846 begin
 847     if exec_cycle = T1 then
 848         fetch_next;
 849         if status_reg(int_flg) = br_cond then
 850             d_print("get rel");
 851
 852             --latch rel value.
 853             dbuf_int_oe_n <= '0';
 854             dl_ah_we_n <= '0';
 855             next_cycle <= T2;
 856         else
 857             d_print("no branch");
 858             next_cycle <= T0;
 859         end if;
 860     elsif exec_cycle = T2 then
 861         d_print("rel ea");
 862         fetch_stop;
 863         dbuf_int_oe_n <= '1';
 864         dl_ah_we_n <= '1';
 865
 866         --calc relative addr.
 867         rel_calc_n <= '0';
 868         pg_next_n <= '1';
 869         dl_dh_oe_n <= '0';
 870         back_oe(pcl_cmd, '0');
 871         back_oe(pch_cmd, '0');
 872         back_we(pcl_cmd, '0');
 873
 874         next_cycle <= T3;
 875     elsif exec_cycle = T3 then
 876         if ea_carry = '1' then
 877             d_print("page crossed.");
 878             --page crossed. adh calc.
 879             back_we(pcl_cmd, '1');
 880             back_oe(pcl_cmd, '0');
 881             back_oe(pch_cmd, '0');
 882             back_we(pch_cmd, '0');
 883             dl_dh_oe_n <= '0';
 884
 885             rel_calc_n <= '0';
 886             pg_next_n <= not ea_carry;
 887             next_cycle <= T0;
 888         else
 889             --no page boundary.
 890             --fetch cycle is done.
 891             t0_cycle;
 892         end if;
 893     end if;
 894 end  procedure;
 895
 896 -------------------------------------------------------------
 897 -------------------------------------------------------------
 898 ---------------- main state machine start.... ---------------
 899 -------------------------------------------------------------
 900 -------------------------------------------------------------
 901     begin
 902
 903         if (res_n = '0') then
 904             --pc l/h is reset vector.
 905             pcl_cmd <= "1110";
 906             pch_cmd <= "1110";
 907             next_cycle <= R0;
 908         elsif (res_n'event and res_n = '1') then
 909             pcl_cmd <= "1111";
 910             pch_cmd <= "1111";
 911         end if;
 912
 913         if (nmi_n'event and nmi_n = '1') then
 914             --reset nmi handle status
 915             nmi_handled_n <= '1';
 916         end if;
 917
 918
 919         if (a2_abs_xy_next_cycle'event) then
 920             if (wait_a2_abs_xy_next = '1') then
 921                 d_print("absx step 2");
 922                 next_cycle <= a2_abs_xy_next_cycle;
 923                 if (ea_carry = '1') then
 924                     a2_page_next;
 925                 end if;
 926             end if;
 927         end if;
 928
 929         if (a2_indir_y_next_cycle'event) then
 930             if (wait_a2_indir_y_next = '1') then
 931                 next_cycle <= a2_indir_y_next_cycle;
 932                 if (ea_carry = '1') then
 933                     a2_page_next;
 934                 end if;
 935             end if;
 936         end if;
 937
 938         if (set_clk'event and set_clk = '1' and res_n = '1') then
 939             d_print(string'("-"));
 940
 941             if exec_cycle = T0 then
 942                 --cycle #1
 943                 t0_cycle;
 944
 945             elsif exec_cycle = T1 or exec_cycle = T2 or exec_cycle = T3 or
 946                 exec_cycle = T4 or exec_cycle = T5 or exec_cycle = T6 then
 947                 --execute inst.
 948
 949                 ---asyncronous page change might happen.
 950                 back_we(pch_cmd, '1');
 951
 952                 if exec_cycle = T1 then
 953                     d_print("decode and execute inst: "
 954                             & conv_hex8(conv_integer(instruction)));
 955                     --disable pin for jmp instruction
 956                     dl_al_oe_n <= '1';
 957                     back_we(pcl_cmd, '1');
 958                     front_we(pch_cmd, '1');
 959
 960                     --grab instruction register data.
 961                     inst_we_n <= '1';
 962                 end if;
 963
 964                 --imelementation is wriiten in the order of hardware manual
 965                 --appendix A.
 966
 967                 ----------------------------------------
 968                 --A.1. Single byte instruction.
 969                 ----------------------------------------
 970                 if instruction = conv_std_logic_vector(16#0a#, dsize) then
 971                     --asl acc mode.
 972                     d_print("asl");
 973                     arith_en_n <= '0';
 974                     back_oe(acc_cmd, '0');
 975                     front_we(acc_cmd, '0');
 976                     set_nzc_from_alu;
 977                     single_inst;
 978
 979                 elsif instruction = conv_std_logic_vector(16#18#, dsize) then
 980                     d_print("clc");
 981                     set_flag0 ('0');
 982                     single_inst;
 983
 984                 elsif instruction = conv_std_logic_vector(16#d8#, dsize) then
 985                     d_print("cld");
 986                     set_flag (st_D, '0');
 987                     single_inst;
 988
 989                 elsif instruction = conv_std_logic_vector(16#58#, dsize) then
 990                     d_print("cli");
 991                     set_flag (st_I, '0');
 992                     single_inst;
 993
 994                 elsif instruction = conv_std_logic_vector(16#b8#, dsize) then
 995                     d_print("clv");
 996                     set_flag (st_V, '0');
 997                     single_inst;
 998
 999                 elsif instruction = conv_std_logic_vector(16#ca#, dsize) then
1000                     d_print("dex");
1001                     arith_en_n <= '0';
1002                     back_oe(x_cmd, '0');
1003                     front_we(x_cmd, '0');
1004                     --set nz bit.
1005                     set_nz_from_bus;
1006                     single_inst;
1007
1008                 elsif instruction = conv_std_logic_vector(16#88#, dsize) then
1009                     d_print("dey");
1010                     arith_en_n <= '0';
1011                     back_oe(y_cmd, '0');
1012                     front_we(y_cmd, '0');
1013                     --set nz bit.
1014                     set_nz_from_bus;
1015                     single_inst;
1016
1017                 elsif instruction = conv_std_logic_vector(16#e8#, dsize) then
1018                     d_print("inx");
1019                     arith_en_n <= '0';
1020                     back_oe(x_cmd, '0');
1021                     front_we(x_cmd, '0');
1022                     --set nz bit.
1023                     set_nz_from_bus;
1024                     single_inst;
1025
1026                 elsif instruction = conv_std_logic_vector(16#c8#, dsize) then
1027                     d_print("iny");
1028                     arith_en_n <= '0';
1029                     back_oe(y_cmd, '0');
1030                     front_we(y_cmd, '0');
1031                     set_nz_from_bus;
1032                     single_inst;
1033
1034                 elsif instruction = conv_std_logic_vector(16#4a#, dsize) then
1035                     --lsr acc mode
1036                     d_print("lsr");
1037                     arith_en_n <= '0';
1038                     back_oe(acc_cmd, '0');
1039                     front_we(acc_cmd, '0');
1040                     set_zc_from_alu;
1041                     single_inst;
1042
1043                 elsif instruction = conv_std_logic_vector(16#ea#, dsize) then
1044                     d_print("nop");
1045                     single_inst;
1046
1047                 elsif instruction = conv_std_logic_vector(16#2a#, dsize) then
1048                     --rol acc
1049                     d_print("rol");
1050                     arith_en_n <= '0';
1051                     back_oe(acc_cmd, '0');
1052                     front_we(acc_cmd, '0');
1053                     set_nzc_from_alu;
1054                     single_inst;
1055
1056                 elsif instruction = conv_std_logic_vector(16#6a#, dsize) then
1057                     --ror acc
1058                     d_print("ror");
1059                     arith_en_n <= '0';
1060                     back_oe(acc_cmd, '0');
1061                     front_we(acc_cmd, '0');
1062                     set_nzc_from_alu;
1063                     single_inst;
1064
1065                 elsif instruction = conv_std_logic_vector(16#38#, dsize) then
1066                     d_print("sec");
1067                     set_flag0 ('1');
1068                     single_inst;
1069
1070                 elsif instruction = conv_std_logic_vector(16#f8#, dsize) then
1071                     d_print("sed");
1072                     set_flag (st_D, '1');
1073                     single_inst;
1074
1075                 elsif instruction = conv_std_logic_vector(16#78#, dsize) then
1076                     d_print("sei");
1077                     set_flag (st_I, '1');
1078                     single_inst;
1079
1080                 elsif instruction = conv_std_logic_vector(16#aa#, dsize) then
1081                     d_print("tax");
1082                     set_nz_from_bus;
1083                     single_inst;
1084                     front_oe(acc_cmd, '0');
1085                     front_we(x_cmd, '0');
1086
1087                 elsif instruction = conv_std_logic_vector(16#a8#, dsize) then
1088                     d_print("tay");
1089                     set_nz_from_bus;
1090                     single_inst;
1091                     front_oe(acc_cmd, '0');
1092                     front_we(y_cmd, '0');
1093
1094                 elsif instruction = conv_std_logic_vector(16#ba#, dsize) then
1095                     d_print("tsx");
1096                     set_nz_from_bus;
1097
1098                 elsif instruction = conv_std_logic_vector(16#8a#, dsize) then
1099                     d_print("txa");
1100                     set_nz_from_bus;
1101                     single_inst;
1102                     front_oe(x_cmd, '0');
1103                     front_we(acc_cmd, '0');
1104
1105                 elsif instruction = conv_std_logic_vector(16#9a#, dsize) then
1106                     d_print("txs");
1107                     set_nz_from_bus;
1108                     single_inst;
1109                     front_oe(x_cmd, '0');
1110                     front_we(sp_cmd, '0');
1111
1112                 elsif instruction = conv_std_logic_vector(16#98#, dsize) then
1113                     d_print("tya");
1114                     set_nz_from_bus;
1115                     single_inst;
1116                     front_oe(y_cmd, '0');
1117                     front_we(acc_cmd, '0');
1118
1119
1120
1121                 ----------------------------------------
1122                 --A.2. internal execution on memory data
1123                 ----------------------------------------
1124                 elsif instruction  = conv_std_logic_vector(16#69#, dsize) then
1125                     --imm
1126                     d_print("adc");
1127                     fetch_imm;
1128                     arith_en_n <= '0';
1129                     back_oe(acc_cmd, '0');
1130                     back_we(acc_cmd, '0');
1131                     set_nvzc_from_alu;
1132
1133                 elsif instruction  = conv_std_logic_vector(16#65#, dsize) then
1134                     --zp
1135                     d_print("adc");
1136                     a2_zp;
1137                     if exec_cycle = T2 then
1138                         arith_en_n <= '0';
1139                         back_oe(acc_cmd, '0');
1140                         back_we(acc_cmd, '0');
1141                         set_nvzc_from_alu;
1142                     end if;
1143
1144                 elsif instruction  = conv_std_logic_vector(16#75#, dsize) then
1145                     --zp, x
1146                     d_print("adc");
1147                     a2_zp_xy(true);
1148                     if exec_cycle = T3 then
1149                         arith_en_n <= '0';
1150                         back_oe(acc_cmd, '0');
1151                         back_we(acc_cmd, '0');
1152                         set_nvzc_from_alu;
1153                     end if;
1154
1155                 elsif instruction  = conv_std_logic_vector(16#6d#, dsize) then
1156                     --abs
1157                     d_print("adc");
1158                     a2_abs;
1159                     if exec_cycle = T3 then
1160                         arith_en_n <= '0';
1161                         back_oe(acc_cmd, '0');
1162                         back_we(acc_cmd, '0');
1163                         set_nvzc_from_alu;
1164                     end if;
1165
1166                 elsif instruction  = conv_std_logic_vector(16#7d#, dsize) then
1167                     --abs, x
1168                     d_print("adc");
1169                     a2_abs_xy(true);
1170                     if exec_cycle = T3 or exec_cycle = T4 then
1171                         arith_en_n <= '0';
1172                         back_oe(acc_cmd, '0');
1173                         back_we(acc_cmd, '0');
1174                         set_nvzc_from_alu;
1175                     end if;
1176
1177                 elsif instruction  = conv_std_logic_vector(16#79#, dsize) then
1178                     --abs, y
1179                     d_print("adc");
1180                     a2_abs_xy(false);
1181                     if exec_cycle = T3 or exec_cycle = T4 then
1182                         arith_en_n <= '0';
1183                         back_oe(acc_cmd, '0');
1184                         back_we(acc_cmd, '0');
1185                         set_nvzc_from_alu;
1186                     end if;
1187
1188                 elsif instruction  = conv_std_logic_vector(16#61#, dsize) then
1189                     --(indir, x)
1190                     d_print("adc");
1191
1192                 elsif instruction  = conv_std_logic_vector(16#71#, dsize) then
1193                     --(indir), y
1194                     d_print("adc");
1195                     a2_indir_y;
1196                     if exec_cycle = T4 or exec_cycle = T5 then
1197                         arith_en_n <= '0';
1198                         back_oe(acc_cmd, '0');
1199                         back_we(acc_cmd, '0');
1200                         set_nvzc_from_alu;
1201                     end if;
1202
1203                 elsif instruction  = conv_std_logic_vector(16#29#, dsize) then
1204                     --imm
1205                     d_print("and");
1206                     fetch_imm;
1207                     arith_en_n <= '0';
1208                     back_oe(acc_cmd, '0');
1209                     back_we(acc_cmd, '0');
1210                     set_nz_from_alu;
1211
1212                 elsif instruction  = conv_std_logic_vector(16#25#, dsize) then
1213                     --zp
1214                     d_print("and");
1215                     a2_zp;
1216                     if exec_cycle = T2 then
1217                         arith_en_n <= '0';
1218                         back_oe(acc_cmd, '0');
1219                         back_we(acc_cmd, '0');
1220                         set_nz_from_alu;
1221                     end if;
1222
1223                 elsif instruction  = conv_std_logic_vector(16#35#, dsize) then
1224                     --zp, x
1225                     d_print("and");
1226                     a2_zp_xy(true);
1227                     if exec_cycle = T3 then
1228                         arith_en_n <= '0';
1229                         back_oe(acc_cmd, '0');
1230                         back_we(acc_cmd, '0');
1231                         set_nz_from_alu;
1232                     end if;
1233
1234                 elsif instruction  = conv_std_logic_vector(16#2d#, dsize) then
1235                     --abs
1236                     d_print("and");
1237                     a2_abs;
1238                     if exec_cycle = T3 then
1239                         arith_en_n <= '0';
1240                         back_oe(acc_cmd, '0');
1241                         back_we(acc_cmd, '0');
1242                         set_nz_from_alu;
1243                     end if;
1244
1245                 elsif instruction  = conv_std_logic_vector(16#3d#, dsize) then
1246                     --abs, x
1247                     d_print("and");
1248                     a2_abs_xy(true);
1249                     if exec_cycle = T3 or exec_cycle = T4 then
1250                         arith_en_n <= '0';
1251                         back_oe(acc_cmd, '0');
1252                         back_we(acc_cmd, '0');
1253                         set_nz_from_alu;
1254                     end if;
1255
1256                 elsif instruction  = conv_std_logic_vector(16#39#, dsize) then
1257                     --abs, y
1258                     d_print("and");
1259                     a2_abs_xy(false);
1260                     if exec_cycle = T3 or exec_cycle = T4 then
1261                         arith_en_n <= '0';
1262                         back_oe(acc_cmd, '0');
1263                         back_we(acc_cmd, '0');
1264                         set_nz_from_alu;
1265                     end if;
1266
1267                 elsif instruction  = conv_std_logic_vector(16#21#, dsize) then
1268                     --(indir, x)
1269                     d_print("and");
1270
1271                 elsif instruction  = conv_std_logic_vector(16#31#, dsize) then
1272                     --(indir), y
1273                     d_print("and");
1274                     a2_indir_y;
1275                     if exec_cycle = T4 or exec_cycle = T5 then
1276                         arith_en_n <= '0';
1277                         back_oe(acc_cmd, '0');
1278                         back_we(acc_cmd, '0');
1279                         set_nz_from_alu;
1280                     end if;
1281
1282                 elsif instruction  = conv_std_logic_vector(16#24#, dsize) then
1283                     --zp
1284                     d_print("bit");
1285                     a2_zp;
1286                     if exec_cycle = T2 then
1287                         arith_en_n <= '0';
1288                         back_oe(acc_cmd, '0');
1289                         set_nvz_from_alu;
1290                     end if;
1291
1292                 elsif instruction  = conv_std_logic_vector(16#2c#, dsize) then
1293                     --abs
1294                     d_print("bit");
1295                     a2_abs;
1296                     if exec_cycle = T3 then
1297                         arith_en_n <= '0';
1298                         back_oe(acc_cmd, '0');
1299                         set_nvz_from_alu;
1300                     end if;
1301
1302                 elsif instruction  = conv_std_logic_vector(16#c9#, dsize) then
1303                     --imm
1304                     d_print("cmp");
1305                     fetch_imm;
1306                     arith_en_n <= '0';
1307                     back_oe(acc_cmd, '0');
1308                     set_nzc_from_alu;
1309
1310                 elsif instruction  = conv_std_logic_vector(16#c5#, dsize) then
1311                     --zp
1312                     d_print("cmp");
1313                     a2_zp;
1314                     if exec_cycle = T2 then
1315                         arith_en_n <= '0';
1316                         back_oe(acc_cmd, '0');
1317                         set_nzc_from_alu;
1318                     end if;
1319
1320                 elsif instruction  = conv_std_logic_vector(16#d5#, dsize) then
1321                     --zp, x
1322                     d_print("cmp");
1323                     a2_zp_xy(true);
1324                     if exec_cycle = T3 then
1325                         arith_en_n <= '0';
1326                         back_oe(acc_cmd, '0');
1327                         set_nzc_from_alu;
1328                     end if;
1329
1330                 elsif instruction  = conv_std_logic_vector(16#cd#, dsize) then
1331                     --abs
1332                     d_print("cmp");
1333                     a2_abs;
1334                     if exec_cycle = T3 then
1335                         arith_en_n <= '0';
1336                         back_oe(acc_cmd, '0');
1337                         set_nzc_from_alu;
1338                     end if;
1339
1340                 elsif instruction  = conv_std_logic_vector(16#dd#, dsize) then
1341                     --abs, x
1342                     d_print("cmp");
1343                     a2_abs_xy(true);
1344                     if exec_cycle = T3 or exec_cycle = T4 then
1345                         arith_en_n <= '0';
1346                         back_oe(acc_cmd, '0');
1347                         set_nzc_from_alu;
1348                     end if;
1349
1350                 elsif instruction  = conv_std_logic_vector(16#d9#, dsize) then
1351                     --abs, y
1352                     d_print("cmp");
1353                     a2_abs_xy(false);
1354                     if exec_cycle = T3 or exec_cycle = T4 then
1355                         arith_en_n <= '0';
1356                         back_oe(acc_cmd, '0');
1357                         set_nzc_from_alu;
1358                     end if;
1359
1360                 elsif instruction  = conv_std_logic_vector(16#c1#, dsize) then
1361                     --(indir, x)
1362                     d_print("cmp");
1363
1364                 elsif instruction  = conv_std_logic_vector(16#d1#, dsize) then
1365                     --(indir), y
1366                     d_print("cmp");
1367                     a2_indir_y;
1368                     if exec_cycle = T4 or exec_cycle = T5 then
1369                         arith_en_n <= '0';
1370                         back_oe(acc_cmd, '0');
1371                         set_nzc_from_alu;
1372                     end if;
1373
1374                 elsif instruction  = conv_std_logic_vector(16#e0#, dsize) then
1375                     --imm
1376                     d_print("cpx");
1377                     fetch_imm;
1378                     arith_en_n <= '0';
1379                     back_oe(x_cmd, '0');
1380                     set_nzc_from_alu;
1381
1382                 elsif instruction  = conv_std_logic_vector(16#e4#, dsize) then
1383                     --zp
1384                     d_print("cpx");
1385                     a2_zp;
1386                     if exec_cycle = T2 then
1387                         arith_en_n <= '0';
1388                         back_oe(x_cmd, '0');
1389                         set_nzc_from_alu;
1390                     end if;
1391
1392                 elsif instruction  = conv_std_logic_vector(16#ec#, dsize) then
1393                     --abs
1394                     d_print("cpx");
1395
1396                 elsif instruction  = conv_std_logic_vector(16#c0#, dsize) then
1397                     --imm
1398                     d_print("cpy");
1399                     fetch_imm;
1400                     arith_en_n <= '0';
1401                     back_oe(y_cmd, '0');
1402                     set_nzc_from_alu;
1403
1404                 elsif instruction  = conv_std_logic_vector(16#c4#, dsize) then
1405                     --zp
1406                     d_print("cpy");
1407
1408                 elsif instruction  = conv_std_logic_vector(16#cc#, dsize) then
1409                     --abs
1410                     d_print("cpy");
1411
1412                 elsif instruction  = conv_std_logic_vector(16#49#, dsize) then
1413                     --imm
1414                     d_print("eor");
1415                     fetch_imm;
1416                     arith_en_n <= '0';
1417                     back_oe(acc_cmd, '0');
1418                     back_we(acc_cmd, '0');
1419                     set_nz_from_alu;
1420
1421                 elsif instruction  = conv_std_logic_vector(16#45#, dsize) then
1422                     --zp
1423                     d_print("eor");
1424                     a2_zp;
1425                     if exec_cycle = T2 then
1426                         arith_en_n <= '0';
1427                         back_oe(acc_cmd, '0');
1428                         back_we(acc_cmd, '0');
1429                         set_nz_from_alu;
1430                     end if;
1431
1432                 elsif instruction  = conv_std_logic_vector(16#55#, dsize) then
1433                     --zp, x
1434                     d_print("eor");
1435
1436                 elsif instruction  = conv_std_logic_vector(16#4d#, dsize) then
1437                     --abs
1438                     d_print("eor");
1439
1440                 elsif instruction  = conv_std_logic_vector(16#5d#, dsize) then
1441                     --abs, x
1442                     d_print("eor");
1443
1444                 elsif instruction  = conv_std_logic_vector(16#59#, dsize) then
1445                     --abs, y
1446                     d_print("eor");
1447
1448                 elsif instruction  = conv_std_logic_vector(16#41#, dsize) then
1449                     --(indir, x)
1450                     d_print("eor");
1451
1452                 elsif instruction  = conv_std_logic_vector(16#51#, dsize) then
1453                     --(indir), y
1454                     d_print("eor");
1455
1456                 elsif instruction  = conv_std_logic_vector(16#a9#, dsize) then
1457                     --imm
1458                     d_print("lda");
1459                     fetch_imm;
1460                     front_we(acc_cmd, '0');
1461                     set_nz_from_bus;
1462
1463                 elsif instruction  = conv_std_logic_vector(16#a5#, dsize) then
1464                     --zp
1465                     d_print("lda");
1466                     a2_zp;
1467                     if exec_cycle = T2 then
1468                         front_we(acc_cmd, '0');
1469                         set_nz_from_bus;
1470                     end if;
1471
1472                 elsif instruction  = conv_std_logic_vector(16#b5#, dsize) then
1473                     --zp, x
1474                     d_print("lda");
1475                     a2_zp_xy(true);
1476                     if exec_cycle = T3 then
1477                         front_we(acc_cmd, '0');
1478                         set_nz_from_bus;
1479                     end if;
1480
1481                 elsif instruction  = conv_std_logic_vector(16#ad#, dsize) then
1482                     --abs
1483                     d_print("lda");
1484                     a2_abs;
1485                     if exec_cycle = T3 then
1486                         set_nz_from_bus;
1487                         front_we(acc_cmd, '0');
1488                     end if;
1489
1490                 elsif instruction  = conv_std_logic_vector(16#bd#, dsize) then
1491                     --abs, x
1492                     d_print("lda");
1493                     a2_abs_xy(true);
1494                     if exec_cycle = T3 or exec_cycle = T4 then
1495                         --lda.
1496                         front_we(acc_cmd, '0');
1497                         set_nz_from_bus;
1498                     end if;
1499
1500                 elsif instruction  = conv_std_logic_vector(16#b9#, dsize) then
1501                     --abs, y
1502                     d_print("lda");
1503                     a2_abs_xy(false);
1504                     if exec_cycle = T3 or exec_cycle = T4 then
1505                         --lda.
1506                         front_we(acc_cmd, '0');
1507                         set_nz_from_bus;
1508                     end if;
1509
1510                 elsif instruction  = conv_std_logic_vector(16#a1#, dsize) then
1511                     --(indir, x)
1512                     d_print("lda");
1513
1514                 elsif instruction  = conv_std_logic_vector(16#b1#, dsize) then
1515                     --(indir), y
1516                     d_print("lda");
1517                     a2_indir_y;
1518                     if exec_cycle = T4 or exec_cycle = T5 then
1519                         --lda.
1520                         front_we(acc_cmd, '0');
1521                         set_nz_from_bus;
1522                     end if;
1523
1524                 elsif instruction  = conv_std_logic_vector(16#a2#, dsize) then
1525                     --imm
1526                     d_print("ldx");
1527                     fetch_imm;
1528                     set_nz_from_bus;
1529                     front_we(x_cmd, '0');
1530
1531                 elsif instruction  = conv_std_logic_vector(16#a6#, dsize) then
1532                     --zp
1533                     d_print("ldx");
1534                     a2_zp;
1535                     if exec_cycle = T2 then
1536                         front_we(x_cmd, '0');
1537                         set_nz_from_bus;
1538                     end if;
1539
1540                 elsif instruction  = conv_std_logic_vector(16#b6#, dsize) then
1541                     --zp, y
1542                     d_print("ldx");
1543
1544                 elsif instruction  = conv_std_logic_vector(16#ae#, dsize) then
1545                     --abs
1546                     d_print("ldx");
1547                     a2_abs;
1548                     if exec_cycle = T3 then
1549                         set_nz_from_bus;
1550                         front_we(x_cmd, '0');
1551                     end if;
1552
1553                 elsif instruction  = conv_std_logic_vector(16#be#, dsize) then
1554                     --abs, y
1555                     d_print("ldx");
1556                     a2_abs_xy(false);
1557                     if exec_cycle = T3 or exec_cycle = T4 then
1558                         front_we(x_cmd, '0');
1559                         set_nz_from_bus;
1560                     end if;
1561
1562                 elsif instruction  = conv_std_logic_vector(16#a0#, dsize) then
1563                     --imm
1564                     d_print("ldy");
1565                     fetch_imm;
1566                     set_nz_from_bus;
1567                     front_we(y_cmd, '0');
1568
1569                 elsif instruction  = conv_std_logic_vector(16#a4#, dsize) then
1570                     --zp
1571                     d_print("ldy");
1572                     a2_zp;
1573                     if exec_cycle = T2 then
1574                         front_we(y_cmd, '0');
1575                         set_nz_from_bus;
1576                     end if;
1577
1578                 elsif instruction  = conv_std_logic_vector(16#b4#, dsize) then
1579                     --zp, x
1580                     d_print("ldy");
1581                     a2_zp_xy(true);
1582                     if exec_cycle = T3 then
1583                         front_we(y_cmd, '0');
1584                         set_nz_from_bus;
1585                     end if;
1586
1587                 elsif instruction  = conv_std_logic_vector(16#ac#, dsize) then
1588                     --abs
1589                     d_print("ldy");
1590                     a2_abs;
1591                     if exec_cycle = T3 then
1592                         set_nz_from_bus;
1593                         front_we(y_cmd, '0');
1594                     end if;
1595
1596                 elsif instruction  = conv_std_logic_vector(16#bc#, dsize) then
1597                     --abs, x
1598                     d_print("ldy");
1599
1600                 elsif instruction  = conv_std_logic_vector(16#09#, dsize) then
1601                     --imm
1602                     d_print("ora");
1603                     fetch_imm;
1604                     arith_en_n <= '0';
1605                     back_oe(acc_cmd, '0');
1606                     back_we(acc_cmd, '0');
1607                     set_nz_from_alu;
1608
1609                 elsif instruction  = conv_std_logic_vector(16#05#, dsize) then
1610                     --zp
1611                     d_print("ora");
1612                     a2_zp;
1613                     if exec_cycle = T2 then
1614                         arith_en_n <= '0';
1615                         back_oe(acc_cmd, '0');
1616                         back_we(acc_cmd, '0');
1617                         set_nz_from_alu;
1618                     end if;
1619
1620                 elsif instruction  = conv_std_logic_vector(16#15#, dsize) then
1621                     --zp, x
1622                     d_print("ora");
1623
1624                 elsif instruction  = conv_std_logic_vector(16#0d#, dsize) then
1625                     --abs
1626                     d_print("ora");
1627
1628                 elsif instruction  = conv_std_logic_vector(16#1d#, dsize) then
1629                     --abs, x
1630                     d_print("ora");
1631
1632                 elsif instruction  = conv_std_logic_vector(16#19#, dsize) then
1633                     --abs, y
1634                     d_print("ora");
1635
1636                 elsif instruction  = conv_std_logic_vector(16#01#, dsize) then
1637                     --(indir, x)
1638                     d_print("ora");
1639
1640                 elsif instruction  = conv_std_logic_vector(16#11#, dsize) then
1641                     --(indir), y
1642                     d_print("ora");
1643
1644                 elsif instruction  = conv_std_logic_vector(16#e9#, dsize) then
1645                     --imm
1646                     d_print("sbc");
1647                     fetch_imm;
1648                     arith_en_n <= '0';
1649                     back_oe(acc_cmd, '0');
1650                     back_we(acc_cmd, '0');
1651                     set_nvzc_from_alu;
1652
1653                 elsif instruction  = conv_std_logic_vector(16#e5#, dsize) then
1654                     --zp
1655                     d_print("sbc");
1656
1657                 elsif instruction  = conv_std_logic_vector(16#f5#, dsize) then
1658                     --zp, x
1659                     d_print("sbc");
1660
1661                 elsif instruction  = conv_std_logic_vector(16#ed#, dsize) then
1662                     --abs
1663                     d_print("sbc");
1664
1665                 elsif instruction  = conv_std_logic_vector(16#fd#, dsize) then
1666                     --abs, x
1667                     d_print("sbc");
1668
1669                 elsif instruction  = conv_std_logic_vector(16#f9#, dsize) then
1670                     --abs, y
1671                     d_print("sbc");
1672                     a2_abs_xy(false);
1673                     if exec_cycle = T3 or exec_cycle = T4 then
1674                         arith_en_n <= '0';
1675                         back_oe(acc_cmd, '0');
1676                         back_we(acc_cmd, '0');
1677                         set_nvzc_from_alu;
1678                     end if;
1679
1680                 elsif instruction  = conv_std_logic_vector(16#e1#, dsize) then
1681                     --(indir, x)
1682                     d_print("sbc");
1683
1684                 elsif instruction  = conv_std_logic_vector(16#f1#, dsize) then
1685                     --(indir), y
1686                     d_print("sbc");
1687
1688
1689
1690                 ----------------------------------------
1691                 ---A.3. store operation.
1692                 ----------------------------------------
1693                 elsif instruction  = conv_std_logic_vector(16#85#, dsize) then
1694                     --zp
1695                     d_print("sta");
1696                     a3_zp;
1697                     if exec_cycle = T2 then
1698                         front_oe(acc_cmd, '0');
1699                     end if;
1700
1701                 elsif instruction  = conv_std_logic_vector(16#95#, dsize) then
1702                     --zp, x
1703                     d_print("sta");
1704
1705                 elsif instruction  = conv_std_logic_vector(16#8d#, dsize) then
1706                     --abs
1707                     d_print("sta");
1708                     a3_abs;
1709                     if exec_cycle = T3 then
1710                         front_oe(acc_cmd, '0');
1711                     end if;
1712
1713                 elsif instruction  = conv_std_logic_vector(16#9d#, dsize) then
1714                     --abs, x
1715                     d_print("sta");
1716                     a3_abs_xy (true);
1717                     if exec_cycle = T4 then
1718                         front_oe(acc_cmd, '0');
1719                     end if;
1720
1721                 elsif instruction  = conv_std_logic_vector(16#99#, dsize) then
1722                     --abs, y
1723                     d_print("sta");
1724                     a3_abs_xy (false);
1725                     if exec_cycle = T4 then
1726                         front_oe(acc_cmd, '0');
1727                     end if;
1728
1729                 elsif instruction  = conv_std_logic_vector(16#81#, dsize) then
1730                     --(indir, x)
1731                     d_print("sta");
1732
1733                 elsif instruction  = conv_std_logic_vector(16#91#, dsize) then
1734                     --(indir), y
1735                     d_print("sta");
1736                     a3_indir_y;
1737                     if exec_cycle = T5 then
1738                         front_oe(acc_cmd, '0');
1739                     end if;
1740
1741                 elsif instruction  = conv_std_logic_vector(16#86#, dsize) then
1742                     --zp
1743                     d_print("stx");
1744                     a3_zp;
1745                     if exec_cycle = T2 then
1746                         front_oe(x_cmd, '0');
1747                     end if;
1748
1749                 elsif instruction  = conv_std_logic_vector(16#96#, dsize) then
1750                     --zp, y
1751                     d_print("stx");
1752
1753                 elsif instruction  = conv_std_logic_vector(16#8e#, dsize) then
1754                     --abs
1755                     d_print("stx");
1756                     a3_abs;
1757                     if exec_cycle = T3 then
1758                         front_oe(x_cmd, '0');
1759                     end if;
1760
1761                 elsif instruction  = conv_std_logic_vector(16#84#, dsize) then
1762                     --zp
1763                     d_print("sty");
1764                     a3_zp;
1765                     if exec_cycle = T2 then
1766                         front_oe(y_cmd, '0');
1767                     end if;
1768
1769                 elsif instruction  = conv_std_logic_vector(16#94#, dsize) then
1770                     --zp, x
1771                     d_print("sty");
1772
1773                 elsif instruction  = conv_std_logic_vector(16#8c#, dsize) then
1774                     --abs
1775                     d_print("sty");
1776                     a3_abs;
1777                     if exec_cycle = T3 then
1778                         front_oe(y_cmd, '0');
1779                     end if;
1780
1781
1782                 ----------------------------------------
1783                 ---A.4. read-modify-write operation
1784                 ----------------------------------------
1785                 elsif instruction  = conv_std_logic_vector(16#06#, dsize) then
1786                     --zp
1787                     d_print("asl");
1788
1789                 elsif instruction  = conv_std_logic_vector(16#16#, dsize) then
1790                     --zp, x
1791                     d_print("asl");
1792
1793                 elsif instruction  = conv_std_logic_vector(16#0e#, dsize) then
1794                     --abs
1795                     d_print("asl");
1796
1797                 elsif instruction  = conv_std_logic_vector(16#1e#, dsize) then
1798                     --abs, x
1799                     d_print("asl");
1800
1801                 elsif instruction  = conv_std_logic_vector(16#c6#, dsize) then
1802                     --zp
1803                     d_print("dec");
1804                     a4_zp;
1805                     if exec_cycle = T4 then
1806                         set_nz_from_bus;
1807                     end if;
1808
1809                 elsif instruction  = conv_std_logic_vector(16#d6#, dsize) then
1810                     --zp, x
1811                     d_print("dec");
1812
1813                 elsif instruction  = conv_std_logic_vector(16#ce#, dsize) then
1814                     --abs
1815                     d_print("dec");
1816                     a4_abs;
1817                     if exec_cycle = T5 then
1818                         set_nz_from_bus;
1819                     end if;
1820
1821                 elsif instruction  = conv_std_logic_vector(16#de#, dsize) then
1822                     --abs, x
1823                     d_print("dec");
1824
1825                 elsif instruction  = conv_std_logic_vector(16#e6#, dsize) then
1826                     --zp
1827                     d_print("inc");
1828                     a4_zp;
1829                     if exec_cycle = T4 then
1830                         set_nz_from_bus;
1831                     end if;
1832
1833                 elsif instruction  = conv_std_logic_vector(16#f6#, dsize) then
1834                     --zp, x
1835                     d_print("inc");
1836
1837                 elsif instruction  = conv_std_logic_vector(16#ee#, dsize) then
1838                     --abs
1839                     d_print("inc");
1840                     a4_abs;
1841                     if exec_cycle = T5 then
1842                         set_nz_from_bus;
1843                     end if;
1844
1845                 elsif instruction  = conv_std_logic_vector(16#fe#, dsize) then
1846                     --abs, x
1847                     d_print("inc");
1848
1849                 elsif instruction  = conv_std_logic_vector(16#46#, dsize) then
1850                     --zp
1851                     d_print("lsr");
1852
1853                 elsif instruction  = conv_std_logic_vector(16#56#, dsize) then
1854                     --zp, x
1855                     d_print("lsr");
1856
1857                 elsif instruction  = conv_std_logic_vector(16#4e#, dsize) then
1858                     --abs
1859                     d_print("lsr");
1860
1861                 elsif instruction  = conv_std_logic_vector(16#5e#, dsize) then
1862                     --abs, x
1863                     d_print("lsr");
1864
1865                 elsif instruction  = conv_std_logic_vector(16#26#, dsize) then
1866                     --zp
1867                     d_print("rol");
1868
1869                 elsif instruction  = conv_std_logic_vector(16#36#, dsize) then
1870                     --zp, x
1871                     d_print("rol");
1872
1873                 elsif instruction  = conv_std_logic_vector(16#2e#, dsize) then
1874                     --abs
1875                     d_print("rol");
1876
1877                 elsif instruction  = conv_std_logic_vector(16#3e#, dsize) then
1878                     --abs, x
1879                     d_print("rol");
1880
1881                 elsif instruction  = conv_std_logic_vector(16#66#, dsize) then
1882                     --zp
1883                     d_print("ror");
1884 --                    a4_zp;
1885 --                    if exec_cycle = T4 then
1886 --                        set_nzc_from_alu;
1887 --                    end if;
1888
1889                 elsif instruction  = conv_std_logic_vector(16#76#, dsize) then
1890                     --zp, x
1891                     d_print("ror");
1892
1893                 elsif instruction  = conv_std_logic_vector(16#6e#, dsize) then
1894                     --abs
1895                     d_print("ror");
1896
1897                 elsif instruction  = conv_std_logic_vector(16#7e#, dsize) then
1898                     --abs, x
1899                     d_print("ror");
1900                     a4_abs_x;
1901                     if exec_cycle = T6 then
1902                         set_nzc_from_alu;
1903                     end if;
1904
1905
1906                 ----------------------------------------
1907                 --A.5. miscellaneous oprations.
1908                 ----------------------------------------
1909
1910                 -- A.5.1 push/pull
1911                 elsif instruction = conv_std_logic_vector(16#08#, dsize) then
1912                     d_print("php");
1913
1914                 elsif instruction = conv_std_logic_vector(16#48#, dsize) then
1915                     d_print("pha");
1916                     a51_push;
1917                     if exec_cycle = T2 then
1918                         front_oe(acc_cmd, '0');
1919                     end if;
1920
1921                 elsif instruction = conv_std_logic_vector(16#28#, dsize) then
1922                     d_print("plp");
1923
1924                 elsif instruction = conv_std_logic_vector(16#68#, dsize) then
1925                     d_print("pla");
1926                     a52_pull;
1927                     if exec_cycle = T3 then
1928                         front_we(acc_cmd, '0');
1929                     end if;
1930
1931
1932                 ----------------------------------------
1933                 -- A.5.3 jsr
1934                 ----------------------------------------
1935                 elsif instruction = conv_std_logic_vector(16#20#, dsize) then
1936                     if exec_cycle = T1 then
1937                         d_print("jsr abs 2");
1938                         --fetch opcode.
1939                         fetch_next;
1940                         dbuf_int_oe_n <= '0';
1941                         --latch adl
1942                         dl_al_we_n <= '0';
1943                         next_cycle <= T2;
1944                     elsif exec_cycle = T2 then
1945                         d_print("jsr 3");
1946                         fetch_stop;
1947                         dbuf_int_oe_n <= '1';
1948                         dl_al_we_n <= '1';
1949
1950                        --push return addr high into stack.
1951                         sp_push_n <= '0';
1952                         sp_oe_n <= '0';
1953                         front_oe(pch_cmd, '0');
1954                         back_oe(sp_cmd, '0');
1955                         back_we(sp_cmd, '0');
1956                         r_nw <= '0';
1957                         next_cycle <= T3;
1958                     elsif exec_cycle = T3 then
1959                         d_print("jsr 4");
1960                         front_oe(pch_cmd, '1');
1961
1962                        --push return addr low into stack.
1963                         sp_push_n <= '0';
1964                         sp_oe_n <= '0';
1965                         front_oe(pcl_cmd, '0');
1966                         back_oe(sp_cmd, '0');
1967                         back_we(sp_cmd, '0');
1968                         r_nw <= '0';
1969
1970                         next_cycle <= T4;
1971                     elsif exec_cycle = T4 then
1972                         d_print("jsr 5");
1973                         sp_push_n <= '1';
1974                         sp_oe_n <= '1';
1975                         front_oe(pcl_cmd, '1');
1976                         back_oe(sp_cmd, '1');
1977                         back_we(sp_cmd, '1');
1978                         r_nw <= '1';
1979
1980                         --fetch last op.
1981                         back_oe(pch_cmd, '0');
1982                         back_oe(pcl_cmd, '0');
1983                         dbuf_int_oe_n <= '0';
1984                         dl_ah_we_n <= '0';
1985
1986                         next_cycle <= T5;
1987                     elsif exec_cycle = T5 then
1988                         d_print("jsr 6");
1989
1990                         back_oe(pch_cmd, '1');
1991                         back_oe(pcl_cmd, '1');
1992                         dbuf_int_oe_n <= '1';
1993                         dl_ah_we_n <= '1';
1994
1995                         --load/output  pch
1996                         ad_oe_n <= '1';
1997                         dl_dh_oe_n <= '0';
1998                         front_we(pch_cmd, '0');
1999
2000                         --load pcl.
2001                         dl_al_oe_n <= '0';
2002                         back_we(pcl_cmd, '0');
2003
2004                         next_cycle <= T0;
2005                     end if; --if exec_cycle = T1 then
2006
2007                 -- A.5.4 break
2008                 elsif instruction = conv_std_logic_vector(16#00#, dsize) then
2009
2010                 ----------------------------------------
2011                 -- A.5.5 return from interrupt
2012                 ----------------------------------------
2013                 elsif instruction = conv_std_logic_vector(16#40#, dsize) then
2014                     if exec_cycle = T1 then
2015                         d_print("rti 2");
2016                         fetch_stop;
2017
2018                         --pop stack (decrement only)
2019                         back_oe(sp_cmd, '0');
2020                         back_we(sp_cmd, '0');
2021                         sp_pop_n <= '0';
2022                         sp_oe_n <= '0';
2023
2024                         next_cycle <= T2;
2025                     elsif exec_cycle = T2 then
2026                         d_print("rti 3");
2027
2028                         --pop p (status)
2029                         back_oe(sp_cmd, '0');
2030                         back_we(sp_cmd, '0');
2031                         sp_pop_n <= '0';
2032                         sp_oe_n <= '0';
2033
2034                         --load status reg
2035                         stat_dec_oe_n <= '1';
2036                         dbuf_int_oe_n <= '0';
2037                         stat_bus_all_n <= '0';
2038
2039                         next_cycle <= T3;
2040                     elsif exec_cycle = T3 then
2041                         d_print("rti 4");
2042                         stat_bus_all_n <= '1';
2043
2044                         --pop pcl
2045                         back_oe(sp_cmd, '0');
2046                         back_we(sp_cmd, '0');
2047                         sp_pop_n <= '0';
2048                         sp_oe_n <= '0';
2049
2050                         --load lo addr.
2051                         dbuf_int_oe_n <= '0';
2052                         front_we(pcl_cmd, '0');
2053
2054                         next_cycle <= T4;
2055                     elsif exec_cycle = T4 then
2056                         d_print("rti 5");
2057                         --stack decrement stop.
2058                         back_we(sp_cmd, '1');
2059                         sp_pop_n <= '1';
2060                         front_we(pcl_cmd, '1');
2061
2062                         --pop pch
2063                         back_oe(sp_cmd, '0');
2064                         sp_oe_n <= '0';
2065                         --load hi addr.
2066                         dbuf_int_oe_n <= '0';
2067                         front_we(pch_cmd, '0');
2068
2069                         next_cycle <= T5;
2070                     elsif exec_cycle = T5 then
2071                         d_print("rti 6");
2072                         back_oe(sp_cmd, '1');
2073                         sp_oe_n <= '1';
2074                         --load hi addr.
2075                         dbuf_int_oe_n <= '1';
2076                         front_we(pch_cmd, '1');
2077
2078                         --increment pc.
2079                         next_cycle <= T0;
2080                     end if; --if exec_cycle = T1 then
2081
2082                 ----------------------------------------
2083                 -- A.5.6 jmp
2084                 ----------------------------------------
2085                 elsif instruction = conv_std_logic_vector(16#4c#, dsize) then
2086                     --abs
2087                     if exec_cycle = T1 then
2088                         d_print("jmp 2");
2089                         --fetch next opcode (abs low).
2090                         fetch_next;
2091
2092                         --latch abs low data.
2093                         dbuf_int_oe_n <= '0';
2094                         dl_al_we_n <= '0';
2095                         next_cycle <= T2;
2096                     elsif exec_cycle = T2 then
2097                         d_print("jmp 3");
2098                         dl_al_we_n <= '1';
2099
2100                         --fetch abs hi
2101                         fetch_next;
2102
2103                         --latch  in dlh
2104                         dbuf_int_oe_n <= '0';
2105                         dl_ah_we_n <= '0';
2106                         ---load pch.
2107                         front_we(pch_cmd, '0');
2108
2109                         next_cycle <= T0;
2110                     end if;
2111
2112                 elsif instruction = conv_std_logic_vector(16#6c#, dsize) then
2113                     --jmp (indir)
2114                     if exec_cycle = T1 then
2115                         d_print("jmp 2");
2116                         --fetch next opcode (abs low).
2117                         fetch_next;
2118
2119                         --latch abs low data.
2120                         dbuf_int_oe_n <= '0';
2121                         dl_al_we_n <= '0';
2122                         next_cycle <= T2;
2123                     elsif exec_cycle = T2 then
2124                         d_print("jmp 3");
2125                         dl_al_we_n <= '1';
2126
2127                         --fetch abs hi
2128                         fetch_next;
2129
2130                         --latch  in dlh
2131                         dbuf_int_oe_n <= '0';
2132                         dl_ah_we_n <= '0';
2133                         next_cycle <= T3;
2134
2135                     elsif exec_cycle = T3 then
2136                         fetch_stop;
2137                         dl_ah_we_n <= '1';
2138
2139                         --IAH/IAL > ADL
2140                         dl_ah_oe_n <= '0';
2141                         dl_al_oe_n <= '0';
2142                         front_we(pcl_cmd, '0');
2143                         next_cycle <= T4;
2144
2145                     elsif exec_cycle = T4 then
2146                         dl_ah_oe_n <= '0';
2147                         dl_al_oe_n <= '0';
2148                         front_we(pcl_cmd, '1');
2149
2150                         --IAH/IAL+1 > ADH
2151                         front_we(pch_cmd, '0');
2152                         indir_n <= '0';
2153
2154                         next_cycle <= T0;
2155
2156                     end if;
2157
2158
2159                 ----------------------------------------
2160                 -- A.5.7 return from soubroutine
2161                 ----------------------------------------
2162                 elsif instruction = conv_std_logic_vector(16#60#, dsize) then
2163                     if exec_cycle = T1 then
2164                         d_print("rts 2");
2165                         fetch_stop;
2166
2167                         --pop stack (decrement only)
2168                         back_oe(sp_cmd, '0');
2169                         back_we(sp_cmd, '0');
2170                         sp_pop_n <= '0';
2171                         sp_oe_n <= '0';
2172
2173                         next_cycle <= T2;
2174                     elsif exec_cycle = T2 then
2175                         d_print("rts 3");
2176
2177                         --pop pcl
2178                         back_oe(sp_cmd, '0');
2179                         back_we(sp_cmd, '0');
2180                         sp_pop_n <= '0';
2181                         sp_oe_n <= '0';
2182
2183                         --load lo addr.
2184                         dbuf_int_oe_n <= '0';
2185                         front_we(pcl_cmd, '0');
2186
2187                         next_cycle <= T3;
2188                     elsif exec_cycle = T3 then
2189                         d_print("rts 4");
2190                         --stack decrement stop.
2191                         back_we(sp_cmd, '1');
2192                         sp_pop_n <= '1';
2193                         front_we(pcl_cmd, '1');
2194
2195                         --pop pch
2196                         back_oe(sp_cmd, '0');
2197                         sp_oe_n <= '0';
2198                         --load hi addr.
2199                         dbuf_int_oe_n <= '0';
2200                         front_we(pch_cmd, '0');
2201
2202                         next_cycle <= T4;
2203                     elsif exec_cycle = T4 then
2204                         d_print("rts 5");
2205                         back_oe(sp_cmd, '1');
2206                         sp_oe_n <= '1';
2207                         --load hi addr.
2208                         dbuf_int_oe_n <= '1';
2209                         front_we(pch_cmd, '1');
2210                         --empty cycle.
2211                         --complying h/w manual...
2212                         next_cycle <= T5;
2213                     elsif exec_cycle = T5 then
2214                         d_print("rts 6");
2215
2216                         --increment pc.
2217                         fetch_next;
2218                         next_cycle <= T0;
2219                     end if; --if exec_cycle = T1 then
2220
2221                 ----------------------------------------
2222                 -- A.5.8 branch operations
2223                 ----------------------------------------
2224                 elsif instruction = conv_std_logic_vector(16#90#, dsize) then
2225                     d_print("bcc");
2226                     a58_branch (st_C, '0');
2227
2228                 elsif instruction = conv_std_logic_vector(16#b0#, dsize) then
2229                     d_print("bcs");
2230                     a58_branch (st_C, '1');
2231
2232                 elsif instruction = conv_std_logic_vector(16#f0#, dsize) then
2233                     d_print("beq");
2234                     a58_branch (st_Z, '1');
2235
2236                 elsif instruction = conv_std_logic_vector(16#30#, dsize) then
2237                     d_print("bmi");
2238                     a58_branch (st_N, '1');
2239
2240                 elsif instruction = conv_std_logic_vector(16#d0#, dsize) then
2241                     d_print("bne");
2242                     a58_branch (st_Z, '0');
2243
2244                 elsif instruction = conv_std_logic_vector(16#10#, dsize) then
2245                     d_print("bpl");
2246                     a58_branch (st_N, '0');
2247
2248                 elsif instruction = conv_std_logic_vector(16#50#, dsize) then
2249                     d_print("bvc");
2250                 elsif instruction = conv_std_logic_vector(16#70#, dsize) then
2251                     d_print("bvs");
2252
2253                 else
2254                     ---unknown instruction!!!!
2255                     assert false
2256                         report "======== unknow instruction "
2257                             & conv_hex8(conv_integer(instruction))
2258                         severity failure;
2259                 end if; --if instruction = conv_std_logic_vector(16#0a#, dsize)
2260
2261             elsif exec_cycle = R0 then
2262                 d_print(string'("reset"));
2263
2264                 front_we(pch_cmd, '1');
2265                 back_we(pcl_cmd, '1');
2266
2267                 --initialize port...
2268                 inst_we_n <= '1';
2269                 ad_oe_n <= '1';
2270                 dbuf_int_oe_n <= '1';
2271                 dl_al_we_n <= '1';
2272                 dl_ah_we_n <= '1';
2273                 dl_al_oe_n <= '1';
2274                 dl_ah_oe_n <= '1';
2275                 dl_dh_oe_n <= '1';
2276                 pcl_inc_n <= '1';
2277                 pcl_cmd <= "1111";
2278                 pch_cmd <= "1111";
2279                 sp_cmd <= "1111";
2280                 sp_oe_n <= '1';
2281                 sp_push_n <= '1';
2282                 sp_pop_n <= '1';
2283                 acc_cmd <= "1111";
2284                 x_cmd <= "1111";
2285                 y_cmd <= "1111";
2286
2287                 abs_xy_n <= '1';
2288                 pg_next_n <= '1';
2289                 zp_n <= '1';
2290                 zp_xy_n <= '1';
2291                 rel_calc_n <= '1';
2292                 indir_n <= '1';
2293                 indir_x_n <= '1';
2294                 indir_y_n <= '1';
2295                 arith_en_n <= '1';
2296
2297                 stat_dec_oe_n <= '1';
2298                 stat_bus_oe_n <= '1';
2299                 stat_set_flg_n <= '1';
2300                 stat_flg <= '1';
2301                 stat_bus_all_n <= '1';
2302                 stat_bus_nz_n <= '1';
2303                 stat_alu_we_n <= '1';
2304
2305                 r_vec_oe_n <= '1';
2306                 n_vec_oe_n <= '1';
2307                 i_vec_oe_n <= '1';
2308                 nmi_handled_n <= '1';
2309                 r_nw <= '1';
2310
2311                 next_cycle <= R1;
2312             elsif exec_cycle = R1 or exec_cycle = N1 then
2313                 pcl_cmd <= "1111";
2314                 pcl_inc_n <= '1';
2315                 inst_we_n <= '1';
2316                 dl_al_oe_n <= '1';
2317
2318                 --push pch.
2319                 d_print("R1");
2320                 ad_oe_n <= '0';
2321                 sp_push_n <= '0';
2322                 sp_oe_n <= '0';
2323                 pch_cmd <= "0111";
2324                 --front_oe(pch_cmd, '0');
2325                 back_oe(sp_cmd, '0');
2326                 back_we(sp_cmd, '0');
2327                 r_nw <= '0';
2328
2329                 if exec_cycle = R1 then
2330                     next_cycle <= R2;
2331                 elsif exec_cycle = N1 then
2332                     next_cycle <= N2;
2333                 end if;
2334
2335             elsif exec_cycle = R2 or exec_cycle = N2 then
2336                 front_oe(pch_cmd, '1');
2337
2338                --push pcl.
2339                 sp_push_n <= '0';
2340                 sp_oe_n <= '0';
2341                 front_oe(pcl_cmd, '0');
2342                 back_oe(sp_cmd, '0');
2343                 back_we(sp_cmd, '0');
2344                 r_nw <= '0';
2345
2346                 if exec_cycle = R2 then
2347                     next_cycle <= R3;
2348                 elsif exec_cycle = N2 then
2349                     next_cycle <= N3;
2350                 end if;
2351
2352             elsif exec_cycle = R3 or exec_cycle = N3 then
2353                 front_oe(pcl_cmd, '1');
2354
2355                --push status.
2356                 sp_push_n <= '0';
2357                 sp_oe_n <= '0';
2358                 stat_bus_oe_n <= '0';
2359                 back_oe(sp_cmd, '0');
2360                 back_we(sp_cmd, '0');
2361                 r_nw <= '0';
2362
2363                 if exec_cycle = R3 then
2364                     next_cycle <= R4;
2365                 elsif exec_cycle = N3 then
2366                     next_cycle <= N4;
2367                 end if;
2368
2369             elsif exec_cycle = R4 or exec_cycle = N4 then
2370                 stat_bus_oe_n <= '1';
2371                 sp_push_n <= '1';
2372                 sp_oe_n <= '1';
2373                 front_oe(pcl_cmd, '1');
2374                 back_oe(sp_cmd, '1');
2375                 back_we(sp_cmd, '1');
2376
2377                 --fetch reset vector low
2378                 r_nw <= '1';
2379                 dbuf_int_oe_n <= '0';
2380                 front_we(pcl_cmd, '0');
2381
2382                 if exec_cycle = R4 then
2383                     r_vec_oe_n <= '0';
2384                     next_cycle <= R5;
2385                 elsif exec_cycle = N4 then
2386                     n_vec_oe_n <= '0';
2387                     next_cycle <= N5;
2388                 end if;
2389
2390             elsif exec_cycle = R5 or exec_cycle = N5 then
2391                 front_we(pcl_cmd, '1');
2392
2393                 --fetch reset vector hi
2394                 front_we(pch_cmd, '0');
2395                 indir_n <= '0';
2396
2397                 if exec_cycle = N5 then
2398                     nmi_handled_n <= '0';
2399                 end if;
2400                 --start execute cycle.
2401                 next_cycle <= T0;
2402
2403             elsif exec_cycle(5) = '1' then
2404                 ---pc increment and next page.
2405                 d_print(string'("pch next page..."));
2406                 --pcl stop increment
2407                 pcl_inc_n <= '1';
2408                 back_we(pcl_cmd, '1');
2409                 --pch increment
2410                 back_we(pch_cmd, '0');
2411                 back_oe(pch_cmd, '0');
2412
2413                 if ('0' & exec_cycle(4 downto 0) = T0) then
2414                     --do the t0 identical routine.
2415                     disable_pins;
2416                     inst_we_n <= '1';
2417                     r_nw <= '1';
2418
2419                 elsif ('0' & exec_cycle(4 downto 0) = T1) then
2420                     --if fetch cycle, preserve instrution register
2421                     inst_we_n <= '1';
2422
2423                     --TODO: must handle for jmp case???
2424                 elsif ('0' & exec_cycle(4 downto 0) = T2) then
2425                     --disable previous we_n gate.
2426                     --t1 cycle is fetch low oprand.
2427                     dl_al_we_n <= '1';
2428                 elsif ('0' & exec_cycle(4 downto 0) = T3) then
2429                     --t2 cycle is fetch high oprand.
2430                     dl_ah_we_n <= '1';
2431                 end if;
2432
2433             end if; --if exec_cycle = T0 then
2434
2435         end if; --if (set_clk'event and set_clk = '1')
2436
2437     end process;
2438
2439 end rtl;
2440