- cmp zp, x

- cmp abs
- cmp abs, x
- cmp indir, y supported.
- test case added.

diff --git a/simulation/cpu/decoder.vhd b/simulation/cpu/decoder.vhd
index 21acf79..162ee7f 100644 (file)
--- a/simulation/cpu/decoder.vhd
+++ b/simulation/cpu/decoder.vhd
@@ -480,6 +480,7 @@ begin
     front_we(acc_cmd, '1');
     front_we(x_cmd, '1');
     front_we(y_cmd, '1');
+    stat_alu_we_n <= '1';
 end  procedure;
 
 procedure a2_abs_xy (is_x : in boolean) is
@@ -1319,14 +1320,32 @@ end  procedure;
                 elsif instruction  = conv_std_logic_vector(16#d5#, dsize) then
                     --zp, x
                     d_print("cmp");
+                    a2_zp_xy(true);
+                    if exec_cycle = T3 then
+                        arith_en_n <= '0';
+                        back_oe(acc_cmd, '0');
+                        set_nzc_from_alu;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#cd#, dsize) then
                     --abs
                     d_print("cmp");
+                    a2_abs;
+                    if exec_cycle = T3 then
+                        arith_en_n <= '0';
+                        back_oe(acc_cmd, '0');
+                        set_nzc_from_alu;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#dd#, dsize) then
                     --abs, x
                     d_print("cmp");
+                    a2_abs_xy(true);
+                    if exec_cycle = T3 or exec_cycle = T4 then
+                        arith_en_n <= '0';
+                        back_oe(acc_cmd, '0');
+                        set_nzc_from_alu;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#d9#, dsize) then
                     --abs, y
@@ -1345,6 +1364,12 @@ end  procedure;
                 elsif instruction  = conv_std_logic_vector(16#d1#, dsize) then
                     --(indir), y
                     d_print("cmp");
+                    a2_indir_y;
+                    if exec_cycle = T4 or exec_cycle = T5 then
+                        arith_en_n <= '0';
+                        back_oe(acc_cmd, '0');
+                        set_nzc_from_alu;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#e0#, dsize) then
                     --imm

diff --git a/tools/test-image/sample1.asm b/tools/test-image/sample1.asm
index 51f8ce4..95f82a4 100644 (file)
--- a/tools/test-image/sample1.asm
+++ b/tools/test-image/sample1.asm
@@ -447,6 +447,33 @@ boundary_3_4:
     ;c9&07=01\r
     and ($07), y\r
 \r
+    ;;cmp zp, x/abs/abs, x/indir, y\r
+    lda #$de\r
+    ldx #$e4\r
+    sta $a4\r
+    ;c5-de=-19 > (e7)\r
+    lda #$c5\r
+    cmp $c0, x\r
+\r
+    sec\r
+    lda #$75\r
+    stx $0734\r
+    ;75-e4=-6f > 91\r
+    cmp $0650, x\r
+\r
+    ldx #$c9\r
+    stx $0825\r
+    lda #$34\r
+    sta $07\r
+    lda #$07\r
+    sta $08\r
+    ldy #$f1\r
+    lda #$c9\r
+    ;page crossing\r
+    ;c9-c9=0\r
+    cmp ($07), y\r
+\r
+\r
     ;;infinite loop.\r
 mainloop:\r
        jmp     mainloop\r