2 use IEEE.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
5 entity testbench_motones_sim is
6 end testbench_motones_sim;
8 architecture stimulus of testbench_motones_sim is
11 base_clk : in std_logic;
13 joypad1 : in std_logic_vector(7 downto 0);
14 joypad2 : in std_logic_vector(7 downto 0);
15 vga_clk : out std_logic;
16 h_sync_n : out std_logic;
17 v_sync_n : out std_logic;
18 r : out std_logic_vector(3 downto 0);
19 g : out std_logic_vector(3 downto 0);
20 b : out std_logic_vector(3 downto 0)
25 port ( vga_clk : in std_logic;
27 h_sync_n : in std_logic;
28 v_sync_n : in std_logic;
29 r : in std_logic_vector(3 downto 0);
30 g : in std_logic_vector(3 downto 0);
31 b : in std_logic_vector(3 downto 0)
35 signal base_clk : std_logic;
36 signal vga_clk : std_logic;
37 signal reset_input : std_logic;
39 signal h_sync_n : std_logic;
40 signal v_sync_n : std_logic;
41 signal r : std_logic_vector(3 downto 0);
42 signal g : std_logic_vector(3 downto 0);
43 signal b : std_logic_vector(3 downto 0);
44 signal joypad1 : std_logic_vector(7 downto 0);
45 signal joypad2 : std_logic_vector(7 downto 0);
47 constant powerup_time : time := 2 us;
48 constant reset_time : time := 890 ns;
50 ---clock frequency = 21,477,270 (21 MHz)
51 --constant base_clock_time : time := 46 ns;
53 --DE1 base clock = 50 MHz
54 constant base_clock_time : time := 20 ns;
58 sim_board : motones_sim port map (base_clk, reset_input, joypad1, joypad2,
59 vga_clk, h_sync_n, v_sync_n, r, g, b);
61 dummy_vga_disp : vga_device
62 port map (vga_clk, reset_input, h_sync_n, v_sync_n, r, g, b);
68 wait for powerup_time;
77 --- generate base clock.
81 wait for base_clock_time / 2;
83 wait for base_clock_time / 2;