src/gen6_mfc.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Zhou Chang <chang.zhou@intel.com>
  26  *
  27  */
  28
  29 #ifndef _GEN6_MFC_H_
  30 #define _GEN6_MFC_H_
  31
  32 #include <drm.h>
  33 #include <i915_drm.h>
  34 #include <intel_bufmgr.h>
  35
  36 #include "i965_encoder.h"
  37 #include "i965_gpe_utils.h"
  38
  39 struct encode_state;
  40
  41 #define MAX_MFC_REFERENCE_SURFACES      16
  42 #define NUM_MFC_DMV_BUFFERS             34
  43
  44 #define INTRA_MB_FLAG_MASK              0x00002000
  45
  46 /* The space required for slice header SLICE_STATE + header.
  47  * Is it enough? */
  48 #define SLICE_HEADER            80
  49
  50 /* the space required for slice tail. */
  51 #define SLICE_TAIL          16
  52
  53
  54 #define MFC_BATCHBUFFER_AVC_INTRA       0
  55 #define MFC_BATCHBUFFER_AVC_INTER       1
  56 #define NUM_MFC_KERNEL                  2
  57
  58 #define BIND_IDX_VME_OUTPUT             0
  59 #define BIND_IDX_MFC_SLICE_HEADER       1
  60 #define BIND_IDX_MFC_BATCHBUFFER        2
  61
  62 #define CMD_LEN_IN_OWORD        4
  63
  64 #define BRC_CLIP(x, min, max)                                   \
  65     {                                                           \
  66         x = ((x > (max)) ? (max) : ((x < (min)) ? (min) : x));  \
  67     }
  68
  69 #define BRC_P_B_QP_DIFF 4
  70 #define BRC_I_P_QP_DIFF 2
  71 #define BRC_I_B_QP_DIFF (BRC_I_P_QP_DIFF + BRC_P_B_QP_DIFF)
  72
  73 #define BRC_PWEIGHT 0.6  /* weight if P slice with comparison to I slice */
  74 #define BRC_BWEIGHT 0.25 /* weight if B slice with comparison to I slice */
  75
  76 #define BRC_QP_MAX_CHANGE 5 /* maximum qp modification */
  77 #define BRC_CY 0.1 /* weight for */
  78 #define BRC_CX_UNDERFLOW 5.
  79 #define BRC_CX_OVERFLOW -4.
  80
  81 #define BRC_PI_0_5 1.5707963267948966192313216916398
  82
  83 typedef enum {
  84     VME_V_PRED = 0,
  85     VME_H_PRED = 1,
  86     VME_DC_PRED = 2,
  87     VME_PL_PRED = 3,
  88
  89     VME_MB_INTRA_MODE_COUNT
  90 } VME_MB_INTRA_PRED_MODE;
  91
  92 typedef enum {
  93     PAK_DC_PRED = 0,
  94     PAK_V_PRED = 1,
  95     PAK_H_PRED = 2,
  96     PAK_TM_PRED = 3,
  97
  98     PAK_MB_INTRA_MODE_COUNT
  99 } VP8_PAK_MB_INTRA_PRED_MODE;
 100
 101 typedef enum {
 102     VME_B_V_PRED = 0,
 103     VME_B_H_PRED = 1,
 104     VME_B_DC_PRED = 2,
 105     VME_B_DL_PRED = 3,
 106     VME_B_DR_PRED = 4,
 107     VME_B_VR_PRED = 5,
 108     VME_B_HD_PRED = 6,
 109     VME_B_VL_PRED = 7,
 110     VME_B_HU_PRED = 8,
 111
 112     VME_B_INTRA_MODE_COUNT
 113 } VME_BLOCK_INTRA_PRED_MODE;
 114
 115 typedef enum {
 116     PAK_B_DC_PRED = 0,
 117     PAK_B_TM_PRED = 1,
 118     PAK_B_VE_PRED = 2,
 119     PAK_B_HE_PRED = 3,
 120     PAK_B_LD_PRED = 4,
 121     PAK_B_RD_PRED = 5,
 122     PAK_B_VR_PRED = 6,
 123     PAK_B_VL_PRED = 7,
 124     PAK_B_HD_PRED = 8,
 125     PAK_B_HU_PRED = 9,
 126
 127     PAK_B_INTRA_MODE_COUNT
 128 } VP8_PAK_BLOCK_INTRA_PRED_MODE;
 129
 130 typedef struct {
 131     int vme_intra_mb_mode;
 132     int vp8_pak_intra_mb_mode;
 133 } vp8_intra_mb_mode_map_t;
 134
 135 typedef struct {
 136     int vme_intra_block_mode;
 137     int vp8_pak_intra_block_mode;
 138 } vp8_intra_block_mode_map_t;
 139
 140 typedef enum _gen6_brc_status {
 141     BRC_NO_HRD_VIOLATION = 0,
 142     BRC_UNDERFLOW = 1,
 143     BRC_OVERFLOW = 2,
 144     BRC_UNDERFLOW_WITH_MAX_QP = 3,
 145     BRC_OVERFLOW_WITH_MIN_QP = 4,
 146 } gen6_brc_status;
 147
 148 struct gen6_mfc_avc_surface_aux {
 149     dri_bo *dmv_top;
 150     dri_bo *dmv_bottom;
 151 };
 152
 153 struct gen6_mfc_context {
 154     struct {
 155         unsigned int width;
 156         unsigned int height;
 157         unsigned int w_pitch;
 158         unsigned int h_pitch;
 159     } surface_state;
 160
 161     //MFX_PIPE_BUF_ADDR_STATE
 162     struct {
 163         dri_bo *bo;
 164     } post_deblocking_output;           //OUTPUT: reconstructed picture
 165
 166     struct {
 167         dri_bo *bo;
 168     } pre_deblocking_output;            //OUTPUT: reconstructed picture with deblocked
 169
 170     struct {
 171         dri_bo *bo;
 172     } uncompressed_picture_source;      //INPUT: original compressed image
 173
 174     struct {
 175         dri_bo *bo;
 176     } intra_row_store_scratch_buffer;   //INTERNAL:
 177
 178     struct {
 179         dri_bo *bo;
 180     } macroblock_status_buffer;         //INTERNAL:
 181
 182     struct {
 183         dri_bo *bo;
 184     } deblocking_filter_row_store_scratch_buffer;       //INTERNAL:
 185
 186     struct {
 187         dri_bo *bo;
 188     } reference_surfaces[MAX_MFC_REFERENCE_SURFACES];   //INTERNAL: refrence surfaces
 189
 190     //MFX_IND_OBJ_BASE_ADDR_STATE
 191     struct {
 192         dri_bo *bo;
 193     } mfc_indirect_mv_object;           //INPUT: the blocks' mv info
 194
 195     struct {
 196         dri_bo *bo;
 197         int offset;
 198         int end_offset;
 199     } mfc_indirect_pak_bse_object;      //OUTPUT: the compressed bitstream
 200
 201     //MFX_BSP_BUF_BASE_ADDR_STATE
 202     struct {
 203         dri_bo *bo;
 204     } bsd_mpc_row_store_scratch_buffer; //INTERNAL:
 205
 206     //MFX_AVC_DIRECTMODE_STATE
 207     struct {
 208         dri_bo *bo;
 209     } direct_mv_buffers[NUM_MFC_DMV_BUFFERS];   //INTERNAL: 0-31 as input,32 and 33 as output
 210
 211     //Bit rate tracking context
 212     struct {
 213         unsigned int MaxQpNegModifier;
 214         unsigned int MaxQpPosModifier;
 215         unsigned char Correct[6];
 216         unsigned char GrowInit;
 217         unsigned char GrowResistance;
 218         unsigned char ShrinkInit;
 219         unsigned char ShrinkResistance;
 220     } bit_rate_control_context[3];      //INTERNAL: for I, P, B frames
 221
 222     struct {
 223         int mode;
 224         int gop_nums[MAX_MFC_REFERENCE_SURFACES][3];
 225         int target_frame_size[MAX_TEMPORAL_LAYERS][3]; // I,P,B
 226         int qp_prime_y[MAX_TEMPORAL_LAYERS][3];
 227         double bits_per_frame[MAX_TEMPORAL_LAYERS];
 228         double qpf_rounding_accumulator[MAX_TEMPORAL_LAYERS];
 229         int bits_prev_frame[MAX_TEMPORAL_LAYERS];
 230         int prev_slice_type[MAX_TEMPORAL_LAYERS];
 231     } brc;
 232
 233     struct {
 234         double current_buffer_fullness[MAX_TEMPORAL_LAYERS];
 235         double target_buffer_fullness[MAX_TEMPORAL_LAYERS];
 236         double buffer_capacity[MAX_TEMPORAL_LAYERS];
 237         unsigned int buffer_size[MAX_TEMPORAL_LAYERS];
 238         unsigned int violation_noted;
 239     } hrd;
 240
 241     //HRD control context
 242     struct {
 243         int i_bit_rate_value;
 244
 245         int i_initial_cpb_removal_delay;
 246         int i_cpb_removal_delay;
 247
 248         int i_frame_number;
 249
 250         int i_initial_cpb_removal_delay_length;
 251         int i_cpb_removal_delay_length;
 252         int i_dpb_output_delay_length;
 253     } vui_hrd;
 254
 255     struct {
 256         unsigned char *vp8_frame_header;
 257         unsigned int frame_header_bit_count;
 258         unsigned int frame_header_qindex_update_pos;
 259         unsigned int frame_header_lf_update_pos;
 260         unsigned int frame_header_token_update_pos;
 261         unsigned int frame_header_bin_mv_upate_pos;
 262
 263         unsigned int intermediate_partition_offset[8];
 264         unsigned int intermediate_buffer_max_size;
 265         unsigned int final_frame_byte_offset;
 266
 267         unsigned char mb_segment_tree_probs[3];
 268         unsigned char y_mode_probs[4];
 269         unsigned char uv_mode_probs[3];
 270         unsigned char mv_probs[2][19];
 271
 272         unsigned char prob_skip_false;
 273         unsigned char prob_intra;
 274         unsigned char prob_last;
 275         unsigned char prob_gf;
 276
 277         dri_bo *frame_header_bo;
 278         dri_bo *intermediate_bo;
 279         dri_bo *final_frame_bo;
 280         dri_bo *stream_out_bo;
 281         dri_bo *coeff_probs_stream_in_bo;
 282         dri_bo *token_statistics_bo;
 283         dri_bo *mpc_row_store_bo;
 284     } vp8_state;
 285
 286     //"buffered_QMatrix" will be used to buffer the QMatrix if the app sends one.
 287     // Or else, we will load a default QMatrix from the driver for JPEG encode.
 288     VAQMatrixBufferJPEG buffered_qmatrix;
 289     struct i965_gpe_context gpe_context;
 290     struct i965_buffer_surface mfc_batchbuffer_surface;
 291     struct intel_batchbuffer *aux_batchbuffer;
 292     struct i965_buffer_surface aux_batchbuffer_surface;
 293
 294     void (*pipe_mode_select)(VADriverContextP ctx,
 295                              int standard_select,
 296                              struct intel_encoder_context *encoder_context);
 297     void (*set_surface_state)(VADriverContextP ctx,
 298                               struct intel_encoder_context *encoder_context);
 299     void (*ind_obj_base_addr_state)(VADriverContextP ctx,
 300                                     struct intel_encoder_context *encoder_context);
 301     void (*avc_img_state)(VADriverContextP ctx,
 302                           struct encode_state *encode_state,
 303                           struct intel_encoder_context *encoder_context);
 304     void (*avc_qm_state)(VADriverContextP ctx,
 305                          struct encode_state *encode_state,
 306                          struct intel_encoder_context *encoder_context);
 307     void (*avc_fqm_state)(VADriverContextP ctx,
 308                           struct encode_state *encode_state,
 309                           struct intel_encoder_context *encoder_context);
 310     void (*insert_object)(VADriverContextP ctx,
 311                           struct intel_encoder_context *encoder_context,
 312                           unsigned int *insert_data,
 313                           int lenght_in_dws, int data_bits_in_last_dw,
 314                           int skip_emul_byte_count,
 315                           int is_last_header, int is_end_of_slice,
 316                           int emulation_flag,
 317                           struct intel_batchbuffer *batch);
 318     void (*buffer_suface_setup)(VADriverContextP ctx,
 319                                 struct i965_gpe_context *gpe_context,
 320                                 struct i965_buffer_surface *buffer_surface,
 321                                 unsigned long binding_table_offset,
 322                                 unsigned long surface_state_offset);
 323 };
 324
 325 VAStatus gen6_mfc_pipeline(VADriverContextP ctx,
 326                            VAProfile profile,
 327                            struct encode_state *encode_state,
 328                            struct intel_encoder_context *encoder_context);
 329 void gen6_mfc_context_destroy(void *context);
 330
 331 extern
 332 Bool gen6_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
 333
 334 extern
 335 Bool gen7_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
 336
 337 extern
 338 Bool gen75_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
 339
 340
 341 extern int intel_mfc_update_hrd(struct encode_state *encode_state,
 342                                 struct intel_encoder_context *encoder_context,
 343                                 int frame_bits);
 344
 345 extern int intel_mfc_brc_postpack(struct encode_state *encode_state,
 346                                   struct intel_encoder_context *encoder_context,
 347                                   int frame_bits);
 348
 349 extern void intel_mfc_hrd_context_update(struct encode_state *encode_state,
 350                                          struct gen6_mfc_context *mfc_context);
 351
 352 extern int intel_mfc_interlace_check(VADriverContextP ctx,
 353                                      struct encode_state *encode_state,
 354                                      struct intel_encoder_context *encoder_context);
 355
 356 extern void intel_mfc_brc_prepare(struct encode_state *encode_state,
 357                                   struct intel_encoder_context *encoder_context);
 358
 359 extern void intel_mfc_avc_pipeline_header_programing(VADriverContextP ctx,
 360                                                      struct encode_state *encode_state,
 361                                                      struct intel_encoder_context *encoder_context,
 362                                                      struct intel_batchbuffer *slice_batch);
 363
 364 extern VAStatus intel_mfc_avc_prepare(VADriverContextP ctx,
 365                                       struct encode_state *encode_state,
 366                                       struct intel_encoder_context *encoder_context);
 367
 368 extern int intel_avc_enc_slice_type_fixup(int type);
 369
 370 extern void
 371 intel_mfc_avc_ref_idx_state(VADriverContextP ctx,
 372                             struct encode_state *encode_state,
 373                             struct intel_encoder_context *encoder_context);
 374
 375 extern
 376 Bool gen8_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
 377
 378 extern void
 379 intel_avc_insert_aud_packed_data(VADriverContextP ctx,
 380                                  struct encode_state *encode_state,
 381                                  struct intel_encoder_context *encoder_context,
 382                                  struct intel_batchbuffer *batch);
 383
 384 extern void
 385 intel_avc_slice_insert_packed_data(VADriverContextP ctx,
 386                                    struct encode_state *encode_state,
 387                                    struct intel_encoder_context *encoder_context,
 388                                    int slice_index,
 389                                    struct intel_batchbuffer *slice_batch);
 390
 391 extern
 392 Bool gen9_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
 393
 394 #endif  /* _GEN6_MFC_BCS_H_ */