tests/amdgpu/vcn_tests.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22 */
  23
  24 #include <stdio.h>
  25 #include <inttypes.h>
  26
  27 #include "CUnit/Basic.h"
  28
  29 #include "util_math.h"
  30
  31 #include "amdgpu_test.h"
  32 #include "amdgpu_drm.h"
  33 #include "amdgpu_internal.h"
  34 #include "decode_messages.h"
  35
  36 #define IB_SIZE         4096
  37 #define MAX_RESOURCES   16
  38
  39 struct amdgpu_vcn_bo {
  40         amdgpu_bo_handle handle;
  41         amdgpu_va_handle va_handle;
  42         uint64_t addr;
  43         uint64_t size;
  44         uint8_t *ptr;
  45 };
  46
  47 struct amdgpu_vcn_reg {
  48         uint32_t data0;
  49         uint32_t data1;
  50         uint32_t cmd;
  51         uint32_t nop;
  52         uint32_t cntl;
  53 };
  54
  55 static amdgpu_device_handle device_handle;
  56 static uint32_t major_version;
  57 static uint32_t minor_version;
  58 static uint32_t family_id;
  59
  60 static amdgpu_context_handle context_handle;
  61 static amdgpu_bo_handle ib_handle;
  62 static amdgpu_va_handle ib_va_handle;
  63 static uint64_t ib_mc_address;
  64 static uint32_t *ib_cpu;
  65
  66 static amdgpu_bo_handle resources[MAX_RESOURCES];
  67 static unsigned num_resources;
  68 static struct amdgpu_vcn_reg reg;
  69
  70 static void amdgpu_cs_vcn_dec_create(void);
  71 static void amdgpu_cs_vcn_dec_decode(void);
  72 static void amdgpu_cs_vcn_dec_destroy(void);
  73
  74 static void amdgpu_cs_vcn_enc_create(void);
  75 static void amdgpu_cs_vcn_enc_encode(void);
  76 static void amdgpu_cs_vcn_enc_destroy(void);
  77
  78 CU_TestInfo vcn_tests[] = {
  79
  80         { "VCN DEC create",  amdgpu_cs_vcn_dec_create },
  81         { "VCN DEC decode",  amdgpu_cs_vcn_dec_decode },
  82         { "VCN DEC destroy",  amdgpu_cs_vcn_dec_destroy },
  83
  84         { "VCN ENC create",  amdgpu_cs_vcn_enc_create },
  85         { "VCN ENC decode",  amdgpu_cs_vcn_enc_encode },
  86         { "VCN ENC destroy",  amdgpu_cs_vcn_enc_destroy },
  87         CU_TEST_INFO_NULL,
  88 };
  89
  90 CU_BOOL suite_vcn_tests_enable(void)
  91 {
  92
  93         if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
  94                                    &minor_version, &device_handle))
  95                 return CU_FALSE;
  96
  97         family_id = device_handle->info.family_id;
  98
  99         if (amdgpu_device_deinitialize(device_handle))
 100                         return CU_FALSE;
 101
 102
 103         if (family_id < AMDGPU_FAMILY_RV) {
 104                 printf("\n\nThe ASIC NOT support VCN, suite disabled\n");
 105                 return CU_FALSE;
 106         }
 107
 108         if (family_id == AMDGPU_FAMILY_RV) {
 109                 reg.data0 = 0x81c4;
 110                 reg.data1 = 0x81c5;
 111                 reg.cmd = 0x81c3;
 112                 reg.nop = 0x81ff;
 113                 reg.cntl = 0x81c6;
 114         } else if (family_id == AMDGPU_FAMILY_NV) {
 115                 reg.data0 = 0x504;
 116                 reg.data1 = 0x505;
 117                 reg.cmd = 0x503;
 118                 reg.nop = 0x53f;
 119                 reg.cntl = 0x506;
 120         } else
 121                 return CU_FALSE;
 122
 123         return CU_TRUE;
 124 }
 125
 126 int suite_vcn_tests_init(void)
 127 {
 128         int r;
 129
 130         r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
 131                                      &minor_version, &device_handle);
 132         if (r)
 133                 return CUE_SINIT_FAILED;
 134
 135         family_id = device_handle->info.family_id;
 136
 137         r = amdgpu_cs_ctx_create(device_handle, &context_handle);
 138         if (r)
 139                 return CUE_SINIT_FAILED;
 140
 141         r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
 142                                     AMDGPU_GEM_DOMAIN_GTT, 0,
 143                                     &ib_handle, (void**)&ib_cpu,
 144                                     &ib_mc_address, &ib_va_handle);
 145         if (r)
 146                 return CUE_SINIT_FAILED;
 147
 148         return CUE_SUCCESS;
 149 }
 150
 151 int suite_vcn_tests_clean(void)
 152 {
 153         int r;
 154
 155         r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
 156                              ib_mc_address, IB_SIZE);
 157         if (r)
 158                 return CUE_SCLEAN_FAILED;
 159
 160         r = amdgpu_cs_ctx_free(context_handle);
 161         if (r)
 162                 return CUE_SCLEAN_FAILED;
 163
 164         r = amdgpu_device_deinitialize(device_handle);
 165         if (r)
 166                 return CUE_SCLEAN_FAILED;
 167
 168         return CUE_SUCCESS;
 169 }
 170
 171 static int submit(unsigned ndw, unsigned ip)
 172 {
 173         struct amdgpu_cs_request ibs_request = {0};
 174         struct amdgpu_cs_ib_info ib_info = {0};
 175         struct amdgpu_cs_fence fence_status = {0};
 176         uint32_t expired;
 177         int r;
 178
 179         ib_info.ib_mc_address = ib_mc_address;
 180         ib_info.size = ndw;
 181
 182         ibs_request.ip_type = ip;
 183
 184         r = amdgpu_bo_list_create(device_handle, num_resources, resources,
 185                                   NULL, &ibs_request.resources);
 186         if (r)
 187                 return r;
 188
 189         ibs_request.number_of_ibs = 1;
 190         ibs_request.ibs = &ib_info;
 191         ibs_request.fence_info.handle = NULL;
 192
 193         r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
 194         if (r)
 195                 return r;
 196
 197         r = amdgpu_bo_list_destroy(ibs_request.resources);
 198         if (r)
 199                 return r;
 200
 201         fence_status.context = context_handle;
 202         fence_status.ip_type = ip;
 203         fence_status.fence = ibs_request.seq_no;
 204
 205         r = amdgpu_cs_query_fence_status(&fence_status,
 206                                          AMDGPU_TIMEOUT_INFINITE,
 207                                          0, &expired);
 208         if (r)
 209                 return r;
 210
 211         return 0;
 212 }
 213
 214 static void alloc_resource(struct amdgpu_vcn_bo *vcn_bo,
 215                         unsigned size, unsigned domain)
 216 {
 217         struct amdgpu_bo_alloc_request req = {0};
 218         amdgpu_bo_handle buf_handle;
 219         amdgpu_va_handle va_handle;
 220         uint64_t va = 0;
 221         int r;
 222
 223         req.alloc_size = ALIGN(size, 4096);
 224         req.preferred_heap = domain;
 225         r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
 226         CU_ASSERT_EQUAL(r, 0);
 227         r = amdgpu_va_range_alloc(device_handle,
 228                                   amdgpu_gpu_va_range_general,
 229                                   req.alloc_size, 1, 0, &va,
 230                                   &va_handle, 0);
 231         CU_ASSERT_EQUAL(r, 0);
 232         r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
 233                             AMDGPU_VA_OP_MAP);
 234         CU_ASSERT_EQUAL(r, 0);
 235         vcn_bo->addr = va;
 236         vcn_bo->handle = buf_handle;
 237         vcn_bo->size = req.alloc_size;
 238         vcn_bo->va_handle = va_handle;
 239         r = amdgpu_bo_cpu_map(vcn_bo->handle, (void **)&vcn_bo->ptr);
 240         CU_ASSERT_EQUAL(r, 0);
 241         memset(vcn_bo->ptr, 0, size);
 242         r = amdgpu_bo_cpu_unmap(vcn_bo->handle);
 243         CU_ASSERT_EQUAL(r, 0);
 244 }
 245
 246 static void free_resource(struct amdgpu_vcn_bo *vcn_bo)
 247 {
 248         int r;
 249
 250         r = amdgpu_bo_va_op(vcn_bo->handle, 0, vcn_bo->size,
 251                             vcn_bo->addr, 0, AMDGPU_VA_OP_UNMAP);
 252         CU_ASSERT_EQUAL(r, 0);
 253
 254         r = amdgpu_va_range_free(vcn_bo->va_handle);
 255         CU_ASSERT_EQUAL(r, 0);
 256
 257         r = amdgpu_bo_free(vcn_bo->handle);
 258         CU_ASSERT_EQUAL(r, 0);
 259         memset(vcn_bo, 0, sizeof(*vcn_bo));
 260 }
 261
 262 static void vcn_dec_cmd(uint64_t addr, unsigned cmd, int *idx)
 263 {
 264         ib_cpu[(*idx)++] = reg.data0;
 265         ib_cpu[(*idx)++] = addr;
 266         ib_cpu[(*idx)++] = reg.data1;
 267         ib_cpu[(*idx)++] = addr >> 32;
 268         ib_cpu[(*idx)++] = reg.cmd;
 269         ib_cpu[(*idx)++] = cmd << 1;
 270 }
 271
 272 static void amdgpu_cs_vcn_dec_create(void)
 273 {
 274         struct amdgpu_vcn_bo msg_buf;
 275         int len, r;
 276
 277         num_resources  = 0;
 278         alloc_resource(&msg_buf, 4096, AMDGPU_GEM_DOMAIN_GTT);
 279         resources[num_resources++] = msg_buf.handle;
 280         resources[num_resources++] = ib_handle;
 281
 282         r = amdgpu_bo_cpu_map(msg_buf.handle, (void **)&msg_buf.ptr);
 283         CU_ASSERT_EQUAL(r, 0);
 284
 285         memset(msg_buf.ptr, 0, 4096);
 286         memcpy(msg_buf.ptr, vcn_dec_create_msg, sizeof(vcn_dec_create_msg));
 287
 288         len = 0;
 289         ib_cpu[len++] = reg.data0;
 290         ib_cpu[len++] = msg_buf.addr;
 291         ib_cpu[len++] = reg.data1;
 292         ib_cpu[len++] = msg_buf.addr >> 32;
 293         ib_cpu[len++] = reg.cmd;
 294         ib_cpu[len++] = 0;
 295         for (; len % 16; ) {
 296                 ib_cpu[len++] = reg.nop;
 297                 ib_cpu[len++] = 0;
 298         }
 299
 300         r = submit(len, AMDGPU_HW_IP_VCN_DEC);
 301         CU_ASSERT_EQUAL(r, 0);
 302
 303         free_resource(&msg_buf);
 304 }
 305
 306 static void amdgpu_cs_vcn_dec_decode(void)
 307 {
 308         const unsigned dpb_size = 15923584, dt_size = 737280;
 309         uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr, sum;
 310         struct amdgpu_vcn_bo dec_buf;
 311         int size, len, i, r;
 312         uint8_t *dec;
 313
 314         size = 4*1024; /* msg */
 315         size += 4*1024; /* fb */
 316         size += 4096; /*it_scaling_table*/
 317         size += ALIGN(sizeof(uvd_bitstream), 4*1024);
 318         size += ALIGN(dpb_size, 4*1024);
 319         size += ALIGN(dt_size, 4*1024);
 320
 321         num_resources  = 0;
 322         alloc_resource(&dec_buf, size, AMDGPU_GEM_DOMAIN_GTT);
 323         resources[num_resources++] = dec_buf.handle;
 324         resources[num_resources++] = ib_handle;
 325
 326         r = amdgpu_bo_cpu_map(dec_buf.handle, (void **)&dec_buf.ptr);
 327         dec = dec_buf.ptr;
 328
 329         CU_ASSERT_EQUAL(r, 0);
 330         memset(dec_buf.ptr, 0, size);
 331         memcpy(dec_buf.ptr, vcn_dec_decode_msg, sizeof(vcn_dec_decode_msg));
 332         memcpy(dec_buf.ptr + sizeof(vcn_dec_decode_msg),
 333                         avc_decode_msg, sizeof(avc_decode_msg));
 334
 335         dec += 4*1024;
 336         dec += 4*1024;
 337         memcpy(dec, uvd_it_scaling_table, sizeof(uvd_it_scaling_table));
 338
 339         dec += 4*1024;
 340         memcpy(dec, uvd_bitstream, sizeof(uvd_bitstream));
 341
 342         dec += ALIGN(sizeof(uvd_bitstream), 4*1024);
 343
 344         dec += ALIGN(dpb_size, 4*1024);
 345
 346         msg_addr = dec_buf.addr;
 347         fb_addr = msg_addr + 4*1024;
 348         it_addr = fb_addr + 4*1024;
 349         bs_addr = it_addr + 4*1024;
 350         dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
 351         ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
 352         dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
 353
 354         len = 0;
 355         vcn_dec_cmd(msg_addr, 0x0, &len);
 356         vcn_dec_cmd(dpb_addr, 0x1, &len);
 357         vcn_dec_cmd(dt_addr, 0x2, &len);
 358         vcn_dec_cmd(fb_addr, 0x3, &len);
 359         vcn_dec_cmd(bs_addr, 0x100, &len);
 360         vcn_dec_cmd(it_addr, 0x204, &len);
 361         vcn_dec_cmd(ctx_addr, 0x206, &len);
 362
 363         ib_cpu[len++] = reg.cntl;
 364         ib_cpu[len++] = 0x1;
 365         for (; len % 16; ) {
 366                 ib_cpu[len++] = reg.nop;
 367                 ib_cpu[len++] = 0;
 368         }
 369
 370         r = submit(len, AMDGPU_HW_IP_VCN_DEC);
 371         CU_ASSERT_EQUAL(r, 0);
 372
 373         for (i = 0, sum = 0; i < dt_size; ++i)
 374                 sum += dec[i];
 375
 376         CU_ASSERT_EQUAL(sum, SUM_DECODE);
 377
 378         free_resource(&dec_buf);
 379 }
 380
 381 static void amdgpu_cs_vcn_dec_destroy(void)
 382 {
 383         struct amdgpu_vcn_bo msg_buf;
 384         int len, r;
 385
 386         num_resources  = 0;
 387         alloc_resource(&msg_buf, 1024, AMDGPU_GEM_DOMAIN_GTT);
 388         resources[num_resources++] = msg_buf.handle;
 389         resources[num_resources++] = ib_handle;
 390
 391         r = amdgpu_bo_cpu_map(msg_buf.handle, (void **)&msg_buf.ptr);
 392         CU_ASSERT_EQUAL(r, 0);
 393
 394         memset(msg_buf.ptr, 0, 1024);
 395         memcpy(msg_buf.ptr, vcn_dec_destroy_msg, sizeof(vcn_dec_destroy_msg));
 396
 397         len = 0;
 398         ib_cpu[len++] = reg.data0;
 399         ib_cpu[len++] = msg_buf.addr;
 400         ib_cpu[len++] = reg.data1;
 401         ib_cpu[len++] = msg_buf.addr >> 32;
 402         ib_cpu[len++] = reg.cmd;
 403         ib_cpu[len++] = 0;
 404         for (; len % 16; ) {
 405                 ib_cpu[len++] = reg.nop;
 406                 ib_cpu[len++] = 0;
 407         }
 408
 409         r = submit(len, AMDGPU_HW_IP_VCN_DEC);
 410         CU_ASSERT_EQUAL(r, 0);
 411
 412         free_resource(&msg_buf);
 413 }
 414
 415 static void amdgpu_cs_vcn_enc_create(void)
 416 {
 417         /* TODO */
 418 }
 419
 420 static void amdgpu_cs_vcn_enc_encode(void)
 421 {
 422         /* TODO */
 423 }
 424
 425 static void amdgpu_cs_vcn_enc_destroy(void)
 426 {
 427         /* TODO */
 428 }