tests/amdgpu/vcn: add VCN2.0 decode support

With different register offsets from VCN1.0

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

diff --git a/tests/amdgpu/vcn_tests.c b/tests/amdgpu/vcn_tests.c
index 859ec49..ad438f3 100644 (file)
--- a/tests/amdgpu/vcn_tests.c
+++ b/tests/amdgpu/vcn_tests.c
@@ -44,6 +44,14 @@ struct amdgpu_vcn_bo {
        uint8_t *ptr;
 };
 
+struct amdgpu_vcn_reg {
+       uint32_t data0;
+       uint32_t data1;
+       uint32_t cmd;
+       uint32_t nop;
+       uint32_t cntl;
+};
+
 static amdgpu_device_handle device_handle;
 static uint32_t major_version;
 static uint32_t minor_version;
@@ -57,6 +65,7 @@ static uint32_t *ib_cpu;
 
 static amdgpu_bo_handle resources[MAX_RESOURCES];
 static unsigned num_resources;
+static struct amdgpu_vcn_reg reg;
 
 static void amdgpu_cs_vcn_dec_create(void);
 static void amdgpu_cs_vcn_dec_decode(void);
@@ -96,6 +105,21 @@ CU_BOOL suite_vcn_tests_enable(void)
                return CU_FALSE;
        }
 
+       if (family_id == AMDGPU_FAMILY_RV) {
+               reg.data0 = 0x81c4;
+               reg.data1 = 0x81c5;
+               reg.cmd = 0x81c3;
+               reg.nop = 0x81ff;
+               reg.cntl = 0x81c6;
+       } else if (family_id == AMDGPU_FAMILY_NV) {
+               reg.data0 = 0x504;
+               reg.data1 = 0x505;
+               reg.cmd = 0x503;
+               reg.nop = 0x53f;
+               reg.cntl = 0x506;
+       } else
+               return CU_FALSE;
+
        return CU_TRUE;
 }
 
@@ -237,11 +261,11 @@ static void free_resource(struct amdgpu_vcn_bo *vcn_bo)
 
 static void vcn_dec_cmd(uint64_t addr, unsigned cmd, int *idx)
 {
-       ib_cpu[(*idx)++] = 0x81C4;
+       ib_cpu[(*idx)++] = reg.data0;
        ib_cpu[(*idx)++] = addr;
-       ib_cpu[(*idx)++] = 0x81C5;
+       ib_cpu[(*idx)++] = reg.data1;
        ib_cpu[(*idx)++] = addr >> 32;
-       ib_cpu[(*idx)++] = 0x81C3;
+       ib_cpu[(*idx)++] = reg.cmd;
        ib_cpu[(*idx)++] = cmd << 1;
 }
 
@@ -262,14 +286,14 @@ static void amdgpu_cs_vcn_dec_create(void)
        memcpy(msg_buf.ptr, vcn_dec_create_msg, sizeof(vcn_dec_create_msg));
 
        len = 0;
-       ib_cpu[len++] = 0x81C4;
+       ib_cpu[len++] = reg.data0;
        ib_cpu[len++] = msg_buf.addr;
-       ib_cpu[len++] = 0x81C5;
+       ib_cpu[len++] = reg.data1;
        ib_cpu[len++] = msg_buf.addr >> 32;
-       ib_cpu[len++] = 0x81C3;
+       ib_cpu[len++] = reg.cmd;
        ib_cpu[len++] = 0;
        for (; len % 16; ) {
-               ib_cpu[len++] = 0x81ff;
+               ib_cpu[len++] = reg.nop;
                ib_cpu[len++] = 0;
        }
 
@@ -336,10 +360,10 @@ static void amdgpu_cs_vcn_dec_decode(void)
        vcn_dec_cmd(it_addr, 0x204, &len);
        vcn_dec_cmd(ctx_addr, 0x206, &len);
 
-       ib_cpu[len++] = 0x81C6;
+       ib_cpu[len++] = reg.cntl;
        ib_cpu[len++] = 0x1;
        for (; len % 16; ) {
-               ib_cpu[len++] = 0x81ff;
+               ib_cpu[len++] = reg.nop;
                ib_cpu[len++] = 0;
        }
 
@@ -371,14 +395,14 @@ static void amdgpu_cs_vcn_dec_destroy(void)
        memcpy(msg_buf.ptr, vcn_dec_destroy_msg, sizeof(vcn_dec_destroy_msg));
 
        len = 0;
-       ib_cpu[len++] = 0x81C4;
+       ib_cpu[len++] = reg.data0;
        ib_cpu[len++] = msg_buf.addr;
-       ib_cpu[len++] = 0x81C5;
+       ib_cpu[len++] = reg.data1;
        ib_cpu[len++] = msg_buf.addr >> 32;
-       ib_cpu[len++] = 0x81C3;
+       ib_cpu[len++] = reg.cmd;
        ib_cpu[len++] = 0;
        for (; len % 16; ) {
-               ib_cpu[len++] = 0x81ff;
+               ib_cpu[len++] = reg.nop;
                ib_cpu[len++] = 0;
        }