/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jul 07 21:06:31 2011\r
- Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Sep 21 22:07:53 2011\r
+ Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com :NON PROFIT USER:\r
*/\r
\r
-module vga_generate ( p_reset , m_clock , pix32_data_i , v_sync_o , h_sync_o , vga_red_o , vga_green_o , vga_blue_o , h_cnt_o , ack_req_32dot , req_32dot );\r
- input p_reset;\r
+module vga_gen ( i_clk50M , m_clock , p_reset , o_vsync , o_hsync , o_vga_r , o_vga_g , o_vga_b , i_wrdata1 , i_wrdata2 , i_wradrs1 , i_wradrs2 , fi_fifo1_write , fi_fifo2_write , outled , o_vcnt );\r
+ input i_clk50M;\r
input m_clock;\r
- input [31:0] pix32_data_i;\r
- output v_sync_o;\r
- output h_sync_o;\r
- output [3:0] vga_red_o;\r
- output [3:0] vga_green_o;\r
- output [3:0] vga_blue_o;\r
- output [9:0] h_cnt_o;\r
- input ack_req_32dot;\r
- output req_32dot;\r
- wire disp_data;\r
- reg v_sync;\r
- reg h_sync;\r
- reg h_flg;\r
- reg vdata_flg;\r
- reg hdata_flg;\r
- reg [9:0] h_cnt;\r
- reg [18:0] v_cnt;\r
- reg [4:0] bit32_cnt;\r
- reg reg_flg;\r
- reg reg_cnt;\r
- reg [31:0] r1;\r
- reg [31:0] r2;\r
- reg data_select_flag;\r
- wire [3:0] red;\r
- wire [3:0] green;\r
- wire [3:0] blue;\r
- wire sel_disp_data;\r
+ input p_reset;\r
+ output o_vsync;\r
+ output o_hsync;\r
+ output [3:0] o_vga_r;\r
+ output [3:0] o_vga_g;\r
+ output [3:0] o_vga_b;\r
+ input [7:0] i_wrdata1;\r
+ input [7:0] i_wrdata2;\r
+ input [7:0] i_wradrs1;\r
+ input [7:0] i_wradrs2;\r
+ input fi_fifo1_write;\r
+ input fi_fifo2_write;\r
+ output outled;\r
+ output [9:0] o_vcnt;\r
+ wire fs_fifo1_read;\r
+ wire fs_fifo2_read;\r
+ wire fs_fifo1_exec;\r
+ wire fs_fifo2_exec;\r
+ wire fs_fifo1_reset;\r
+ wire fs_fifo2_reset;\r
+ reg [4:0] r_bit_number;\r
+ reg r_vsync;\r
+ reg r_hsync;\r
+ reg [9:0] r_vcnt;\r
+ reg [9:0] r_hcnt;\r
+ reg [25:0] cnt;\r
+ reg testled;\r
+ reg [2:0] r_outcnt;\r
+ reg [6:0] r_outclr;\r
+ reg r_vcnt_hld;\r
+ wire [23:0] w_rddata1;\r
+ wire [23:0] w_rddata2;\r
+ reg [7:0] r_rdadrs1;\r
+ reg [7:0] r_rdadrs2;\r
+ wire _u_FIFO_p_reset;\r
+ wire _u_FIFO_m_clock;\r
+ wire _u_FIFO_i_we1;\r
+ wire [7:0] _u_FIFO_i_wrdata1;\r
+ wire [7:0] _u_FIFO_i_wradrs1;\r
+ wire _u_FIFO_i_we2;\r
+ wire [7:0] _u_FIFO_i_wrdata2;\r
+ wire [7:0] _u_FIFO_i_wradrs2;\r
+ wire [23:0] _u_FIFO_o_rddata1;\r
+ wire [23:0] _u_FIFO_o_rddata2;\r
+ wire [7:0] _u_FIFO_i_rdadrs1;\r
+ wire [7:0] _u_FIFO_i_rdadrs2;\r
+ wire _u_FIFO_i_clock;\r
+ wire _u_FIFO_i_re1;\r
+ wire _u_FIFO_i_re2;\r
+ wire _u_FIFO_o_rdack1;\r
+ wire _u_FIFO_o_rdack2;\r
wire _net_0;\r
wire _net_1;\r
wire _net_2;\r
wire _net_52;\r
wire _net_53;\r
wire _net_54;\r
- wire _net_55;\r
- wire _net_56;\r
- wire _net_57;\r
- wire _net_58;\r
- wire _net_59;\r
- wire _net_60;\r
- wire _net_61;\r
- wire _net_62;\r
- wire _net_63;\r
- wire _net_64;\r
- wire _net_65;\r
- wire _net_66;\r
- wire _net_67;\r
- wire _net_68;\r
- wire _net_69;\r
+vga_ram u_FIFO (.o_rdack2(_u_FIFO_o_rdack2), .o_rdack1(_u_FIFO_o_rdack1), .i_re2(_u_FIFO_i_re2), .i_re1(_u_FIFO_i_re1), .i_clock(_u_FIFO_i_clock), .i_rdadrs2(_u_FIFO_i_rdadrs2), .i_rdadrs1(_u_FIFO_i_rdadrs1), .o_rddata2(_u_FIFO_o_rddata2), .o_rddata1(_u_FIFO_o_rddata1), .i_wradrs2(_u_FIFO_i_wradrs2), .i_wrdata2(_u_FIFO_i_wrdata2), .i_we2(_u_FIFO_i_we2), .i_wradrs1(_u_FIFO_i_wradrs1), .i_wrdata1(_u_FIFO_i_wrdata1), .i_we1(_u_FIFO_i_we1), .m_clock(_u_FIFO_m_clock), .p_reset(_u_FIFO_p_reset));\r
+\r
+ assign fs_fifo1_read = _net_22;\r
+ assign fs_fifo2_read = _net_19;\r
+ assign fs_fifo1_exec = _net_14;\r
+ assign fs_fifo2_exec = _net_12;\r
+ assign fs_fifo1_reset = _net_1;\r
+ assign fs_fifo2_reset = _net_0;\r
+ assign w_rddata1 = _u_FIFO_o_rddata1;\r
+ assign w_rddata2 = _u_FIFO_o_rddata2;\r
+ assign _u_FIFO_m_clock = m_clock;\r
+ assign _u_FIFO_i_we1 = fi_fifo1_write;\r
+ assign _u_FIFO_i_wrdata1 = i_wrdata1;\r
+ assign _u_FIFO_i_wradrs1 = i_wradrs1;\r
+ assign _u_FIFO_i_we2 = fi_fifo2_write;\r
+ assign _u_FIFO_i_wrdata2 = i_wrdata2;\r
+ assign _u_FIFO_i_wradrs2 = i_wradrs2;\r
+ assign _u_FIFO_i_rdadrs1 = r_rdadrs1;\r
+ assign _u_FIFO_i_rdadrs2 = r_rdadrs2;\r
+ assign _u_FIFO_i_clock = i_clk50M;\r
+ assign _u_FIFO_i_re1 = fs_fifo1_read;\r
+ assign _u_FIFO_i_re2 = fs_fifo2_read;\r
+ assign _net_0 = r_vcnt_hld&(~(r_vcnt[0]));\r
+ assign _net_1 = (~r_vcnt_hld)&(r_vcnt[0]);\r
+ assign _net_2 = (cnt)==(26'b01011111010111100001000000);\r
+ assign _net_3 = ~_net_2;\r
+ assign _net_4 = (r_hcnt) < (10'b1100100000);\r
+ assign _net_5 = ~_net_4;\r
+ assign _net_6 = (r_vcnt) < (10'b1000001001);\r
+ assign _net_7 = ~_net_4;\r
+ assign _net_8 = (~_net_4)&_net_6;\r
+ assign _net_9 = (~_net_4)&(~_net_6);\r
+ assign _net_10 = ((r_hcnt) < (10'b1010000000))&((r_vcnt) < (10'b0111100000));\r
+ assign _net_11 = r_vcnt[0];\r
+ assign _net_12 = _net_10&_net_11;\r
+ assign _net_13 = ~(r_vcnt[0]);\r
+ assign _net_14 = _net_10&_net_13;\r
+ assign _net_15 = (r_bit_number)==(5'b10111);\r
+ assign _net_16 = _net_10&_net_15;\r
+ assign _net_17 = r_vcnt[0];\r
+ assign _net_18 = _net_10&_net_15;\r
+ assign _net_19 = (_net_10&_net_15)&_net_17;\r
+ assign _net_20 = ~(r_vcnt[0]);\r
+ assign _net_21 = _net_10&_net_15;\r
+ assign _net_22 = (_net_10&_net_15)&_net_20;\r
+ assign _net_23 = _net_10&(~_net_15);\r
+ assign _net_24 = (r_hcnt)==(10'b1011110000);\r
+ assign _net_25 = ~_net_10;\r
+ assign _net_26 = (~_net_10)&_net_24;\r
+ assign _net_27 = (r_hcnt)==(10'b1010010000);\r
+ assign _net_28 = ~_net_10;\r
+ assign _net_29 = (~_net_10)&_net_27;\r
+ assign _net_30 = (r_hcnt)==(10'b1010000000);\r
+ assign _net_31 = ~_net_10;\r
+ assign _net_32 = (~_net_10)&_net_30;\r
+ assign _net_33 = (~_net_10)&_net_30;\r
+ assign _net_34 = (~_net_10)&_net_30;\r
+ assign _net_35 = (~_net_10)&_net_30;\r
+ assign _net_36 = (~_net_10)&_net_30;\r
+ assign _net_37 = (~_net_10)&_net_30;\r
+ assign _net_38 = (r_vcnt)==(10'b0111101100);\r
+ assign _net_39 = (r_vcnt)==(10'b0111101010);\r
+ assign _net_40 = (r_vcnt)==(10'b0111100000);\r
+ assign _net_41 = w_rddata1[r_bit_number];\r
+ assign _net_42 = fs_fifo1_exec&_net_41;\r
+ assign _net_43 = fs_fifo1_exec&_net_41;\r
+ assign _net_44 = fs_fifo1_exec&_net_41;\r
+ assign _net_45 = fs_fifo1_exec&(~_net_41);\r
+ assign _net_46 = fs_fifo1_exec&(~_net_41);\r
+ assign _net_47 = fs_fifo1_exec&(~_net_41);\r
+ assign _net_48 = w_rddata2[r_bit_number];\r
+ assign _net_49 = fs_fifo2_exec&_net_48;\r
+ assign _net_50 = fs_fifo2_exec&_net_48;\r
+ assign _net_51 = fs_fifo2_exec&_net_48;\r
+ assign _net_52 = fs_fifo2_exec&(~_net_48);\r
+ assign _net_53 = fs_fifo2_exec&(~_net_48);\r
+ assign _net_54 = fs_fifo2_exec&(~_net_48);\r
+ assign o_vsync = r_vsync;\r
+ assign o_hsync = r_hsync;\r
+ assign o_vga_r = ((_net_49|_net_42)?4'b1111:4'b0)|\r
+ ((_net_52|_net_45|_net_32)?4'b0000:4'b0);\r
+ assign o_vga_g = ((_net_50|_net_43)?4'b1111:4'b0)|\r
+ ((_net_53|_net_46|_net_33)?4'b0000:4'b0);\r
+ assign o_vga_b = ((_net_51|_net_44)?4'b1111:4'b0)|\r
+ ((_net_54|_net_47|_net_34)?4'b0000:4'b0);\r
+ assign outled = testled;\r
+ assign o_vcnt = r_vcnt;\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_bit_number <= 5'b00000;\r
+else if ((_net_23)|(_net_37|_net_16)) \r
+ r_bit_number <= ((_net_23) ?(r_bit_number)+(5'b00001):5'b0)|\r
+ ((_net_37|_net_16) ?5'b00000:5'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_vsync <= 1'b0;\r
+else if ((_net_39)|(_net_38)) \r
+ r_vsync <= ((_net_39) ?1'b0:1'b0)|\r
+ ((_net_38) ?1'b1:1'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_hsync <= 1'b0;\r
+else if ((_net_29)|(_net_26)) \r
+ r_hsync <= ((_net_29) ?1'b0:1'b0)|\r
+ ((_net_26) ?1'b1:1'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_vcnt <= 10'b0000000000;\r
+else if ((_net_9)|(_net_8)) \r
+ r_vcnt <= ((_net_9) ?10'b0000000000:10'b0)|\r
+ ((_net_8) ?(r_vcnt)+(10'b0000000001):10'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_hcnt <= 10'b0000000000;\r
+else if ((_net_5)|(_net_4)) \r
+ r_hcnt <= ((_net_5) ?10'b0000000000:10'b0)|\r
+ ((_net_4) ?(r_hcnt)+(10'b0000000001):10'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ cnt <= 26'b00000000000000000000000000;\r
+else if ((_net_3)|(_net_2)) \r
+ cnt <= ((_net_3) ?(cnt)+(26'b00000000000000000000000001):26'b0)|\r
+ ((_net_2) ?26'b00000000000000000000000000:26'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ testled <= 1'b0;\r
+else if ((_net_2)) \r
+ testled <= ~testled;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_outcnt <= 3'b000;\r
+else if ((_net_35)) \r
+ r_outcnt <= 3'b000;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_outclr <= 7'b0000000;\r
+else if ((_net_36)) \r
+ r_outclr <= 7'b0000000;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_vcnt_hld <= 1'b0;\r
+else r_vcnt_hld <= r_vcnt[0];\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_rdadrs1 <= 8'b00000000;\r
+else if ((fs_fifo1_reset)|(fs_fifo1_read)) \r
+ r_rdadrs1 <= ((fs_fifo1_reset) ?8'b00000000:8'b0)|\r
+ ((fs_fifo1_read) ?(r_rdadrs1)+(8'b00000011):8'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_rdadrs2 <= 8'b00000000;\r
+else if ((fs_fifo2_reset)|(fs_fifo2_read)) \r
+ r_rdadrs2 <= ((fs_fifo2_reset) ?8'b00000000:8'b0)|\r
+ ((fs_fifo2_read) ?(r_rdadrs2)+(8'b00000011):8'b0);\r
+\r
+end\r
+endmodule\r
+/*\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Sep 21 22:08:00 2011\r
+ Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com \r
+*/\r
+\r
+module vga_top ( p_reset , m_clock , i_sw , o_vsync , o_hsync , o_vga_r , o_vga_g , o_vga_b , o_LED );\r
+ input p_reset, m_clock;\r
+ input i_sw;\r
+ output o_vsync;\r
+ output o_hsync;\r
+ output [3:0] o_vga_r;\r
+ output [3:0] o_vga_g;\r
+ output [3:0] o_vga_b;\r
+ output [7:0] o_LED;\r
+ reg [2:0] trigger;\r
+ reg r_cnt;\r
+ reg r_reset;\r
+ reg [25:0] r_sec_cnt;\r
+ reg r_LED;\r
+ reg [13:0] r_init_cnt;\r
+ reg [13:0] r_vram_adrs1;\r
+ reg [13:0] r_vram_adrs2;\r
+ reg [15:0] r_vram_rddata;\r
+ reg [13:0] r_vram_start_adrs;\r
+ reg r_hld_vram_start;\r
+ wire [7:0] w_wrdata1;\r
+ wire [7:0] w_wrdata2;\r
+ wire [7:0] w_wradrs1;\r
+ wire [7:0] w_wradrs2;\r
+ wire fs_fifo1_write;\r
+ wire fs_fifo2_write;\r
+ wire fs_init;\r
+ wire fs_fifo1_charge;\r
+ wire fs_fifo2_charge;\r
+ wire fs_vram_cnt_inc;\r
+ reg [7:0] r_wradrs1;\r
+ reg [7:0] r_wradrs2;\r
+ wire test_write;\r
+ reg [25:0] r_wait_cnt;\r
+ reg [25:0] r_wait_val;\r
+ reg p_wait;\r
+ wire [13:0] _net_57;\r
+ wire [13:0] _net_60;\r
+ wire [13:0] _net_63;\r
+ wire [13:0] _net_66;\r
+ wire [13:0] _net_69;\r
+ wire _proc_p_wait_set;\r
+ wire _proc_p_wait_reset;\r
wire _net_70;\r
+ wire _u_VGA_i_clk50M;\r
+ wire _u_VGA_m_clock;\r
+ wire _u_VGA_p_reset;\r
+ wire _u_VGA_o_vsync;\r
+ wire _u_VGA_o_hsync;\r
+ wire [3:0] _u_VGA_o_vga_r;\r
+ wire [3:0] _u_VGA_o_vga_g;\r
+ wire [3:0] _u_VGA_o_vga_b;\r
+ wire [7:0] _u_VGA_i_wrdata1;\r
+ wire [7:0] _u_VGA_i_wrdata2;\r
+ wire [7:0] _u_VGA_i_wradrs1;\r
+ wire [7:0] _u_VGA_i_wradrs2;\r
+ wire _u_VGA_fi_fifo1_write;\r
+ wire _u_VGA_fi_fifo2_write;\r
+ wire _u_VGA_outled;\r
+ wire [9:0] _u_VGA_o_vcnt;\r
+ wire [13:0] _u_EXP_i_Radrs;\r
+ wire [15:0] _u_EXP_o_Rdata;\r
+ wire _u_EXP_fi_Rd_req;\r
+ wire _u_EXP_fo_Rd_ack;\r
+ wire [7:0] _u_EXP_i_Wdata;\r
+ wire [13:0] _u_EXP_i_Wadrs;\r
+ wire _u_EXP_fi_Wr_req;\r
+ wire _u_EXP_p_reset;\r
+ wire _u_EXP_m_clock;\r
wire _net_71;\r
wire _net_72;\r
wire _net_73;\r
wire _net_80;\r
wire _net_81;\r
wire _net_82;\r
- wire _net_83;\r
- wire _net_84;\r
- wire _net_85;\r
- wire _net_86;\r
- wire _net_87;\r
- wire _net_88;\r
- wire _net_89;\r
- wire _net_90;\r
- wire _net_91;\r
- wire _net_92;\r
- wire _net_93;\r
- wire _net_94;\r
- wire _net_95;\r
- wire _net_96;\r
- wire _net_97;\r
- wire _net_98;\r
- wire _net_99;\r
- wire _net_100;\r
+ reg _reg_83;\r
+ reg _reg_84;\r
+ reg _reg_85;\r
+ reg _reg_86;\r
+ reg _reg_87;\r
+ reg _reg_88;\r
+ reg _reg_89;\r
+ reg _reg_90;\r
+ reg _reg_91;\r
+ reg _reg_92;\r
+ reg _reg_93;\r
+ reg _reg_94;\r
+ reg _reg_95;\r
+ reg _reg_96;\r
+ reg _reg_97;\r
+ reg _reg_98;\r
+ reg _reg_99;\r
+ reg _reg_100;\r
wire _net_101;\r
+ wire _reg_86_goto;\r
wire _net_102;\r
+ wire _reg_90_goin;\r
wire _net_103;\r
wire _net_104;\r
+ wire _reg_90_goto;\r
wire _net_105;\r
+ wire _reg_85_goin;\r
wire _net_106;\r
wire _net_107;\r
wire _net_108;\r
wire _net_109;\r
+ wire _reg_93_goto;\r
wire _net_110;\r
+ wire _reg_97_goin;\r
wire _net_111;\r
wire _net_112;\r
+ wire _reg_97_goto;\r
wire _net_113;\r
+ wire _reg_92_goin;\r
wire _net_114;\r
wire _net_115;\r
wire _net_116;\r
wire _net_117;\r
+ wire _reg_99_goto;\r
wire _net_118;\r
+ wire _reg_98_goin;\r
wire _net_119;\r
wire _net_120;\r
wire _net_121;\r
wire _net_122;\r
wire _net_123;\r
wire _net_124;\r
+ wire _reg_99_goin;\r
wire _net_125;\r
wire _net_126;\r
wire _net_127;\r
wire _net_144;\r
wire _net_145;\r
wire _net_146;\r
- wire _net_147;\r
- wire _net_148;\r
- wire _net_149;\r
- wire _net_150;\r
- wire _net_151;\r
- wire _net_152;\r
- wire _net_153;\r
- wire _net_154;\r
+ reg _reg_147;\r
+ reg _reg_148;\r
+ reg _reg_149;\r
+ reg _reg_150;\r
+ reg _reg_151;\r
+ reg _reg_152;\r
+ reg _reg_153;\r
+ reg _reg_154;\r
wire _net_155;\r
wire _net_156;\r
wire _net_157;\r
+ wire _reg_149_goto;\r
wire _net_158;\r
+ wire _reg_153_goin;\r
wire _net_159;\r
wire _net_160;\r
+ wire _reg_153_goto;\r
wire _net_161;\r
+ wire _reg_148_goin;\r
wire _net_162;\r
wire _net_163;\r
wire _net_164;\r
wire _net_170;\r
wire _net_171;\r
wire _net_172;\r
- wire _net_173;\r
- wire _net_174;\r
- wire _net_175;\r
- wire _net_176;\r
- wire _net_177;\r
- wire _net_178;\r
- wire _net_179;\r
- wire _net_180;\r
- wire _net_181;\r
+ reg _reg_173;\r
+ reg _reg_174;\r
+ reg _reg_175;\r
+ reg _reg_176;\r
+ reg _reg_177;\r
+ reg _reg_178;\r
+ reg _reg_179;\r
+ reg _reg_180;\r
+ reg _reg_181;\r
wire _net_182;\r
wire _net_183;\r
wire _net_184;\r
+ wire _reg_176_goto;\r
wire _net_185;\r
+ wire _reg_180_goin;\r
wire _net_186;\r
wire _net_187;\r
+ wire _reg_180_goto;\r
wire _net_188;\r
+ wire _reg_175_goin;\r
wire _net_189;\r
wire _net_190;\r
wire _net_191;\r
wire _net_205;\r
wire _net_206;\r
wire _net_207;\r
- wire _net_208;\r
- wire _net_209;\r
- wire _net_210;\r
- wire _net_211;\r
- wire _net_212;\r
- wire _net_213;\r
- wire _net_214;\r
- wire _net_215;\r
- wire _net_216;\r
- wire _net_217;\r
- wire _net_218;\r
+exp_ctrl u_EXP (.p_reset(p_reset), .m_clock(m_clock), .fi_Wr_req(_u_EXP_fi_Wr_req), .i_Wadrs(_u_EXP_i_Wadrs), .i_Wdata(_u_EXP_i_Wdata), .fo_Rd_ack(_u_EXP_fo_Rd_ack), .fi_Rd_req(_u_EXP_fi_Rd_req), .o_Rdata(_u_EXP_o_Rdata), .i_Radrs(_u_EXP_i_Radrs));\r
+vga_gen u_VGA (.o_vcnt(_u_VGA_o_vcnt), .outled(_u_VGA_outled), .fi_fifo2_write(_u_VGA_fi_fifo2_write), .fi_fifo1_write(_u_VGA_fi_fifo1_write), .i_wradrs2(_u_VGA_i_wradrs2), .i_wradrs1(_u_VGA_i_wradrs1), .i_wrdata2(_u_VGA_i_wrdata2), .i_wrdata1(_u_VGA_i_wrdata1), .o_vga_b(_u_VGA_o_vga_b), .o_vga_g(_u_VGA_o_vga_g), .o_vga_r(_u_VGA_o_vga_r), .o_hsync(_u_VGA_o_hsync), .o_vsync(_u_VGA_o_vsync), .p_reset(_u_VGA_p_reset), .m_clock(_u_VGA_m_clock), .i_clk50M(_u_VGA_i_clk50M));\r
\r
- assign disp_data = _net_10;\r
- assign red = 4'b0000;\r
- assign green = 4'b0000;\r
- assign blue = ((_net_20)?4'b0000:4'b0)|\r
- ((_net_18)?4'b1111:4'b0);\r
- assign sel_disp_data = ((_net_218)?r2[31]:1'b0)|\r
- ((_net_215)?r2[30]:1'b0)|\r
- ((_net_212)?r2[29]:1'b0)|\r
- ((_net_209)?r2[28]:1'b0)|\r
- ((_net_206)?r2[27]:1'b0)|\r
- ((_net_203)?r2[26]:1'b0)|\r
- ((_net_200)?r2[25]:1'b0)|\r
- ((_net_197)?r2[24]:1'b0)|\r
- ((_net_194)?r2[23]:1'b0)|\r
- ((_net_191)?r2[22]:1'b0)|\r
- ((_net_188)?r2[21]:1'b0)|\r
- ((_net_185)?r2[20]:1'b0)|\r
- ((_net_182)?r2[19]:1'b0)|\r
- ((_net_179)?r2[18]:1'b0)|\r
- ((_net_176)?r2[17]:1'b0)|\r
- ((_net_173)?r2[16]:1'b0)|\r
- ((_net_170)?r2[15]:1'b0)|\r
- ((_net_167)?r2[14]:1'b0)|\r
- ((_net_164)?r2[13]:1'b0)|\r
- ((_net_161)?r2[12]:1'b0)|\r
- ((_net_158)?r2[11]:1'b0)|\r
- ((_net_155)?r2[10]:1'b0)|\r
- ((_net_152)?r2[9]:1'b0)|\r
- ((_net_149)?r2[8]:1'b0)|\r
- ((_net_146)?r2[7]:1'b0)|\r
- ((_net_143)?r2[6]:1'b0)|\r
- ((_net_140)?r2[5]:1'b0)|\r
- ((_net_137)?r2[4]:1'b0)|\r
- ((_net_134)?r2[3]:1'b0)|\r
- ((_net_131)?r2[2]:1'b0)|\r
- ((_net_128)?r2[1]:1'b0)|\r
- ((_net_124)?r2[0]:1'b0)|\r
- ((_net_121)?r1[31]:1'b0)|\r
- ((_net_118)?r1[30]:1'b0)|\r
- ((_net_115)?r1[29]:1'b0)|\r
- ((_net_112)?r1[28]:1'b0)|\r
- ((_net_109)?r1[27]:1'b0)|\r
- ((_net_106)?r1[26]:1'b0)|\r
- ((_net_103)?r1[25]:1'b0)|\r
- ((_net_100)?r1[24]:1'b0)|\r
- ((_net_97)?r1[23]:1'b0)|\r
- ((_net_94)?r1[22]:1'b0)|\r
- ((_net_91)?r1[21]:1'b0)|\r
- ((_net_88)?r1[20]:1'b0)|\r
- ((_net_85)?r1[19]:1'b0)|\r
- ((_net_82)?r1[18]:1'b0)|\r
- ((_net_79)?r1[17]:1'b0)|\r
- ((_net_76)?r1[16]:1'b0)|\r
- ((_net_73)?r1[15]:1'b0)|\r
- ((_net_70)?r1[14]:1'b0)|\r
- ((_net_67)?r1[13]:1'b0)|\r
- ((_net_64)?r1[12]:1'b0)|\r
- ((_net_61)?r1[11]:1'b0)|\r
- ((_net_58)?r1[10]:1'b0)|\r
- ((_net_55)?r1[9]:1'b0)|\r
- ((_net_52)?r1[8]:1'b0)|\r
- ((_net_49)?r1[7]:1'b0)|\r
- ((_net_46)?r1[6]:1'b0)|\r
- ((_net_43)?r1[5]:1'b0)|\r
- ((_net_40)?r1[4]:1'b0)|\r
- ((_net_37)?r1[3]:1'b0)|\r
- ((_net_34)?r1[2]:1'b0)|\r
- ((_net_31)?r1[1]:1'b0)|\r
- ((_net_27)?r1[0]:1'b0);\r
- assign _net_0 = (h_cnt)==(10'b1100100000);\r
- assign _net_1 = (h_cnt)==(10'b1100001110);\r
- assign _net_2 = (h_cnt)==(10'b0010001110);\r
- assign _net_3 = (h_cnt)==(10'b0001100000);\r
- assign _net_4 = (((~_net_0)&(~_net_1))&(~_net_2))&(~_net_3);\r
- assign _net_5 = (v_cnt)==(19'b1100101110000011111);\r
- assign _net_6 = (v_cnt)==(19'b1100011110011011111);\r
- assign _net_7 = (v_cnt)==(19'b0000110000011011111);\r
- assign _net_8 = (v_cnt)==(19'b0000000011000111111);\r
- assign _net_9 = (((~_net_5)&(~_net_6))&(~_net_7))&(~_net_8);\r
- assign _net_10 = hdata_flg&vdata_flg;\r
- assign _net_11 = (((h_cnt) >= ((10'b0010001110)+(10'b1001100001)))&((h_cnt) <= (((10'b1100001110)+(10'b1001100001))+(10'b1111111111))))&((v_cnt) >= ((19'b0000110000011011111)+(19'b1111111111111100001)))&((v_cnt) <= (((19'b1100011110011011111)+(19'b1111111111111100001))+(19'b1111111111111111111)));\r
- assign _net_12 = (bit32_cnt)==(5'b00000);\r
- assign _net_13 = _net_11&_net_12;\r
- assign _net_14 = (bit32_cnt)==(5'b11111);\r
- assign _net_15 = _net_11&_net_14;\r
- assign _net_16 = _net_11&(~_net_14);\r
- assign _net_17 = ~_net_11;\r
- assign _net_18 = hdata_flg&vdata_flg;\r
- assign _net_19 = ~_net_18;\r
- assign _net_20 = ~_net_18;\r
- assign _net_21 = ~_net_18;\r
- assign _net_22 = ack_req_32dot&data_select_flag;\r
- assign _net_23 = ack_req_32dot&(~data_select_flag);\r
- assign _net_24 = ~reg_flg;\r
- assign _net_25 = (bit32_cnt)==(5'b11111);\r
- assign _net_26 = disp_data&_net_24;\r
- assign _net_27 = (disp_data&_net_24)&_net_25;\r
- assign _net_28 = (disp_data&_net_24)&_net_25;\r
- assign _net_29 = (bit32_cnt)==(5'b11110);\r
- assign _net_30 = disp_data&_net_24;\r
- assign _net_31 = (disp_data&_net_24)&_net_29;\r
- assign _net_32 = (bit32_cnt)==(5'b11101);\r
- assign _net_33 = disp_data&_net_24;\r
- assign _net_34 = (disp_data&_net_24)&_net_32;\r
- assign _net_35 = (bit32_cnt)==(5'b11100);\r
- assign _net_36 = disp_data&_net_24;\r
- assign _net_37 = (disp_data&_net_24)&_net_35;\r
- assign _net_38 = (bit32_cnt)==(5'b11011);\r
- assign _net_39 = disp_data&_net_24;\r
- assign _net_40 = (disp_data&_net_24)&_net_38;\r
- assign _net_41 = (bit32_cnt)==(5'b11010);\r
- assign _net_42 = disp_data&_net_24;\r
- assign _net_43 = (disp_data&_net_24)&_net_41;\r
- assign _net_44 = (bit32_cnt)==(5'b11001);\r
- assign _net_45 = disp_data&_net_24;\r
- assign _net_46 = (disp_data&_net_24)&_net_44;\r
- assign _net_47 = (bit32_cnt)==(5'b11000);\r
- assign _net_48 = disp_data&_net_24;\r
- assign _net_49 = (disp_data&_net_24)&_net_47;\r
- assign _net_50 = (bit32_cnt)==(5'b10111);\r
- assign _net_51 = disp_data&_net_24;\r
- assign _net_52 = (disp_data&_net_24)&_net_50;\r
- assign _net_53 = (bit32_cnt)==(5'b10110);\r
- assign _net_54 = disp_data&_net_24;\r
- assign _net_55 = (disp_data&_net_24)&_net_53;\r
- assign _net_56 = (bit32_cnt)==(5'b10101);\r
- assign _net_57 = disp_data&_net_24;\r
- assign _net_58 = (disp_data&_net_24)&_net_56;\r
- assign _net_59 = (bit32_cnt)==(5'b10100);\r
- assign _net_60 = disp_data&_net_24;\r
- assign _net_61 = (disp_data&_net_24)&_net_59;\r
- assign _net_62 = (bit32_cnt)==(5'b10011);\r
- assign _net_63 = disp_data&_net_24;\r
- assign _net_64 = (disp_data&_net_24)&_net_62;\r
- assign _net_65 = (bit32_cnt)==(5'b10010);\r
- assign _net_66 = disp_data&_net_24;\r
- assign _net_67 = (disp_data&_net_24)&_net_65;\r
- assign _net_68 = (bit32_cnt)==(5'b10001);\r
- assign _net_69 = disp_data&_net_24;\r
- assign _net_70 = (disp_data&_net_24)&_net_68;\r
- assign _net_71 = (bit32_cnt)==(5'b10000);\r
- assign _net_72 = disp_data&_net_24;\r
- assign _net_73 = (disp_data&_net_24)&_net_71;\r
- assign _net_74 = (bit32_cnt)==(5'b01111);\r
- assign _net_75 = disp_data&_net_24;\r
- assign _net_76 = (disp_data&_net_24)&_net_74;\r
- assign _net_77 = (bit32_cnt)==(5'b01110);\r
- assign _net_78 = disp_data&_net_24;\r
- assign _net_79 = (disp_data&_net_24)&_net_77;\r
- assign _net_80 = (bit32_cnt)==(5'b01101);\r
- assign _net_81 = disp_data&_net_24;\r
- assign _net_82 = (disp_data&_net_24)&_net_80;\r
- assign _net_83 = (bit32_cnt)==(5'b01100);\r
- assign _net_84 = disp_data&_net_24;\r
- assign _net_85 = (disp_data&_net_24)&_net_83;\r
- assign _net_86 = (bit32_cnt)==(5'b01011);\r
- assign _net_87 = disp_data&_net_24;\r
- assign _net_88 = (disp_data&_net_24)&_net_86;\r
- assign _net_89 = (bit32_cnt)==(5'b01010);\r
- assign _net_90 = disp_data&_net_24;\r
- assign _net_91 = (disp_data&_net_24)&_net_89;\r
- assign _net_92 = (bit32_cnt)==(5'b01001);\r
- assign _net_93 = disp_data&_net_24;\r
- assign _net_94 = (disp_data&_net_24)&_net_92;\r
- assign _net_95 = (bit32_cnt)==(5'b01000);\r
- assign _net_96 = disp_data&_net_24;\r
- assign _net_97 = (disp_data&_net_24)&_net_95;\r
- assign _net_98 = (bit32_cnt)==(5'b00111);\r
- assign _net_99 = disp_data&_net_24;\r
- assign _net_100 = (disp_data&_net_24)&_net_98;\r
- assign _net_101 = (bit32_cnt)==(5'b00110);\r
- assign _net_102 = disp_data&_net_24;\r
- assign _net_103 = (disp_data&_net_24)&_net_101;\r
- assign _net_104 = (bit32_cnt)==(5'b00101);\r
- assign _net_105 = disp_data&_net_24;\r
- assign _net_106 = (disp_data&_net_24)&_net_104;\r
- assign _net_107 = (bit32_cnt)==(5'b00100);\r
- assign _net_108 = disp_data&_net_24;\r
- assign _net_109 = (disp_data&_net_24)&_net_107;\r
- assign _net_110 = (bit32_cnt)==(5'b00011);\r
- assign _net_111 = disp_data&_net_24;\r
- assign _net_112 = (disp_data&_net_24)&_net_110;\r
- assign _net_113 = (bit32_cnt)==(5'b00010);\r
- assign _net_114 = disp_data&_net_24;\r
- assign _net_115 = (disp_data&_net_24)&_net_113;\r
- assign _net_116 = (bit32_cnt)==(5'b00001);\r
- assign _net_117 = disp_data&_net_24;\r
- assign _net_118 = (disp_data&_net_24)&_net_116;\r
- assign _net_119 = (bit32_cnt)==(5'b00000);\r
- assign _net_120 = disp_data&_net_24;\r
- assign _net_121 = (disp_data&_net_24)&_net_119;\r
- assign _net_122 = (bit32_cnt)==(5'b11111);\r
- assign _net_123 = disp_data&(~_net_24);\r
- assign _net_124 = (disp_data&(~_net_24))&_net_122;\r
- assign _net_125 = (disp_data&(~_net_24))&_net_122;\r
- assign _net_126 = (bit32_cnt)==(5'b11110);\r
- assign _net_127 = disp_data&(~_net_24);\r
- assign _net_128 = (disp_data&(~_net_24))&_net_126;\r
- assign _net_129 = (bit32_cnt)==(5'b11101);\r
- assign _net_130 = disp_data&(~_net_24);\r
- assign _net_131 = (disp_data&(~_net_24))&_net_129;\r
- assign _net_132 = (bit32_cnt)==(5'b11100);\r
- assign _net_133 = disp_data&(~_net_24);\r
- assign _net_134 = (disp_data&(~_net_24))&_net_132;\r
- assign _net_135 = (bit32_cnt)==(5'b11011);\r
- assign _net_136 = disp_data&(~_net_24);\r
- assign _net_137 = (disp_data&(~_net_24))&_net_135;\r
- assign _net_138 = (bit32_cnt)==(5'b11010);\r
- assign _net_139 = disp_data&(~_net_24);\r
- assign _net_140 = (disp_data&(~_net_24))&_net_138;\r
- assign _net_141 = (bit32_cnt)==(5'b11001);\r
- assign _net_142 = disp_data&(~_net_24);\r
- assign _net_143 = (disp_data&(~_net_24))&_net_141;\r
- assign _net_144 = (bit32_cnt)==(5'b11000);\r
- assign _net_145 = disp_data&(~_net_24);\r
- assign _net_146 = (disp_data&(~_net_24))&_net_144;\r
- assign _net_147 = (bit32_cnt)==(5'b10111);\r
- assign _net_148 = disp_data&(~_net_24);\r
- assign _net_149 = (disp_data&(~_net_24))&_net_147;\r
- assign _net_150 = (bit32_cnt)==(5'b10110);\r
- assign _net_151 = disp_data&(~_net_24);\r
- assign _net_152 = (disp_data&(~_net_24))&_net_150;\r
- assign _net_153 = (bit32_cnt)==(5'b10101);\r
- assign _net_154 = disp_data&(~_net_24);\r
- assign _net_155 = (disp_data&(~_net_24))&_net_153;\r
- assign _net_156 = (bit32_cnt)==(5'b10100);\r
- assign _net_157 = disp_data&(~_net_24);\r
- assign _net_158 = (disp_data&(~_net_24))&_net_156;\r
- assign _net_159 = (bit32_cnt)==(5'b10011);\r
- assign _net_160 = disp_data&(~_net_24);\r
- assign _net_161 = (disp_data&(~_net_24))&_net_159;\r
- assign _net_162 = (bit32_cnt)==(5'b10010);\r
- assign _net_163 = disp_data&(~_net_24);\r
- assign _net_164 = (disp_data&(~_net_24))&_net_162;\r
- assign _net_165 = (bit32_cnt)==(5'b10001);\r
- assign _net_166 = disp_data&(~_net_24);\r
- assign _net_167 = (disp_data&(~_net_24))&_net_165;\r
- assign _net_168 = (bit32_cnt)==(5'b10000);\r
- assign _net_169 = disp_data&(~_net_24);\r
- assign _net_170 = (disp_data&(~_net_24))&_net_168;\r
- assign _net_171 = (bit32_cnt)==(5'b01111);\r
- assign _net_172 = disp_data&(~_net_24);\r
- assign _net_173 = (disp_data&(~_net_24))&_net_171;\r
- assign _net_174 = (bit32_cnt)==(5'b01110);\r
- assign _net_175 = disp_data&(~_net_24);\r
- assign _net_176 = (disp_data&(~_net_24))&_net_174;\r
- assign _net_177 = (bit32_cnt)==(5'b01101);\r
- assign _net_178 = disp_data&(~_net_24);\r
- assign _net_179 = (disp_data&(~_net_24))&_net_177;\r
- assign _net_180 = (bit32_cnt)==(5'b01100);\r
- assign _net_181 = disp_data&(~_net_24);\r
- assign _net_182 = (disp_data&(~_net_24))&_net_180;\r
- assign _net_183 = (bit32_cnt)==(5'b01011);\r
- assign _net_184 = disp_data&(~_net_24);\r
- assign _net_185 = (disp_data&(~_net_24))&_net_183;\r
- assign _net_186 = (bit32_cnt)==(5'b01010);\r
- assign _net_187 = disp_data&(~_net_24);\r
- assign _net_188 = (disp_data&(~_net_24))&_net_186;\r
- assign _net_189 = (bit32_cnt)==(5'b01001);\r
- assign _net_190 = disp_data&(~_net_24);\r
- assign _net_191 = (disp_data&(~_net_24))&_net_189;\r
- assign _net_192 = (bit32_cnt)==(5'b01000);\r
- assign _net_193 = disp_data&(~_net_24);\r
- assign _net_194 = (disp_data&(~_net_24))&_net_192;\r
- assign _net_195 = (bit32_cnt)==(5'b00111);\r
- assign _net_196 = disp_data&(~_net_24);\r
- assign _net_197 = (disp_data&(~_net_24))&_net_195;\r
- assign _net_198 = (bit32_cnt)==(5'b00110);\r
- assign _net_199 = disp_data&(~_net_24);\r
- assign _net_200 = (disp_data&(~_net_24))&_net_198;\r
- assign _net_201 = (bit32_cnt)==(5'b00101);\r
- assign _net_202 = disp_data&(~_net_24);\r
- assign _net_203 = (disp_data&(~_net_24))&_net_201;\r
- assign _net_204 = (bit32_cnt)==(5'b00100);\r
- assign _net_205 = disp_data&(~_net_24);\r
- assign _net_206 = (disp_data&(~_net_24))&_net_204;\r
- assign _net_207 = (bit32_cnt)==(5'b00011);\r
- assign _net_208 = disp_data&(~_net_24);\r
- assign _net_209 = (disp_data&(~_net_24))&_net_207;\r
- assign _net_210 = (bit32_cnt)==(5'b00010);\r
- assign _net_211 = disp_data&(~_net_24);\r
- assign _net_212 = (disp_data&(~_net_24))&_net_210;\r
- assign _net_213 = (bit32_cnt)==(5'b00001);\r
- assign _net_214 = disp_data&(~_net_24);\r
- assign _net_215 = (disp_data&(~_net_24))&_net_213;\r
- assign _net_216 = (bit32_cnt)==(5'b00000);\r
- assign _net_217 = disp_data&(~_net_24);\r
- assign _net_218 = (disp_data&(~_net_24))&_net_216;\r
- assign v_sync_o = v_sync;\r
- assign h_sync_o = h_sync;\r
- assign vga_red_o = red;\r
- assign vga_green_o = green;\r
- assign vga_blue_o = blue;\r
- assign h_cnt_o = h_cnt;\r
- assign req_32dot = _net_13;\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- v_sync <= 1'b0;\r
-else if ((_net_8|_net_5)) \r
- v_sync <= ~v_sync;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- h_sync <= 1'b0;\r
-else if ((_net_3|_net_0)) \r
- h_sync <= ~h_sync;\r
+ assign w_wrdata1 = ((_reg_150|_reg_95)?r_vram_rddata[15:8]:8'b0)|\r
+ ((_reg_151|_reg_94)?r_vram_rddata[7:0]:8'b0);\r
+ assign w_wrdata2 = ((_reg_177|_reg_88)?r_vram_rddata[15:8]:8'b0)|\r
+ ((_reg_178|_reg_87)?r_vram_rddata[7:0]:8'b0);\r
+ assign w_wradrs1 = r_wradrs1;\r
+ assign w_wradrs2 = r_wradrs2;\r
+ assign fs_fifo1_write = _reg_151|_reg_150|_reg_95|_reg_94;\r
+ assign fs_fifo2_write = _reg_178|_reg_177|_reg_88|_reg_87;\r
+ assign fs_init = _net_71;\r
+ assign fs_fifo1_charge = _net_76;\r
+ assign fs_fifo2_charge = _net_80;\r
+ assign fs_vram_cnt_inc = _reg_173;\r
+ assign test_write = 1'b0;\r
+ assign _net_57 = (r_init_cnt)+(14'b00000000000001);\r
+ assign _net_60 = (r_init_cnt)+(14'b00000000000001);\r
+ assign _net_63 = (r_init_cnt)+(14'b00000000000001);\r
+ assign _net_66 = (r_init_cnt)+(14'b00000000000001);\r
+ assign _net_69 = (r_init_cnt)+(14'b00000000000001);\r
+ assign _proc_p_wait_set = 1'b0;\r
+ assign _proc_p_wait_reset = _net_206;\r
+ assign _net_70 = _proc_p_wait_set|_proc_p_wait_reset;\r
+ assign _u_VGA_i_clk50M = m_clock;\r
+ assign _u_VGA_m_clock = r_cnt;\r
+ assign _u_VGA_p_reset = r_reset;\r
+ assign _u_VGA_i_wrdata1 = w_wrdata1;\r
+ assign _u_VGA_i_wrdata2 = w_wrdata2;\r
+ assign _u_VGA_i_wradrs1 = w_wradrs1;\r
+ assign _u_VGA_i_wradrs2 = w_wradrs2;\r
+ assign _u_VGA_fi_fifo1_write = fs_fifo1_write;\r
+ assign _u_VGA_fi_fifo2_write = fs_fifo2_write;\r
+ assign _u_EXP_i_Radrs = ((_net_164|_net_116)?r_vram_adrs1:14'b0)|\r
+ ((_net_191|_net_108)?r_vram_adrs2:14'b0);\r
+ assign _u_EXP_fi_Rd_req = _net_190|_net_163|_net_115|_net_107;\r
+ assign _u_EXP_i_Wdata = r_init_cnt[7:0];\r
+ assign _u_EXP_i_Wadrs = r_init_cnt;\r
+ assign _u_EXP_fi_Wr_req = _net_126;\r
+ assign _net_71 = (trigger)==(3'b011);\r
+ assign _net_72 = ~r_reset;\r
+ assign _net_73 = (~r_hld_vram_start)&(_u_VGA_o_vcnt[0]);\r
+ assign _net_74 = (_u_VGA_o_vcnt) < (10'b0111100000);\r
+ assign _net_75 = _net_72&_net_73;\r
+ assign _net_76 = (_net_72&_net_73)&_net_74;\r
+ assign _net_77 = r_hld_vram_start&(~(_u_VGA_o_vcnt[0]));\r
+ assign _net_78 = (_u_VGA_o_vcnt) < (10'b0111100000);\r
+ assign _net_79 = _net_72&_net_77;\r
+ assign _net_80 = (_net_72&_net_77)&_net_78;\r
+ assign _net_81 = (r_sec_cnt)==(26'b10111110101111000010000000);\r
+ assign _net_82 = ~_net_81;\r
+ assign _net_101 = (_net_63) < (14'b00000000101000);\r
+ assign _reg_86_goto = _net_102;\r
+ assign _net_102 = _reg_86&_net_101;\r
+ assign _reg_90_goin = _net_103;\r
+ assign _net_103 = _reg_86&_net_101;\r
+ assign _net_104 = ~((r_init_cnt) < (14'b00000000101000));\r
+ assign _reg_90_goto = _net_105;\r
+ assign _net_105 = _reg_90&_net_104;\r
+ assign _reg_85_goin = _net_106;\r
+ assign _net_106 = _reg_90&_net_104;\r
+ assign _net_107 = _reg_90&(~_net_104);\r
+ assign _net_108 = _reg_90&(~_net_104);\r
+ assign _net_109 = (_net_60) < (14'b00000000101000);\r
+ assign _reg_93_goto = _net_110;\r
+ assign _net_110 = _reg_93&_net_109;\r
+ assign _reg_97_goin = _net_111;\r
+ assign _net_111 = _reg_93&_net_109;\r
+ assign _net_112 = ~((r_init_cnt) < (14'b00000000101000));\r
+ assign _reg_97_goto = _net_113;\r
+ assign _net_113 = _reg_97&_net_112;\r
+ assign _reg_92_goin = _net_114;\r
+ assign _net_114 = _reg_97&_net_112;\r
+ assign _net_115 = _reg_97&(~_net_112);\r
+ assign _net_116 = _reg_97&(~_net_112);\r
+ assign _net_117 = ~((r_init_cnt) < (14'b10010110000000));\r
+ assign _reg_99_goto = _net_124|_net_118;\r
+ assign _net_118 = _reg_99&_net_117;\r
+ assign _reg_98_goin = _net_119;\r
+ assign _net_119 = _reg_99&_net_117;\r
+ assign _net_120 = _reg_99&(~_net_117);\r
+ assign _net_121 = _reg_99&(~_net_117);\r
+ assign _net_122 = (_net_57) < (14'b10010110000000);\r
+ assign _net_123 = _reg_99&(~_net_117);\r
+ assign _net_124 = (_reg_99&(~_net_117))&_net_122;\r
+ assign _reg_99_goin = _net_125;\r
+ assign _net_125 = (_reg_99&(~_net_117))&_net_122;\r
+ assign _net_126 = _reg_99&(~_net_117);\r
+ assign _net_127 = _reg_99&(~_net_117);\r
+ assign _net_128 = _reg_99&(~_net_117);\r
+ assign _net_129 = fs_init|_reg_100;\r
+ assign _net_130 = (_reg_99_goin|fs_init)|_reg_99|_reg_100;\r
+ assign _net_131 = _reg_98_goin|_reg_98|_reg_99;\r
+ assign _net_132 = _reg_97_goin|_reg_97|_reg_98;\r
+ assign _net_133 = _reg_97_goin|_reg_96|_reg_97;\r
+ assign _net_134 = _reg_97_goin|_reg_95|_reg_96;\r
+ assign _net_135 = _reg_97_goin|_reg_94|_reg_95;\r
+ assign _net_136 = _reg_97_goin|_reg_93|_reg_94;\r
+ assign _net_137 = _reg_92_goin|_reg_92|_reg_93;\r
+ assign _net_138 = _reg_92_goin|_reg_91|_reg_92;\r
+ assign _net_139 = _reg_90_goin|_reg_90|_reg_91;\r
+ assign _net_140 = _reg_90_goin|_reg_89|_reg_90;\r
+ assign _net_141 = _reg_90_goin|_reg_88|_reg_89;\r
+ assign _net_142 = _reg_90_goin|_reg_87|_reg_88;\r
+ assign _net_143 = _reg_90_goin|_reg_86|_reg_87;\r
+ assign _net_144 = _reg_85_goin|_reg_85|_reg_86;\r
+ assign _net_145 = _reg_85_goin|_reg_84|_reg_85;\r
+ assign _net_146 = _reg_85_goin|_reg_83|_reg_84;\r
+ assign _net_155 = (r_vram_adrs1)==(14'b10010110000000);\r
+ assign _net_156 = _reg_147&_net_155;\r
+ assign _net_157 = (_net_66) < (14'b00000000101000);\r
+ assign _reg_149_goto = _net_158;\r
+ assign _net_158 = _reg_149&_net_157;\r
+ assign _reg_153_goin = _net_159;\r
+ assign _net_159 = _reg_149&_net_157;\r
+ assign _net_160 = ~((r_init_cnt) < (14'b00000000101000));\r
+ assign _reg_153_goto = _net_161;\r
+ assign _net_161 = _reg_153&_net_160;\r
+ assign _reg_148_goin = _net_162;\r
+ assign _net_162 = _reg_153&_net_160;\r
+ assign _net_163 = _reg_153&(~_net_160);\r
+ assign _net_164 = _reg_153&(~_net_160);\r
+ assign _net_165 = fs_fifo1_charge|_reg_154;\r
+ assign _net_166 = (_reg_153_goin|fs_fifo1_charge)|_reg_153|_reg_154;\r
+ assign _net_167 = (_reg_153_goin|fs_fifo1_charge)|_reg_152|_reg_153;\r
+ assign _net_168 = (_reg_153_goin|fs_fifo1_charge)|_reg_151|_reg_152;\r
+ assign _net_169 = (_reg_153_goin|fs_fifo1_charge)|_reg_150|_reg_151;\r
+ assign _net_170 = (_reg_153_goin|fs_fifo1_charge)|_reg_149|_reg_150;\r
+ assign _net_171 = _reg_148_goin|_reg_148|_reg_149;\r
+ assign _net_172 = _reg_148_goin|_reg_147|_reg_148;\r
+ assign _net_182 = (r_vram_adrs2)==(14'b10010110000000);\r
+ assign _net_183 = _reg_174&_net_182;\r
+ assign _net_184 = (_net_69) < (14'b00000000101000);\r
+ assign _reg_176_goto = _net_185;\r
+ assign _net_185 = _reg_176&_net_184;\r
+ assign _reg_180_goin = _net_186;\r
+ assign _net_186 = _reg_176&_net_184;\r
+ assign _net_187 = ~((r_init_cnt) < (14'b00000000101000));\r
+ assign _reg_180_goto = _net_188;\r
+ assign _net_188 = _reg_180&_net_187;\r
+ assign _reg_175_goin = _net_189;\r
+ assign _net_189 = _reg_180&_net_187;\r
+ assign _net_190 = _reg_180&(~_net_187);\r
+ assign _net_191 = _reg_180&(~_net_187);\r
+ assign _net_192 = fs_fifo2_charge|_reg_181;\r
+ assign _net_193 = (_reg_180_goin|fs_fifo2_charge)|_reg_180|_reg_181;\r
+ assign _net_194 = (_reg_180_goin|fs_fifo2_charge)|_reg_179|_reg_180;\r
+ assign _net_195 = (_reg_180_goin|fs_fifo2_charge)|_reg_178|_reg_179;\r
+ assign _net_196 = (_reg_180_goin|fs_fifo2_charge)|_reg_177|_reg_178;\r
+ assign _net_197 = (_reg_180_goin|fs_fifo2_charge)|_reg_176|_reg_177;\r
+ assign _net_198 = _reg_175_goin|_reg_175|_reg_176;\r
+ assign _net_199 = _reg_175_goin|_reg_174|_reg_175;\r
+ assign _net_200 = _reg_175_goin|_reg_173|_reg_174;\r
+ assign _net_201 = (r_vram_start_adrs)==(14'b10010101011000);\r
+ assign _net_202 = fs_vram_cnt_inc&_net_201;\r
+ assign _net_203 = fs_vram_cnt_inc&(~_net_201);\r
+ assign _net_204 = (r_wait_cnt)==(r_wait_val);\r
+ assign _net_205 = p_wait&_net_204;\r
+ assign _net_206 = p_wait&_net_204;\r
+ assign _net_207 = p_wait&(~_net_204);\r
+ assign o_vsync = _u_VGA_o_vsync;\r
+ assign o_hsync = _u_VGA_o_hsync;\r
+ assign o_vga_r = _u_VGA_o_vga_r;\r
+ assign o_vga_g = _u_VGA_o_vga_g;\r
+ assign o_vga_b = _u_VGA_o_vga_b;\r
+ assign o_LED = {5'b00000,i_sw,r_LED,_u_VGA_outled};\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ trigger <= 3'b000;\r
+else trigger <= {trigger[1:0],1'b1};\r
end\r
-always @(posedge p_reset)\r
- begin\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
if (p_reset)\r
- h_flg <= 1'b0;\r
+ r_cnt <= 1'b0;\r
+else r_cnt <= ~r_cnt;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- vdata_flg <= 1'b0;\r
-else if ((_net_7)|(_net_6)) \r
- vdata_flg <= ((_net_7) ?1'b1:1'b0)|\r
- ((_net_6) ?1'b0:1'b0);\r
+ r_reset <= 1'b1;\r
+else if ((_reg_83)) \r
+ r_reset <= 1'b0;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_sec_cnt <= 26'b00000000000000000000000000;\r
+else if ((_net_82)|(_net_81)) \r
+ r_sec_cnt <= ((_net_82) ?(r_sec_cnt)+(26'b00000000000000000000000001):26'b0)|\r
+ ((_net_81) ?26'b00000000000000000000000000:26'b0);\r
\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- hdata_flg <= 1'b0;\r
-else if ((_net_2)|(_net_1)) \r
- hdata_flg <= ((_net_2) ?1'b1:1'b0)|\r
- ((_net_1) ?1'b0:1'b0);\r
+ r_LED <= 1'b0;\r
+else if ((_net_81)) \r
+ r_LED <= ~r_LED;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_init_cnt <= 14'b00000000000000;\r
+else if ((_reg_176)|(_reg_149)|(_net_120)|(_reg_93)|(_net_192|_net_165|_net_129|_reg_98|_reg_91)|(_reg_86)) \r
+ r_init_cnt <= ((_reg_176) ?_net_69:14'b0)|\r
+ ((_reg_149) ?_net_66:14'b0)|\r
+ ((_net_120) ?_net_57:14'b0)|\r
+ ((_reg_93) ?_net_60:14'b0)|\r
+ ((_net_192|_net_165|_net_129|_reg_98|_reg_91) ?14'b00000000000000:14'b0)|\r
+ ((_reg_86) ?_net_63:14'b0);\r
\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- h_cnt <= 10'b0000000000;\r
-else if ((_net_4|_net_3|_net_2|_net_1)|(_net_0)) \r
- h_cnt <= ((_net_4|_net_3|_net_2|_net_1) ?(h_cnt)+(10'b0000000001):10'b0)|\r
- ((_net_0) ?10'b0000000000:10'b0);\r
+ r_vram_adrs1 <= 14'b00000000000000;\r
+else if ((_net_156)|(_reg_149|_reg_93)) \r
+ r_vram_adrs1 <= ((_net_156) ?14'b00000000000000:14'b0)|\r
+ ((_reg_149|_reg_93) ?(r_vram_adrs1)+(14'b00000000000001):14'b0);\r
\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- v_cnt <= 19'b0000000000000000000;\r
-else if ((_net_9|_net_8|_net_7|_net_6)|(_net_5)) \r
- v_cnt <= ((_net_9|_net_8|_net_7|_net_6) ?(v_cnt)+(19'b0000000000000000001):19'b0)|\r
- ((_net_5) ?19'b0000000000000000000:19'b0);\r
+ r_vram_adrs2 <= 14'b00000000000000;\r
+else if ((_net_183)|(_reg_176|_reg_86)) \r
+ r_vram_adrs2 <= ((_net_183) ?14'b00000000000000:14'b0)|\r
+ ((_reg_176|_reg_86) ?(r_vram_adrs2)+(14'b00000000000001):14'b0);\r
\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- bit32_cnt <= 5'b00000;\r
-else if ((disp_data)|(_net_16)|(_net_17|_net_15)) \r
- bit32_cnt <= ((disp_data) ?(bit32_cnt)+(5'b00001):5'b0)|\r
- ((_net_16) ?(bit32_cnt)+(5'b00001):5'b0)|\r
- ((_net_17|_net_15) ?5'b00000:5'b0);\r
+ r_vram_rddata <= 16'b0000000000000000;\r
+else if ((_reg_179|_reg_152|_reg_96|_reg_89)) \r
+ r_vram_rddata <= _u_EXP_o_Rdata;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_vram_start_adrs <= 14'b00000000000000;\r
+else if ((_net_202)|(_net_203|_reg_84)) \r
+ r_vram_start_adrs <= ((_net_202) ?14'b00000000000000:14'b0)|\r
+ ((_net_203|_reg_84) ?(r_vram_start_adrs)+(14'b00000000101000):14'b0);\r
\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- reg_flg <= 1'b0;\r
-else if ((_net_125|_net_28)) \r
- reg_flg <= ~reg_flg;\r
+ r_hld_vram_start <= 1'b0;\r
+else r_hld_vram_start <= _u_VGA_o_vcnt[0];\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_wradrs1 <= 8'b00000000;\r
+else if ((_reg_151|_reg_150|_reg_95|_reg_94)|(_reg_148|_reg_92)) \r
+ r_wradrs1 <= ((_reg_151|_reg_150|_reg_95|_reg_94) ?(r_wradrs1)+(8'b00000001):8'b0)|\r
+ ((_reg_148|_reg_92) ?8'b00000000:8'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_wradrs2 <= 8'b00000000;\r
+else if ((_reg_178|_reg_177|_reg_88|_reg_87)|(_reg_175|_reg_85)) \r
+ r_wradrs2 <= ((_reg_178|_reg_177|_reg_88|_reg_87) ?(r_wradrs2)+(8'b00000001):8'b0)|\r
+ ((_reg_175|_reg_85) ?8'b00000000:8'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_wait_cnt <= 26'b00000000000000000000000000;\r
+else if ((_net_207)|(_net_205)) \r
+ r_wait_cnt <= ((_net_207) ?(r_wait_cnt)+(26'b00000000000000000000000001):26'b0)|\r
+ ((_net_205) ?26'b00000000000000000000000000:26'b0);\r
+\r
end\r
always @(posedge p_reset)\r
begin\r
if (p_reset)\r
- reg_cnt <= 1'b0;\r
+ r_wait_val <= 26'b00000000000000000000000000;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- r1 <= 32'b00000000000000000000000000000000;\r
-else if ((_net_22)) \r
- r1 <= pix32_data_i;\r
+ p_wait <= 1'b0;\r
+else if ((_net_70)) \r
+ p_wait <= _proc_p_wait_set;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- r2 <= 32'b00000000000000000000000000000000;\r
-else if ((_net_23)) \r
- r2 <= pix32_data_i;\r
+ _reg_83 <= 1'b0;\r
+else if ((_net_146)) \r
+ _reg_83 <= _reg_84;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- data_select_flag <= 1'b0;\r
-else if ((ack_req_32dot)) \r
- data_select_flag <= ~data_select_flag;\r
+ _reg_84 <= 1'b0;\r
+else if ((_net_145)) \r
+ _reg_84 <= _reg_85;\r
end\r
-endmodule\r
-/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jul 07 21:06:36 2011\r
- Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
-*/\r
-\r
-module vga_top ( p_reset , m_clock , o_v_sync , o_h_sync , o_red , o_green , o_blue , o_LED );\r
- input p_reset, m_clock;\r
- output o_v_sync;\r
- output o_h_sync;\r
- output [3:0] o_red;\r
- output [3:0] o_green;\r
- output [3:0] o_blue;\r
- output [7:0] o_LED;\r
- reg r_cnt;\r
- reg [2:0] r_reset;\r
- reg [14:0] r_line_cnt;\r
- reg [13:0] r_line_cnt2;\r
- reg [13:0] r_vram_adrs_cnt;\r
- reg [24:0] r_Sec_cnt;\r
- reg r_Init_flag;\r
- reg [7:0] r_LED;\r
- reg r_test_LED;\r
- reg [7:0] line_buff1 [0:79];\r
- reg [7:0] line_buff2 [0:79];\r
- wire fs_vga_sys_init;\r
- wire [14:0] _net_221;\r
- wire _u_VGA_p_reset;\r
- wire _u_VGA_m_clock;\r
- wire [31:0] _u_VGA_pix32_data_i;\r
- wire _u_VGA_v_sync_o;\r
- wire _u_VGA_h_sync_o;\r
- wire [3:0] _u_VGA_vga_red_o;\r
- wire [3:0] _u_VGA_vga_green_o;\r
- wire [3:0] _u_VGA_vga_blue_o;\r
- wire [9:0] _u_VGA_h_cnt_o;\r
- wire _u_VGA_ack_req_32dot;\r
- wire _u_VGA_req_32dot;\r
- wire [13:0] _U_EXP_iRadrs;\r
- wire [15:0] _U_EXP_oRdata;\r
- wire _U_EXP_fiRd_req;\r
- wire _U_EXP_foRd_ack;\r
- wire [7:0] _U_EXP_iWdata;\r
- wire [13:0] _U_EXP_iWadrs;\r
- wire _U_EXP_fiWr_req;\r
- wire _U_EXP_p_reset;\r
- wire _U_EXP_m_clock;\r
- wire _net_222;\r
- wire _net_223;\r
- wire _net_224;\r
- wire _net_225;\r
- wire _net_226;\r
- wire _net_227;\r
- wire _net_228;\r
- wire _net_229;\r
- wire _net_230;\r
- wire _net_231;\r
- wire _net_232;\r
- wire _net_233;\r
- reg _reg_234;\r
- reg _reg_235;\r
- reg _reg_236;\r
- reg _reg_237;\r
- wire _net_238;\r
- wire _reg_235_goto;\r
- wire _net_239;\r
- wire _reg_236_goin;\r
- wire _net_240;\r
- wire _net_241;\r
- wire _reg_236_goto;\r
- wire _net_242;\r
- wire _reg_234_goin;\r
- wire _net_243;\r
- wire _net_244;\r
- wire _net_245;\r
- wire _net_246;\r
- wire _net_247;\r
- wire _net_248;\r
- wire _net_249;\r
- wire _net_250;\r
-exp_ctrl U_EXP (.p_reset(p_reset), .m_clock(m_clock), .fiWr_req(_U_EXP_fiWr_req), .iWadrs(_U_EXP_iWadrs), .iWdata(_U_EXP_iWdata), .foRd_ack(_U_EXP_foRd_ack), .fiRd_req(_U_EXP_fiRd_req), .oRdata(_U_EXP_oRdata), .iRadrs(_U_EXP_iRadrs));\r
-vga_generate u_VGA (.req_32dot(_u_VGA_req_32dot), .ack_req_32dot(_u_VGA_ack_req_32dot), .h_cnt_o(_u_VGA_h_cnt_o), .vga_blue_o(_u_VGA_vga_blue_o), .vga_green_o(_u_VGA_vga_green_o), .vga_red_o(_u_VGA_vga_red_o), .h_sync_o(_u_VGA_h_sync_o), .v_sync_o(_u_VGA_v_sync_o), .pix32_data_i(_u_VGA_pix32_data_i), .m_clock(_u_VGA_m_clock), .p_reset(_u_VGA_p_reset));\r
-\r
- assign fs_vga_sys_init = _net_222;\r
- assign _net_221 = (r_line_cnt)+(15'b000000000000001);\r
- assign _u_VGA_p_reset = r_reset[2];\r
- assign _u_VGA_m_clock = r_cnt;\r
- assign _u_VGA_pix32_data_i = 32'b11111111111111111111111111111111;\r
- assign _u_VGA_ack_req_32dot = _u_VGA_req_32dot;\r
- assign _U_EXP_iRadrs = r_line_cnt2;\r
- assign _U_EXP_fiRd_req = _net_224;\r
- assign _U_EXP_iWdata = 8'b11110000;\r
- assign _U_EXP_iWadrs = r_line_cnt[13:0];\r
- assign _U_EXP_fiWr_req = _net_244;\r
- assign _net_222 = (r_reset)==(3'b100);\r
- assign _net_223 = (r_Sec_cnt)==(25'b0111110101111000010000000);\r
- assign _net_224 = r_Init_flag&_net_223;\r
- assign _net_225 = r_Init_flag&_net_223;\r
- assign _net_226 = r_Init_flag&_net_223;\r
- assign _net_227 = r_Init_flag&_net_223;\r
- assign _net_228 = (r_line_cnt2)==(14'b00001111101000);\r
- assign _net_229 = r_Init_flag&_net_223;\r
- assign _net_230 = (r_Init_flag&_net_223)&_net_228;\r
- assign _net_231 = (r_Init_flag&_net_223)&(~_net_228);\r
- assign _net_232 = r_Init_flag&(~_net_223);\r
- assign _net_233 = ~r_Init_flag;\r
- assign _net_238 = (_net_221) < (15'b100000000000000);\r
- assign _reg_235_goto = _net_239;\r
- assign _net_239 = _reg_235&_net_238;\r
- assign _reg_236_goin = _net_240;\r
- assign _net_240 = _reg_235&_net_238;\r
- assign _net_241 = ~((r_line_cnt) < (15'b100000000000000));\r
- assign _reg_236_goto = _net_242;\r
- assign _net_242 = _reg_236&_net_241;\r
- assign _reg_234_goin = _net_243;\r
- assign _net_243 = _reg_236&_net_241;\r
- assign _net_244 = _reg_236&(~_net_241);\r
- assign _net_245 = _reg_236&(~_net_241);\r
- assign _net_246 = _reg_236&(~_net_241);\r
- assign _net_247 = fs_vga_sys_init|_reg_237;\r
- assign _net_248 = (_reg_236_goin|fs_vga_sys_init)|_reg_236|_reg_237;\r
- assign _net_249 = (_reg_236_goin|fs_vga_sys_init)|_reg_235|_reg_236;\r
- assign _net_250 = _reg_234_goin|_reg_234|_reg_235;\r
- assign o_v_sync = _u_VGA_v_sync_o;\r
- assign o_h_sync = _u_VGA_h_sync_o;\r
- assign o_red = _u_VGA_vga_red_o;\r
- assign o_green = _u_VGA_vga_green_o;\r
- assign o_blue = _u_VGA_vga_blue_o;\r
- assign o_LED = r_LED;\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- r_cnt <= 1'b0;\r
-else r_cnt <= ~r_cnt;\r
+ _reg_85 <= 1'b0;\r
+else if ((_net_144)) \r
+ _reg_85 <= _reg_85_goin|(_reg_86&(~_reg_86_goto));\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- r_reset <= 3'b111;\r
-else r_reset <= {r_reset[1:0],1'b0};\r
+ _reg_86 <= 1'b0;\r
+else if ((_net_143)) \r
+ _reg_86 <= _reg_87;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- r_line_cnt <= 15'b000000000000000;\r
-else if ((_net_247)|(_reg_235)) \r
- r_line_cnt <= ((_net_247) ?15'b000000000000000:15'b0)|\r
- ((_reg_235) ?_net_221:15'b0);\r
-\r
+ _reg_87 <= 1'b0;\r
+else if ((_net_142)) \r
+ _reg_87 <= _reg_88;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- r_line_cnt2 <= 14'b00000000000000;\r
-else if ((_net_231)|(_net_230)) \r
- r_line_cnt2 <= ((_net_231) ?(r_line_cnt2)+(14'b00000000000001):14'b0)|\r
- ((_net_230) ?14'b00000000000000:14'b0);\r
-\r
+ _reg_88 <= 1'b0;\r
+else if ((_net_141)) \r
+ _reg_88 <= _reg_89;\r
end\r
-always @(posedge p_reset)\r
- begin\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
if (p_reset)\r
- r_vram_adrs_cnt <= 14'b00000000000000;\r
+ _reg_89 <= 1'b0;\r
+else if ((_net_140)) \r
+ _reg_89 <= _reg_90&(~_reg_90_goto);\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- r_Sec_cnt <= 25'b0000000000000000000000000;\r
-else if ((_net_232)|(_net_233|_net_226)) \r
- r_Sec_cnt <= ((_net_232) ?(r_Sec_cnt)+(25'b0000000000000000000000001):25'b0)|\r
- ((_net_233|_net_226) ?25'b0000000000000000000000000:25'b0);\r
-\r
+ _reg_90 <= 1'b0;\r
+else if ((_net_139)) \r
+ _reg_90 <= _reg_90_goin|_reg_91;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_91 <= 1'b0;\r
+else if ((_net_138)) \r
+ _reg_91 <= _reg_92;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_92 <= 1'b0;\r
+else if ((_net_137)) \r
+ _reg_92 <= _reg_92_goin|(_reg_93&(~_reg_93_goto));\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_93 <= 1'b0;\r
+else if ((_net_136)) \r
+ _reg_93 <= _reg_94;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_94 <= 1'b0;\r
+else if ((_net_135)) \r
+ _reg_94 <= _reg_95;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_95 <= 1'b0;\r
+else if ((_net_134)) \r
+ _reg_95 <= _reg_96;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_96 <= 1'b0;\r
+else if ((_net_133)) \r
+ _reg_96 <= _reg_97&(~_reg_97_goto);\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_97 <= 1'b0;\r
+else if ((_net_132)) \r
+ _reg_97 <= _reg_97_goin|_reg_98;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_98 <= 1'b0;\r
+else if ((_net_131)) \r
+ _reg_98 <= _reg_98_goin|(_reg_99&(~_reg_99_goto));\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_99 <= 1'b0;\r
+else if ((_net_130)) \r
+ _reg_99 <= (_reg_99_goin|_reg_100)|fs_init;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_100 <= 1'b0;\r
+else if ((_reg_100)) \r
+ _reg_100 <= 1'b0;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_147 <= 1'b0;\r
+else if ((_net_172)) \r
+ _reg_147 <= _reg_148;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_148 <= 1'b0;\r
+else if ((_net_171)) \r
+ _reg_148 <= _reg_148_goin|(_reg_149&(~_reg_149_goto));\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_149 <= 1'b0;\r
+else if ((_net_170)) \r
+ _reg_149 <= _reg_150;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_150 <= 1'b0;\r
+else if ((_net_169)) \r
+ _reg_150 <= _reg_151;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_151 <= 1'b0;\r
+else if ((_net_168)) \r
+ _reg_151 <= _reg_152;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_152 <= 1'b0;\r
+else if ((_net_167)) \r
+ _reg_152 <= _reg_153&(~_reg_153_goto);\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_153 <= 1'b0;\r
+else if ((_net_166)) \r
+ _reg_153 <= (_reg_153_goin|_reg_154)|fs_fifo1_charge;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_154 <= 1'b0;\r
+else if ((_reg_154)) \r
+ _reg_154 <= 1'b0;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_173 <= 1'b0;\r
+else if ((_net_200)) \r
+ _reg_173 <= _reg_174;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_174 <= 1'b0;\r
+else if ((_net_199)) \r
+ _reg_174 <= _reg_175;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- r_Init_flag <= 1'b0;\r
-else if ((_reg_234)) \r
- r_Init_flag <= 1'b1;\r
+ _reg_175 <= 1'b0;\r
+else if ((_net_198)) \r
+ _reg_175 <= _reg_175_goin|(_reg_176&(~_reg_176_goto));\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- r_LED <= 8'b00000000;\r
-else if ((_U_EXP_foRd_ack)) \r
- r_LED <= {_U_EXP_oRdata[10],_U_EXP_oRdata[8],_U_EXP_oRdata[6],_U_EXP_oRdata[4],_U_EXP_oRdata[2],_U_EXP_oRdata[0],r_test_LED,r_Init_flag};\r
+ _reg_176 <= 1'b0;\r
+else if ((_net_197)) \r
+ _reg_176 <= _reg_177;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- r_test_LED <= 1'b0;\r
-else if ((_net_227)) \r
- r_test_LED <= ~r_test_LED;\r
+ _reg_177 <= 1'b0;\r
+else if ((_net_196)) \r
+ _reg_177 <= _reg_178;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_234 <= 1'b0;\r
-else if ((_net_250)) \r
- _reg_234 <= _reg_234_goin|(_reg_235&(~_reg_235_goto));\r
+ _reg_178 <= 1'b0;\r
+else if ((_net_195)) \r
+ _reg_178 <= _reg_179;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_235 <= 1'b0;\r
-else if ((_net_249)) \r
- _reg_235 <= _reg_236&(~_reg_236_goto);\r
+ _reg_179 <= 1'b0;\r
+else if ((_net_194)) \r
+ _reg_179 <= _reg_180&(~_reg_180_goto);\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_236 <= 1'b0;\r
-else if ((_net_248)) \r
- _reg_236 <= (_reg_236_goin|_reg_237)|fs_vga_sys_init;\r
+ _reg_180 <= 1'b0;\r
+else if ((_net_193)) \r
+ _reg_180 <= (_reg_180_goin|_reg_181)|fs_fifo2_charge;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_237 <= 1'b0;\r
-else if ((_reg_237)) \r
- _reg_237 <= 1'b0;\r
+ _reg_181 <= 1'b0;\r
+else if ((_reg_181)) \r
+ _reg_181 <= 1'b0;\r
end\r
endmodule\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jul 07 21:06:37 2011\r
- Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Sep 21 22:08:07 2011\r
+ Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com \r
*/\r
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