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SDRAM設計開始
authoryujiro_kaeko <zyangalianhamster01@gmail.com>
Sat, 15 Oct 2011 02:18:48 +0000 (11:18 +0900)
committeryujiro_kaeko <zyangalianhamster01@gmail.com>
Sat, 15 Oct 2011 02:18:48 +0000 (11:18 +0900)
commit23256c98d672dc9af875a61d7e97cb3d994db9ba
tree02937d9aec55c47cd3000896127b3426e921ec0b
parente2c2509f158d5dba4981529b62824510d2780e6f
SDRAM設計開始
ALTERA Cyclone VI
PLLの逓倍回路50MHz->100MHz
動作確認コード

Change-Id: I5f264b8a174442108a05d1b6bb060614606e6433
14 files changed:
VGADisplay/SDRAMC_src/PLLU.nsh [new file with mode: 0644]
VGADisplay/SDRAMC_src/SDRAMC.nsl [new file with mode: 0644]
VGADisplay/SDRAMC_src/SDRAM_top.nsl [new file with mode: 0644]
VGADisplay/SDRAMC_src/btn_ctrl.nsl [new file with mode: 0644]
VGADisplay/Verilog/SDRAM_top.v [new file with mode: 0644]
VGADisplay/Verilog/exp_ctrl.v
VGADisplay/Verilog/from_ctrl.v
VGADisplay/Verilog/vga_gen.v
VGADisplay/Verilog/vga_top.v
VGADisplay/Verilog/vram.v
VGADisplay/Verilog/vram_ctrl.v
VGADisplay/src/vga_generate.nsh [deleted file]
VGADisplay/src/vga_generate.nsl [deleted file]
VGADisplay/src/vga_top.nsl