-#include "vram.nsh"
+/**
+* VRAM Control Module
+* Module name is "vram_ctrl"
+* @author zyanham
+* @version 1.0
+* Comment : Reading Steiner
+*/
-declare vram_ctrl interface {
- input m_clock ;
- input p_reset ;
+#include "vram.nsh"
- input wrdata_i[8] ;
- input rdaddress_i[14] ;
- input wraddress_i[14] ;
- output rddata_o[8] ;
+declare vram_ctrl {
- func_in read_req( rdaddress_i ) ;
- func_out read_ack( rddata_o ) ;
+ input i_Wdata[8] ; // in Write Data
+ input i_Wadrs[14] ; // in Write Address
+ input i_Radrs[14] ; // in Read Address
+ output o_Rdata[8] ; // out Read Data
+ func_in fi_Wr_req( i_Wadrs, i_Wdata ) ;
+ func_in fi_Rd_req( i_Radrs ) ;
+ func_out fo_Rd_ack( o_Rdata ) ;
}
module vram_ctrl{
- vram U_VRAM ;
+ vram u_VRAM ;
+
+ reg r_Radrs_hld[14] = 0 ;
+
+ {
+ u_VRAM.clock = m_clock ;
+
+ /* Memory Terminal Assign */
+
+ if(~fi_Wr_req) {
+ u_VRAM.wren = 0 ;
+ }
+ }
+
+ func fi_Wr_req {
+ u_VRAM.wren = 1 ;
+ u_VRAM.data = i_Wdata ;
+ u_VRAM.wraddress = i_Wadrs ;
+ }
- /* Assign */
- U_VRAM.clock = m_clock ;
- U_VRAM.data = wrdata_i ;
- U_VRAM.rdaddress = rdaddress_i ;
- U_VRAM.wraddress = wraddress_i ;
-// U_VRAM.wren = wren_i ;
- rddata_o = U_VRAM.q ;
+ func fi_Rd_req seq {
+ u_VRAM.rdaddress = i_Radrs ;
+ {
+ u_VRAM.rdaddress = r_Radrs_hld ;
+ fo_Rd_ack( u_VRAM.q ) ;
+ }
+ }
}
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