clock enabler update

[motonesfpga/motonesfpga.git] / de0_cv_nes / mos6502-timing.sdc

diff --git a/de0_cv_nes/mos6502-timing.sdc b/de0_cv_nes/mos6502-timing.sdc
index 99896b8..87fa99a 100644 (file)
--- a/de0_cv_nes/mos6502-timing.sdc
+++ b/de0_cv_nes/mos6502-timing.sdc
@@ -1,3 +1,3 @@
-create_clock -name base_clock -period 10 [get_ports {base_clk}]\r
+create_clock -name base_clock -period 20 [get_ports {base_clk}]\r
 #create_generated_clock -name cpu_clock -source [get_ports {base_clk}] -divide_by 24 -invert [get_registers {clock_divider:clock_inst|cpu_clk_wk}]\r
 #create_generated_clock -name emu_ppu_clock -source [get_ports {base_clk}] -divide_by 4 -invert [get_registers {clock_divider:clock_inst|counter_register:cpu_clk_cnt|d_flip_flop:counter_reg_inst|q[1]}]\r