clock enabler update

[motonesfpga/motonesfpga.git] / de0_cv_nes / simulation / modelsim / de0_cv_nes_run_msim_rtl_vhdl.do

diff --git a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
index bc1eabb..6b90a4c 100644 (file)
--- a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
+++ b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
@@ -15,20 +15,21 @@ vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -
 ##script custom part...\r
 \r
 \r
-#add wave -label rst_n sim:/testbench_motones_sim/sim_board/pi_rst_n;\r
+add wave -label rst_n sim:/testbench_motones_sim/sim_board/pi_rst_n;\r
 #add wave -label r_nw sim:/testbench_motones_sim/sim_board/wr_r_nw;\r
-#add wave -label base_clk sim:/testbench_motones_sim/sim_board/pi_base_clk;\r
+add wave -label base_clk sim:/testbench_motones_sim/sim_board/pi_base_clk;\r
 \r
 #add wave sim:/testbench_motones_sim/*;\r
 #add wave sim:/testbench_motones_sim/sim_board/*;\r
-add wave sim:/testbench_motones_sim/sim_board/chip_selector_inst/*;\r
+add wave sim:/testbench_motones_sim/sim_board/chip_selector_inst/reg_cpu_en;\r
+add wave sim:/testbench_motones_sim/sim_board/chip_selector_inst/reg_ppu_en;\r
 \r
 \r
 view structure\r
 view signals\r
 \r
-run 8 us\r
-run 100 us\r
+run 300 ns\r
 wave zoom full\r
 \r
+run 5 us\r
 \r